CN106549662B

CN106549662B - A kind of multi-mode programmable counter and its implementation, frequency divider

Info

Publication number: CN106549662B
Application number: CN201610934256.9A
Authority: CN
Inventors: 黄兆磊
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2016-10-31
Filing date: 2016-10-31
Publication date: 2019-07-09
Anticipated expiration: 2036-10-31
Also published as: CN106549662A

Abstract

The present invention discloses a kind of multi-mode programmable counter and its implementation, frequency divider, is related to frequency splitting technology field, to solve the problems, such as that multi-mode programmable counter in the prior art can not realize high-frequency work.The multi-mode programmable counter includes: that can set counter, count status detection circuit, first control signal generator, initial set unit and n set unit；Wherein initial set unit is for generating at least one of initial set signal or initial reverse phase set signal, and n set unit is for generating the 1st set signal to the n-th set signal and the 1st reverse phase set signal to the n-th reverse phase set signal；Counter can be set for according to initial set signal, initial reverse phase set signal, at least one signal of the 1st set signal to the n-th set signal and the 1st reverse phase set signal into the n-th reverse phase set signal, carry out multiple clock cycle to set several operations.Multi-mode programmable counter provided by the invention is for dividing.

Description

A kind of multi-mode programmable counter and its implementation, frequency divider

Technical field

The present invention relates to frequency splitting technology field more particularly to a kind of multi-mode programmable counter and its implementation, frequency dividing Device.

Background technique

With the continuous development of wireless communication technology, multimode transceiver using more and more extensive, frequency synthesizer is received as multimode Key modules in hair machine can generate the signal of various different frequencies using PHASE-LOCKED LOOP PLL TECHNIQUE；And it is different in order to adapt to Crystal oscillator, and carrier signal is provided for the channel of different agreement, frequency synthesizer is requested to have wider frequency dividing ratio range.Due to above-mentioned lock Phaselocked loop employed in phase loop technique includes frequency divider, therefore is wanted based on the above-mentioned wide frequency dividing ratio range proposed to frequency synthesizer It asks, it is necessary to which the frequency divider of use can satisfy the requirement of high speed, wide frequency dividing ratio.

Referring to Fig. 1, widely used frequency divider includes: that dual-modulus prescaler 91, multimode can be compiled in the prior art Journey counter 93 and gulp down counter 92；Wherein the output of dual-modulus prescaler 91 is multi-mode programmable counter 93 and gulps down counter 92 provide fractional frequency signal, and multi-mode programmable counter 93 meets frequency requirement for being divided and being exported to fractional frequency signal Target fractional frequency signal.Enabling minimum frequency dividing ratio achieved by dual-modulus prescaler 91 is M², then M is smaller, and minimum frequency dividing ratio is smaller, Corresponding frequency dividing ratio range is bigger, so that the noiseproof feature of frequency divider is better.Since the bimodulus selected in frequency divider is pre- The frequency dividing ratio range of frequency divider 91 is bigger, it is desirable to which the working frequency that multi-mode programmable counter 93 can satisfy is higher, and shows There is the multi-mode programmable counter 93 in technology to be also unable to satisfy the requirement of higher operational frequency.

Summary of the invention

The present invention provides a kind of multi-mode programmable counter and its implementation, frequency divider, to meet the need of high-frequency work It asks.

In order to achieve the above objectives, the present invention adopts the following technical scheme:

In a first aspect, the present invention provides a kind of multi-mode programmable counter, comprising: counter can be set, for connecing respectively Preset division signal and clock signal are received, and counting operation is carried out according to the preset division signal and the clock signal, it is defeated Count value out；It is coupled to the count status detection circuit that can set counter, the count status detection circuit is for examining It surveys whether the count value is equal to default first object numerical value, and exports first detection signal；It is coupled to the count status inspection The first control signal generator of slowdown monitoring circuit, the first control signal generator for receive the first detection signal, just Beginning M signal and feedback signal, and initial holding signal is generated according to the initial M signal and the feedback signal, then Initial input, which is generated, according to the initial holding signal and the first detection signal controls signal, the initial M signal packet It includes: initial at least one of set signal or initial reverse phase set signal；It is coupled to the first control signal generator Initial set unit, the initial set unit are used to control signal and the clock signal according to the initial input, generate The initial M signal；Setting circuit, including cascade n set unit, the n set unit are used for according to described first Beginning M signal and the clock signal, or according to the initial holding signal and the clock signal, generate n set signal And n reverse phase set signal, wherein the n set signal includes: the 1st set signal to the n-th set signal, and the n is a Reverse phase set signal includes: the 1st reverse phase set signal to the n-th reverse phase set signal, and n is positive integer, in the n set unit The set unit that grade is associated in rearmost position generates the 1st set signal and the 1st reverse phase set signal, the 1st set Signal or the 1st reverse phase set signal are the feedback signal；The counter of setting is also used to initially be set according to described Position signal, the initial reverse phase set signal, the 1st set signal to the n-th set signal and the 1st reverse phase At least one signal of set signal into the n-th reverse phase set signal, carry out multiple clock cycle sets several operations.

In the case where the series that can set frequency unit included by counter determines, counter completion can be set and set number Time required for operating is just corresponding determining.Since multi-mode programmable counter in the prior art only includes one for producing The set unit of raw set signal, this allows for the set signal generated and is merely able to continue in several operating times in determining setting One clock cycle, so that the set signal can set counter when control can set counter and set number operation It is merely able to complete to set several operations within a clock cycle, therefore causes the working frequency of multi-mode programmable counter lower.This Inventive embodiments provide multi-mode programmable counter in, including count status detection circuit, first control signal generator, just Beginning set unit and setting circuit, and first control signal generator respectively with count status detection circuit, initial set list Member and setting circuit are coupled, and initial holding signal can be generated according to initial M signal and feedback signal, further according to It is initial that signal and first detection signal is kept to generate initial input control signal；Since feedback signal is by setting circuit cascade Therefore (i.e. feedback signal is ultimately produced by setting circuit) that set unit in rearmost position generates is fed back generating Before signal, first control signal generator can generate initial input according only to initial M signal and first detection signal Signal is controlled, and so that initial set unit is controlled signal according to the initial input and exports initial M signal, during this The initial M signal of output or the initial input for keeping signal as setting circuit, control setting circuit export corresponding signal, Until setting circuit generates feedback signal, first control signal generator is further according to initial M signal, the first detection letter Number and these three signals of feedback signal generate corresponding initial input and control signal, and control setting circuit output corresponding signal.

According to above-mentioned analytic process it is found that multi-mode programmable counter provided in an embodiment of the present invention can pass through the first control Signal generator, initial set unit and setting circuit processed control the initial M signal exported by initial set unit, and Enable to initial set unit set several periods (determine set in several times) output can continue multiple clock cycle just Beginning M signal.Moreover, the output of setting circuit will receive initial M signal or the initial influence for keeping signal, i.e., by set Equally there may be signals in n set signal of circuit output and n reverse phase set signal can be to set several period lasts more A clock cycle.Therefore, can set counter can be according to initial set signal, initial reverse phase set signal, the 1st set signal To at least one signal of the n-th set signal and the 1st reverse phase set signal into the n-th reverse phase set signal, when carrying out multiple The clock period sets several operations, improves working frequency, so that the working frequency with higher of multi-mode programmable counter 1, Improve the operating rate of multi-mode programmable counter 1.

In addition, when counter can be set according to initial set signal, initial reverse phase set signal, the 1st set signal to n-th The multiple signals of set signal and the 1st reverse phase set signal into the n-th reverse phase set signal, when carrying out setting number operation, quite It is grouped in whole frequency units that counter includes will can be set, and the different corresponding frequency dividings for controlling different groups of signal Unit.Compared with controlling whole frequency units with signal, multiple signals control multiple groups frequency units, are equivalent to that reduce can Set counter completion set number operate required for the time, and by multiple signals control can set counter set number operation and Several release operations are set, can set the frequency unit in counter can carry out setting several operations simultaneously, improve multi-mode programmable meter The operating rate of number device, to further improve the working frequency of multi-mode programmable counter.Moreover, being controlled by multiple signals Whole frequency units in counter can be set, it is thus also avoided that whole frequency dividings in counter can be only set by a signal control The excessive problem of the signal load that unit occurs.

With reference to first aspect, n-th of set list in the first implementation of first aspect, in the setting circuit It is first to be coupled with the initial set unit, n-th of the set unit be used for according to the initial M signal and it is described when Clock signal exports at least one signal in the n-th set signal or the n-th reverse phase set signal；In n set unit I-th of set unit be coupled with i+1 set unit, i-th of the set unit be used for according to the clock signal At least one signal in the i-th set signal or the i-th reverse phase set signal is generated with i+1 M signal；Among the i+1 Signal includes: at least one of i+1 set signal or i+1 reverse phase set signal；The value of i subtracts every time since n-1 1, until being recycled to i=1；Or, i-th of the set unit is coupled with the first control signal generator, described i-th Set unit is used to keep signal according to the clock signal and i-th, generates in the i-th set signal or the i-th reverse phase set signal At least one signal；The first control signal generator is also used to according to letter among the feedback signal and the i+1 Number, it generates described i-th and keeps signal, and the i-th holding signal is supplied to i-th of the set unit；The value of i is from n- 1 starts, and subtracts 1 every time, until being recycled to i=1.

The specific structure and connection type of setting circuit provided by the invention are varied, can be realized respective logic function ?.Moreover, when i-th of set unit is coupled with first control signal generator, and the i-th set signal is for making that number can be set When counter set number operation, can by controlling the generation time of the 1st set signal, to control the i-th set signal, thus Control can set the time that counter set number operation；It carries out setting several behaviour when there is the control of multiple signals that can set counter in this way When making, multiple signals can be led to by the control of feedback signal when can set counter will carry out counting operation Cross feedback signal and control each target set signal and stop output, thus avoid well terminate in previous target set signal it is defeated After out, adjacent latter set signal does not complete also and sets several situations, avoids the occurrence of the problem of logic operation mistake.

With reference to first aspect, n-th of set list in second of implementation of first aspect, in the setting circuit It is first to be coupled with the first control signal generator, n-th of the set unit be used for according to initial the holdings signal with The clock signal exports at least one signal in the n-th set signal or the n-th reverse phase set signal；N set I-th of set unit in unit is coupled with i+1 set unit, i-th of the set unit be used for according to it is described when Clock signal and i+1 M signal generate at least one signal in the i-th set signal or the i-th reverse phase set signal；Described i-th + 1 M signal includes: at least one of i+1 set signal or i+1 reverse phase set signal；The value of i since n-1, Subtract 1 every time, until being recycled to i=1；Or, i-th of the set unit is coupled with the first control signal generator, institute I-th of set unit is stated for keeping signal according to the clock signal and i-th, generates the i-th set signal or the i-th reverse phase set At least one signal in signal；The first control signal generator is also used to according to the feedback signal and the i+1 M signal generates described i-th and keeps signal, and the i-th holding signal is supplied to i-th of the set unit；I's takes Value subtracts 1 every time since n-1, until being recycled to i=1.

Second of implementation of the first implementation or first aspect with reference to first aspect, the of first aspect In three kinds of implementations, the counter of setting includes cascade multiple frequency units, when the counter of setting is used for According to the initial set signal, the initial reverse phase set signal, the 1st set signal to the n-th set signal, with And multiple signals of the 1st reverse phase set signal into the n-th reverse phase set signal, carry out multiple clock cycle sets number When operation, at least one frequency unit in counter can be set described in the corresponding control of each signal and carries out setting several operations, and is each The frequency unit of the corresponding control of a signal is not identical.

Counter provided by the invention of setting includes cascade multiple frequency units, and can pass through multiple frequency units It realizes countdown operation and sets several operations.

Second of implementation of the first implementation or first aspect with reference to first aspect, the of first aspect In four kinds of implementations, the first control signal generator is used for the 1st set signal and the initial reverse phase set Signal carries out logic or operation and logical not operation, obtains the initial holding signal；The first control signal generator It is also used to carry out logic or operation and logical not operation to the initial holding signal and the first detection signal, obtains institute State initial input control signal；Or, the first control signal generator is used to carry out logic NOT fortune to the 1st set signal It calculates, obtains the 1st reverse phase set signal, then logical AND fortune is carried out to the 1st reverse phase set signal and initial set signal Calculation and logical not operation, obtain the initial holding signal；The first control signal generator is also used to described initial It keeps signal and the first detection signal to carry out logic and operation and logical not operation, obtains the initial input control letter Number.

The type of first control signal generator provided by the invention is varied, can by different logical operations come Realize its function.

Second of implementation of the first implementation or first aspect with reference to first aspect, the of first aspect In five kinds of implementations, the first control signal generator is also used to carry out logical not operation to the feedback signal, obtains Inverted feedback signal, then carry out logic and operation to the inverted feedback signal and the i+1 set signal obtains described the I keeps signal；Or, the first control signal generator is also used to carry out logical not operation to the i+1 set signal, obtain Logic or operation are carried out to i+1 reverse phase set signal, then to the i+1 reverse phase set signal and the feedback signal, is obtained Signal is kept to described i-th.

The type of the corresponding part for generating the i-th holding signal is a variety of more in first control signal generator provided by the invention Sample can realize its function by different logical operations.

With reference to first aspect, in the 6th kind of implementation of first aspect, when the count status detection circuit detects When being equal to default first object numerical value to the count value, the first detection signal of the count status detection circuit output For high level signal, when the count status detection circuit detects the count value not equal to the default first object numerical value When, the first detection signal of the count status detection circuit output is low level signal；Or, when the count status is examined When slowdown monitoring circuit detects that the count value is equal to default first object numerical value, described the of the count status detection circuit output One detection signal is low level signal, when the count status detection circuit detects the count value not equal to described default the When one target value, the first detection signal of the count status detection circuit output is high level signal.

The low and high level of first detection signal can be set according to actual needs, need to only be met when count value is equal in advance If when first object numerical value, the corresponding level of first detection signal, and when count value is not equal to default first object numerical value, the The corresponding level of one detection signal is not identical.

With reference to first aspect, in the 7th kind of implementation of first aspect, the count status detection circuit is also used to Whether it is equal to default second target value, output the second detection signal according to the count value；The multi-mode programmable counter Further include: it is coupled to the second control signal generator of the count status detection circuit, the second control signal generator For receiving the second detection signal, window M signal and the feedback signal, and according to the window M signal and The feedback signal generates window and keeps signal, keeps signal and the second detection signal to generate window further according to the window Input control signal, the window M signal include: at least one of time window signal or phase reversal time window signal； It is coupled to the time window generator of the second control signal generator, the time window generator is used for according to the window Mouth input control signal and the clock signal, generate the window M signal.

Above-mentioned time window generator and second control signal generator cooperating pass through the 1st set signal of control Generation time can accurately control the output duration of time window signal and phase reversal time window signal, this makes it possible to Generate accurate time window signal and phase reversal time window signal according to actual needs for using.

The 7th kind of implementation with reference to first aspect, in the 8th kind of implementation of first aspect, second control Signal generator processed is used to carry out logic or operation and logic to the 1st set signal and the phase reversal time window signal Inverse obtains the window and keeps signal；The second control signal generator be also used to the window keep signal and The second detection signal carries out logic or operation and logical not operation, obtains the window input control signal；Or, described Second control signal generator is used to carry out logical not operation to the 1st set signal, obtains the 1st reverse phase set letter Number, then logic and operation and logical not operation are carried out to the 1st reverse phase set signal and the time window signal, it obtains The window keeps signal；The second control signal generator is also used to keep the window signal and second detection Signal carries out logic and operation and logical not operation, obtains the window input control signal.

The type of second control signal generator provided by the invention is varied, can by different logical operations come Realize its function.

8th kind of implementation of the 7th kind of implementation or first aspect with reference to first aspect, in first aspect In 9th kind of implementation, when the count status detection circuit detects that the count value is equal to default second target value When, the second detection signal of the count status detection circuit output is high level signal, when the count status detects When circuit detects the count value not equal to default second target value, the institute of the count status detection circuit output Stating the second detection signal is low level signal；Or, being preset when the count status detection circuit detects that the count value is equal to When the second target value, the second detection signal of the count status detection circuit output is low level signal, when described When count status detection circuit detects the count value not equal to default second target value, the count status detection The second detection signal of circuit output is high level signal.

The low and high level of second detection signal can be set according to actual needs, need to only be met when count value is equal in advance If when the second target value, the second corresponding level of detection signal, and when count value is not equal to default second target value, the The corresponding level of two detection signals is not identical.

Second of implementation of the first implementation or first aspect with reference to first aspect, the of first aspect In ten kinds of implementations, the first detection signal includes: low level first detection signal and high-order first detection signal；The meter Number state detection circuit is used to set minimum bit corresponding to the count value of counter output, output according to The low level first detection signal；The count status detection circuit is also used to according to corresponding to the count value except lowest order Other bits other than binary number export the high-order first detection signal；When the count status detection circuit When detecting that the count value is equal to default first object numerical value, the low level first of the count status detection circuit output Detection signal is high level signal, and the high-order first detection signal of output is high level signal；Or, working as the count status When detection circuit detects that the count value is equal to default first object numerical value, the count status detection circuit is exported described Low level first detection signal is low level signal, and the high-order first detection signal of output is low level signal；Described first Control signal generator is used to carry out logic or operation to the 1st set signal and the initial reverse phase set signal and patrol Inverse is collected, the initial holding signal is obtained；The first control signal generator is also used to the initial holding signal Logic or operation are carried out with the low level first detection signal, obtains the first median, and to the initial holding signal and institute It states high-order first detection signal and carries out logic or operation, obtain the second median, then to first median and described second Median carries out logic and operation and obtains the initial input control signal；Or, the first control signal generator for pair The 1st set signal carries out logical not operation, obtains the 1st reverse phase set signal, then to the 1st reverse phase set signal and institute It states initial set signal and carries out logic and operation, obtain the initial holding signal；The first control signal generator is also used In carrying out logic or operation to the initial holding signal and the low level first detection signal, third median is obtained, and right The initial holding signal and the high-order first detection signal carry out logic or operation, obtain the 4th median, then to described Third median and the 4th median carry out logic and operation and obtain the initial input control signal；Or, described first It controls signal generator to be used to carry out logic or operation to the 1st set signal and the initial reverse phase set signal, obtain The initial holding signal；The first control signal generator is also used to the initial holding signal and the low level first It detects signal and carries out logic and operation, obtain the 5th median, and to the initial holding signal and high-order first detection Signal carries out logic and operation, obtains the 6th median, is patrolled respectively the 5th median and the 6th median Volume inverse, it is corresponding to obtain the 7th median and the 8th median, then to the 7th median and the 8th median into Row logic and operation obtains the initial input control signal；Or, the first control signal generator is used for the described 1st Set signal carries out logical not operation, obtains the 1st reverse phase set signal, then to the 1st reverse phase set signal and described initial Set signal carries out logic and operation and logical not operation, obtains the initial holding signal；The first control signal is raw It grows up to be a useful person and is also used to carry out logic and operation to the initial holding signal and the low level first detection signal, obtain among the 9th Value, and logic and operation is carried out to the initial holding signal and the high-order first detection signal, the tenth median is obtained, it is right 9th median and the tenth median carry out logical not operation respectively, and correspondence obtains the 11st median and the 12nd Median, then logic and operation is carried out to the 11st median and the 12nd median, obtain the initial input Control signal；Or, the first control signal generator is used for the 1st set signal and the initial reverse phase set signal Logic or operation are carried out, the initial holding signal is obtained；The first control signal generator is also used to the initial guarantor It holds signal and the low level first detection signal carries out logic and operation, obtain the 13rd median, and to the initial holding Signal and the high-order first detection signal carry out logic and operation, obtain the 14th median, then among the described 13rd Value and the 14th median carry out logic or operation, obtain the initial input control signal；Or, the first control letter Number generator is used to carry out logical not operation to the 1st set signal, obtains the 1st reverse phase set signal, then anti-to the described 1st Phase set signal and the initial set signal carry out logic and operation and logical not operation, obtain the initial holding letter Number；The first control signal generator is also used to patrol the initial holding signal and the low level first detection signal Volume and operation, obtain the 15th median, and to initial the holdings signal and the high-order first detection signal progress logic With operation, the 16th median is obtained, then logic or operation are carried out to the 15th median and the 16th median, Obtain the initial input control signal；Or, the first control signal generator is used for the 1st set signal and described Initial reverse phase set signal carries out logic or operation and logical not operation, obtains the initial holding signal；First control Signal generator processed is also used to carry out logic or operation to the initial holding signal and the low level first detection signal, obtains 17th median, and carry out logic or operation to the initial holding signal and the high-order first detection signal obtains the 18 medians, then logical not operation is carried out respectively to the 17th median and the 18th median, correspondence obtains 19th median and the 20th median, then logic or fortune are carried out to the 19th median and the 20th median It calculates, obtains the initial input control signal；Or, the first control signal generator be used for the 1st set signal into Row logical not operation, obtains the 1st reverse phase set signal, then to the 1st reverse phase set signal and the initial set signal into Row logic and operation obtains the initial holding signal；The first control signal generator is also used to the initial holding Signal and the low level first detection signal carry out logic or operation, obtain the 21st median, and to the initial holding Signal and the high-order first detection signal carry out logic or operation, obtain the 22nd median, then to the described 21st Median and the 22nd median carry out logical not operation respectively, and correspondence obtains the 23rd median and the 24th Median, then logic or operation are carried out to the 23rd median and the 24th median, it obtains described initial Input control signal.

When first detection signal includes low level first detection signal and high-order first detection signal, first control signal is raw Growing up to be a useful person, there are various structures for correspondence, it can its function is realized by different logical operations.

Second aspect, the present invention provide a kind of implementation method of multi-mode programmable counter, comprising: the multi-mode programmable Counter of setting in counter receives preset division signal and clock signal respectively, and according to the preset division signal and The clock signal carries out counting operation, exports count value；The multi-mode programmable counter detect the count value whether etc. In default first object numerical value, and export first detection signal；The multi-mode programmable counter receives the first detection letter Number, initial M signal and feedback signal, and generated according to the initial M signal and the feedback signal and initial keep letter Number, initial input, which is generated, further according to the initial holding signal and the first detection signal controls signal, the initial centre Signal includes: at least one of initial set signal or initial reverse phase set signal；The multi-mode programmable counter according to The initial input control signal and the clock signal, generate the initial M signal；The multi-mode programmable counter According to the initial M signal and the clock signal, or according to the initial holding signal and the clock signal, generate n A set signal and n reverse phase set signal, wherein the n set signal includes: that the 1st set signal to the n-th set is believed Number, the n reverse phase set signal includes: the 1st reverse phase set signal to the n-th reverse phase set signal, and n is positive integer；Described 1st Set signal or the 1st reverse phase set signal are the feedback signal, and the feedback signal is that the setting circuit is last The signal of output；The multi-mode programmable counter utilizes the initial set signal, and the initial reverse phase set signal is described 1st set signal is to the n-th set signal and the 1st reverse phase set signal into the n-th reverse phase set signal At least one signal carries out setting several operations to the counter of setting, and the number of setting operates lasting multiple clock cycle.

The implementation method of multi-mode programmable counter provided by the invention is implemented by above-mentioned multi-mode programmable counter, above-mentioned Multi-mode programmable counter can by first control signal generator so that initial set unit set several periods outputs can The initial M signal for continuing multiple clock cycle, until setting circuit generates feedback signal.Moreover, setting circuit is defeated It will receive initial M signal or the initial influence for keeping signal out, so that the n set signal and n of setting circuit output are a anti- There are at least one signals in phase set signal, can equally set several period lasts multiple clock cycle.Therefore, several meters can be set Number device can be according to initial set signal, and initial reverse phase set signal, the 1st set signal to the n-th set signal and the 1st is instead At least one signal of phase set signal into the n-th reverse phase set signal, carry out multiple clock cycle sets several operations.Therefore, The implementation method of multi-mode programmable counter provided by the invention improves the working frequency that can set counter, so that more Mould programmable counter working frequency with higher, improves the operating rate of multi-mode programmable counter.

In conjunction with second aspect, in the first implementation of second aspect, the implementation method of multi-mode programmable counter Further include: the multi-mode programmable counter also detects the count value and whether is equal to default second target value, and exports the Two detection signals；The multi-mode programmable counter also receives the second detection signal, window M signal and the feedback Signal, and window is generated according to the window M signal and the feedback signal and keeps signal, it is kept further according to the window Signal and the second detection signal generate window input control signal, and the window M signal includes: time window signal Or at least one of phase reversal time window signal；The multi-mode programmable counter is also according to the window input control signal With the clock signal, the window M signal is generated.

Above-mentioned time window generator and second control signal generator cooperating pass through the 1st set signal of control Generation time accurately controls the output duration of time window signal and phase reversal time window signal, and this makes it possible to bases Actual needs generates accurate time window signal and phase reversal time window signal for using.

The third aspect, the present invention provide a kind of frequency divider, including dual-modulus prescaler, gulp down counter and above-mentioned multimode can Program counter；Wherein, the dual-modulus prescaler controls signal for receiving input periodic signal and frequency dividing ratio, and according to institute Input periodic signal and frequency dividing ratio control signal are stated, the first fractional frequency signal and the second fractional frequency signal are exported；The multimode can Program counter is coupled with the dual-modulus prescaler, for receiving first fractional frequency signal and the second frequency dividing letter Number, and according to first fractional frequency signal and second fractional frequency signal output target fractional frequency signal and counting controling signal；Institute It states and gulps down counter and be coupled respectively with the dual-modulus prescaler and the multi-mode programmable counter, for receiving described first Fractional frequency signal and the counting controling signal, according to first fractional frequency signal and the counting controling signal, described point of output Frequency ratio controls signal, and frequency dividing ratio control signal is supplied to the dual-modulus prescaler.

Frequency divider provided by the invention includes above-mentioned multi-mode programmable counter, and above-mentioned multi-mode programmable counter energy Enough realize higher working frequency, therefore, frequency divider provided by the invention can be realized biggish frequency dividing ratio range, have more preferable Noiseproof feature.

Detailed description of the invention

In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with It obtains other drawings based on these drawings.

Fig. 1 is the structural schematic diagram of frequency divider in the prior art；

Fig. 2 is the first structure diagram of multi-mode programmable counter provided in an embodiment of the present invention；

Fig. 3 is the first working timing figure of multi-mode programmable counter provided in an embodiment of the present invention；

Fig. 4 is the second structural schematic diagram of multi-mode programmable counter provided in an embodiment of the present invention；

Fig. 5 is the second working timing figure of multi-mode programmable counter provided in an embodiment of the present invention；

Fig. 6 is the first structure diagram of first control signal generator provided in an embodiment of the present invention；

Fig. 7 is the second structural schematic diagram of first control signal generator provided in an embodiment of the present invention；

Fig. 8 is the third structural schematic diagram of first control signal generator provided in an embodiment of the present invention；

Fig. 9 is the 4th structural schematic diagram of first control signal generator provided in an embodiment of the present invention；

Figure 10 is the 5th structural schematic diagram of first control signal generator provided in an embodiment of the present invention；

Figure 11 is the 6th structural schematic diagram of first control signal generator provided in an embodiment of the present invention；

Figure 12 is the 7th structural schematic diagram of first control signal generator provided in an embodiment of the present invention；

Figure 13 is the 8th structural schematic diagram of first control signal generator provided in an embodiment of the present invention；

Figure 14 is the 9th structural schematic diagram of first control signal generator provided in an embodiment of the present invention；

Figure 15 is the tenth structural schematic diagram of first control signal generator provided in an embodiment of the present invention；

Figure 16 is the 11st structural schematic diagram of first control signal generator provided in an embodiment of the present invention；

Figure 17 is the 12nd structural schematic diagram of first control signal generator provided in an embodiment of the present invention；

Figure 18 is the first connected mode schematic diagram of the i-th set unit provided in an embodiment of the present invention；

Figure 19 is second of connected mode schematic diagram of the i-th set unit provided in an embodiment of the present invention；

Figure 20 is the 13rd structural schematic diagram of first control signal generator provided in an embodiment of the present invention；

Figure 21 is the 14th structural schematic diagram of first control signal generator provided in an embodiment of the present invention；

Figure 22 is the 15th structural schematic diagram of first control signal generator provided in an embodiment of the present invention；

Figure 23 is the 16th structural schematic diagram of first control signal generator provided in an embodiment of the present invention；

Figure 24 is the 17th structural schematic diagram of first control signal generator provided in an embodiment of the present invention；

Figure 25 is the 18th structural schematic diagram of first control signal generator provided in an embodiment of the present invention；

Figure 26 is the 19th structural schematic diagram of first control signal generator provided in an embodiment of the present invention；

Figure 27 is the 20th structural schematic diagram of first control signal generator provided in an embodiment of the present invention；

Figure 28 is the 21st structural schematic diagram of first control signal generator provided in an embodiment of the present invention；

Figure 29 is the 22nd structural schematic diagram of first control signal generator provided in an embodiment of the present invention；

Figure 30 is the 23rd structural schematic diagram of first control signal generator provided in an embodiment of the present invention；

Figure 31 is the 24th structural schematic diagram of first control signal generator provided in an embodiment of the present invention；

Figure 32 is the 25th structural schematic diagram of first control signal generator provided in an embodiment of the present invention；

Figure 33 is the 26th structural schematic diagram of first control signal generator provided in an embodiment of the present invention；

Figure 34 is the 27th structural schematic diagram of first control signal generator provided in an embodiment of the present invention；

Figure 35 is the 28th structural schematic diagram of first control signal generator provided in an embodiment of the present invention；

Figure 36 is the third structural schematic diagram of multi-mode programmable counter provided in an embodiment of the present invention；

Figure 37 is the structural schematic diagram of frequency divider provided in an embodiment of the present invention.

Specific embodiment

Below in conjunction with the attached drawing in the present embodiment, the technical solution in the present embodiment is explicitly described, it is clear that Described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Based on the implementation in the present invention Example, every other embodiment obtained by those of ordinary skill in the art without making creative efforts belong to The scope of protection of the invention.

Referring to Fig. 2, multi-mode programmable counter 1 provided in an embodiment of the present invention includes: that can set counter 10, count State detection circuit 30, first control signal generator 40, initial set unit dff0 and setting circuit 60.

Can set counter 10 for receive respectively preset division signal (it is illustrative, use n<0>here, n<1>, n<2>, N<3>, n<4>, n<5>, n<6>, n<7>, n<8>indicate each fractional frequency signal) and clock signal clk, and according to preset division Signal and clock signal clk carry out counting operation, export count value cnt, it should be noted that can set counter 10 and carry out skill The principle of art operation, has been fully described in first technology, specifically can with reference to first technology (such as: IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.33,NO.10；IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS- II:ANALOG AND DIGITAL SIGNAL PROCESSING, VOL.49, NO.9 and US20020036935A1).Count shape State detection circuit 30, which is coupled to, can set counter 10, for detecting whether count value cnt is equal to default first object numerical value, and Export first detection signal o_eoc1.First control signal generator 40 is coupled to count status detection circuit 30, for receiving First detection signal o_eoc1, initial M signal and feedback signal, and generated just according to initial M signal and feedback signal Begin to keep signal, keep signal and first detection signal o_eoc1 to generate initial input controlling signal further according to initial, it is initial in Between signal include: at least one of initial set signal ld0 or initial reverse phase set signal ld0b.Initial set unit dff0 It is coupled to first control signal generator 40, for controlling signal and clock signal clk according to initial input, generates initial intermediate Signal.Setting circuit 60 includes cascade n set unit, and n set unit is used to be believed according to initial M signal and clock Number clk, or signal and clock signal clk are kept according to initial, n set signal and n reverse phase set signal are generated, In, n set signal includes: the 1st set signal ld1 to the n-th set signal ldn, and n reverse phase set signal includes: the 1st reverse phase Set signal ld1b to n-th reverse phase set signal ldnb, n are positive integer；Set of the n set unit cascade in rearmost position Unit generates the 1st set signal ld1 and the 1st reverse phase set signal ld1b, the 1st set signal ld1 or the 1st reverse phase set signal Ld1b is feedback signal；Illustratively, when n is more than or equal to 2, the n set unit that setting circuit 60 includes can be respectively as follows: 1st set unit dff1 ... is until n-th of set unit dffn, wherein the n set unit according to number size, It is cascaded in a manner of descending, that is to say, that n-th of set unit dffn is located at the starting position of cascaded link, (n-1)th set Unit is located at the next position of cascaded link, and cascades with n-th of set unit dffn, and so on, the 1st set unit Dff1 is located at the last one position of cascaded link.Counter 10 can be set to be also used to according to initial set signal ld0, it is initial anti- Phase set signal ld0b, the 1st set signal ld1 are anti-to the n-th set signal ldn and the 1st reverse phase set signal ld1b to n-th At least one signal in phase set signal ldnb, carry out multiple clock cycle sets several operations, and those skilled in the art should Know, sets number operation and refer in the use process that can set counter 10, preset a number for counter 10 can be set Value, then can set counter 10 and start counting from this preset numerical value, and counting mode can be incremental, be also possible to Successively decrease, can specifically refer to the prior art.

The course of work of above-mentioned multi-mode programmable counter 1 are as follows:

Counter 10 can be set and receive preset division signal and clock signal clk, and according to preset division signal and clock Signal clk carries out counting operation, exports count value cnt；Specifically, can be set when that can set counter 10 and set number operation Counter 10 can export preset count value cnt according to preset division signal, carry out counting operation that can set counter 10 When, the meeting of counter 10 signal pulse according to corresponding to the clock signal clk received can be set and carry out countdown, can be set Counter 10 often receives the signal pulse of a clock signal clk, can set the count value cnt that counter 10 is exported and subtract 1。

Count status detection circuit 30 detects whether count value cnt is equal to default first object numerical value, and exports the first inspection Survey signal o_eoc1.Wherein, presetting first object numerical value can be set according to actual needs, when detecting count value cnt When equal to default first object numerical value, counter 10 can be set and carry out setting several operations, that is, export preset count value cnt, work as inspection When measuring count value cnt not equal to default first object numerical value, counter 10 can be set and carry out countdown operation, and output phase The count value cnt answered.

First control signal generator 40 receives first detection signal o_eoc1, initial M signal and feedback signal, and Initial holding signal is generated according to initial M signal and feedback signal, keeps signal and first detection signal o_ further according to initial Eoc1 generates initial input and controls signal.

Initial set unit dff0 controls signal and clock signal clk according to initial input, generates initial M signal.

Setting circuit 60 keeps signal and clock signal according to initial M signal and clock signal clk, or according to initial Clk, the 1st set signal ld1 of generation to the n-th set signal ldn and the 1st reverse phase set signal ld1b to the n-th reverse phase set believe Number ldnb.

Counter 10 can be set according to initial set signal ld0, initial reverse phase set signal ld0b, the 1st set signal ld1 Believe at least one of to the n-th set signal ldn and the 1st reverse phase set signal ld1b to the n-th reverse phase set signal ldnb Number, carry out lasting multiple clock cycle sets several operations.In more detail, control can set counter 10 and carry out setting number operation Signal can set several operation time periods, continue multiple clock cycle, therefore, can set counter 10 can carry out according to the signal Multiple clock cycle set several operations.

In the case where the series that can set frequency unit 20 included by counter 10 determines, it is complete that counter 10 can be set It is just determined accordingly at the time required for number operates is set.Since multi-mode programmable counter 93 in the prior art only includes one A set unit for being used to generate set signal, this allows for the set signal generated and sets in several operating times only in determining It can continue a clock cycle, so that the set signal be when control can set counter 10 and set number operation, it can It sets counter 10 to be merely able to complete to set several operations within a clock cycle, therefore leads to the work of multi-mode programmable counter Frequency is lower.In multi-mode programmable counter 1 provided in an embodiment of the present invention, including count status detection circuit 30, first is controlled Signal generator 40, initial set unit dff0 and setting circuit 60 processed, and first control signal generator 40 respectively and meter Number state detection circuit 30, initial set unit dff0 and setting circuit 60 are coupled, and can be according to initial M signal Initial holding signal is generated with feedback signal, keeps signal and first detection signal o_eoc1 to generate initial input further according to initial Control signal；Since feedback signal is (the i.e. feedback letter that the set unit by 60 cascade of setting circuit in rearmost position generates Number ultimately produced by setting circuit 60), therefore, before generating feedback signal, first control signal generator 40 can It according only to initial M signal and first detection signal o_eoc1, generates initial input and controls signal, and make initial set unit Dff0 can control signal according to the initial input and export initial M signal, the initial M signal or first exported during this Begin to keep input of the signal as setting circuit 60, control setting circuit 60 exports corresponding signal, until setting circuit 60 generates Until feedback signal, first control signal generator 40 is further according to initial M signal, first detection signal o_eoc1 and feedback These three signals of signal generate corresponding initial input and control signal, and control setting circuit 60 and export corresponding signal.

According to above-mentioned analytic process it is found that multi-mode programmable counter 1 provided in an embodiment of the present invention can pass through first Signal generator 40, initial set unit dff0 and setting circuit 60 are controlled, what control was exported by initial set unit dff0 Initial M signal, and enable to initial set unit dff0 that can hold setting several periods (determine set in several times) output Continue the initial M signal of multiple clock cycle.Moreover, the output of setting circuit 60 will receive initial M signal or initial guarantor The influence of signal is held, i.e., equally may exist letter in the n set signal and n reverse phase set signal exported by setting circuit 60 Number it can set several period lasts multiple clock cycle.Therefore, can set counter 10 can according to initial set signal ld0, Initial reverse phase set signal ld0b, the 1st set signal ld1 to the n-th set signal ldn and the 1st reverse phase set signal ld1b extremely At least one signal in n-th reverse phase set signal ldnb, carry out multiple clock cycle sets several operations, improves work frequency Rate, so that the working frequency with higher of multi-mode programmable counter 1, improves the work of multi-mode programmable counter 1 Speed meets the demand of high-frequency work.

In addition, when counter 10 can be set according to initial set signal ld0, initial reverse phase set signal ld0b, the 1st set Signal ld1 to the n-th set signal ldn and the 1st reverse phase set signal ld1b is multiple into the n-th reverse phase set signal ldnb Signal, when carrying out setting number operation, whole frequency units 20 that counter 10 includes will can be set by, which being equivalent to, is grouped, and not The corresponding frequency unit 20 for controlling different groups of same signal.Compared with controlling whole frequency units 20 with a signal, Duo Gexin Number control multiple groups frequency unit 20, be equivalent to reduce can set counter 10 completion set number operate required for the time, and Setting for counter 10 can be set by, which being controlled by multiple signals, counts operation and sets several release operations, can set the frequency dividing list in counter 10 Member 20 can carry out setting several operations simultaneously, the operating rate of multi-mode programmable counter 1 be improved, to further improve more The working frequency of mould programmable counter 1.Moreover, whole frequency units in counter 10 can be set by the control of multiple signals 20, it is thus also avoided that the signal load mistake that whole frequency units 20 in counter 10 occur only can be set by a signal control Big problem.

It should be noted that multi-mode programmable counter 1 provided in an embodiment of the present invention can be with bimodulus as shown in Figure 1 91 fit applications of pre-divider, or be used alone as counter, multi-mode programmable counter 1 is when being used alone, same energy It enough realizes biggish division range, has not only well adapted to multimode application, be also adapted to the demand of different crystal oscillators.

It is worth noting that, when counter 10 can be set according to initial set signal ld0, initial reverse phase set signal Ld0b, the 1st set signal ld1 are to the n-th set signal ldn and the 1st reverse phase set signal ld1b to the n-th reverse phase set signal Multiple signals in ldnb, when carrying out setting number operation, as long as there is a signal that can make that counter 10 can be set in multiple signals Carry out multiple clock cycle sets several operations, the corresponding technical effect of the present invention can be realized, below for such case pair How to improve working frequency and carries out detailed analysis.

Assuming that can set counter 10 has M grades of frequency units 20, the clock cycle of multi-mode programmable counter works is T (i.e. frequency be 1/T), then can be approximately considered can set counter 10 it is corresponding set number operation with set several release operations when Between it is directly proportional to the series of frequency unit 20, it is assumed that set the times that number operation needs to each grade of frequency unit 20 is T1, set the time that several release operations need to each grade of frequency unit 20 is t0, then carries out setting number to M grades of frequency units 20 It is M × t1 the time required to operation, is M × t0 the time required to setting several release operations.

For traditional structure, setting number operation and setting several release operations for all frequency units is both needed in 1 clock cycle T It completes, that is, meets following formula:

T≥M×t1

T≥M×t0

Therefore, the minimum clock cycle T that the multi-mode programmable counter 93 of traditional structure works_minAre as follows:

T_min=max { M × t1, M × t0 }

For the structure that the embodiment of the present invention proposes, it is with the counter 10 of setting in Fig. 2 including 9 frequency units Example, here by initial set signal ld0, initial reverse phase set signal ld0b, the 1st set signal ld1 to the n-th set signal ldn, And the 1st reverse phase set signal ld1b into the n-th reverse phase set signal ldnb, can control can set 10 working condition of counter The signal definition of (including: to set number state and count status) is target set signal, and target set signal is initial set in Fig. 2 Signal ld0 and the 2nd set signal ld2, wherein initial set signal ld0 is responsible for 5 that control can be set in counter 10 and divides Unit 20, and 5 frequency units 20 it is corresponding set number operation need to be responsible for control in 3 interior completions of clock cycle T ', the 2nd set signal Make remaining 4 frequency unit 20, and 4 frequency units 20 are corresponding sets number operation and need to set in 2 interior completions of clock cycle T ' Number release operation is required to complete (can be understood as signal process from high to low level) within 1 clock cycle.

For setting several operations, meet following formula:

3T′≥5×t1

2T′≥4×t1

For setting several release operations, meet following formula:

T′≥5×t0

T′≥4×t0

Therefore, the minimum duty cycle T for the multi-mode programmable counter 1 that the embodiment of the present invention proposes_min' are as follows:

That is:

T′_min=max { 2 × t1,5 × t0 }

It includes 9 frequency units 20 that counter, which can be set, altogether, therefore for the multi-mode programmable counter 93 of traditional structure Minimum duty cycle T_minAre as follows:

T_min=max { 9 × t1,9 × t0 }

It can be seen that multi-mode programmable of the multi-mode programmable counter 1 provided in an embodiment of the present invention relative to traditional structure Counter 93 can be realized the smaller duty cycle, so as to realize higher working frequency.

Fig. 4 and Fig. 5 are please referred to, for the structure in Fig. 4, target set signal includes: the 1st set signal ld1 and initial Set signal ld0, the 1st set signal ld1 are responsible for controlling 2 frequency units 20, and 2 frequency units 20 are corresponding sets several operations It being both needed to complete in 1 clock cycle T ＂ with several release operations are set, the 2nd set signal ld2 is responsible for controlling 7 frequency units 20, And 7 frequency units 20 are corresponding sets number operation and set several release operations and be both needed to complete in 2 clock cycle T ＂.

For setting several operations, meet following formula:

T″≥2×t1

2T″≥7×t1

For setting several release operations, meet following formula:

T″≥2×t0

2T″≥7×t0

Therefore, the minimum duty cycle T of multi-mode programmable counter 1 provided in an embodiment of the present invention_min＂ are as follows: T "_min= Max { 3.5 × t1,3.5 × t0 }, is equally substantially better than the multi-mode programmable counter 93 of traditional structure.

The structure and connection type of above-mentioned setting circuit 60 are varied, two kinds of concrete conditions are given below, with opposed The specific work process of position circuit 60 is illustrated.

The first situation, n-th of the set unit dffn and initial set unit dff0 in setting circuit 60 are coupled, and N set unit dffn is used to export the n-th set signal ldn according to initial M signal and clock signal clk or the n-th reverse phase is set At least one signal in the signal ldnb of position.

Second situation, n-th of set unit dffn and 40 phase coupling of first control signal generator in setting circuit 60 It closes, n-th of set unit dffn is used to keep signal and clock signal clk to export the n-th set signal ldn or n-th according to initial At least one signal in reverse phase set signal ldnb.

The 1st set unit dff1 to based on any one situation in above-mentioned two situations, in n set unit There are following two kinds of working methods in n-1 set unit:

The first working method, i-th of set unit dffi and i+1 set unit dff_i in n set unit + 1 is coupled, and i-th of set unit dffi is used to generate the i-th set signal according to clock signal clk and i+1 M signal At least one signal in ldi or the i-th reverse phase set signal ldib；I+1 M signal includes: i+1 set signal ld_i+ At least one of 1 or i+1 reverse phase set signal ld_i+1b；The value of i subtracts 1 every time since n-1, is recycled to i=1 and is Only；

Second of working method, i-th of set unit dffi and first control signal generator 40 in n set unit Be coupled, i-th set unit dffi is used to keep signal according to clock signal clk and i-th, generate the i-th set signal ldi or At least one signal in i-th reverse phase set signal ldib；In this mode of operation, first control signal generator 40 is also used In with i+1 M signal, generation i-th keeps signal, and the i-th holding signal is supplied to i-th of set based on the feedback signal Unit dffi；The value of i subtracts 1 every time since n-1, until being recycled to i=1.

Setting circuit 60, can be by the corresponding above-mentioned two situations of n-th of set unit dffn and in actual work The corresponding above two working method any combination of 1 set unit dff1 to (n-1)th set unit, Lai Shixian setting circuit 60 work.Preferably, n-th of set unit dffn in setting circuit 60 uses above-mentioned second situation, the 1st set list First dff1 to (n-1)th set unit uses above-mentioned second of working method.Under this preferred embodiment, in setting circuit 60 N-th of set unit dffn receives initial holding signal, and i-th of set unit dffi receives i-th and keep signal (1~n- of i value 1)；And n-th of set unit dffn keeps signal and clock signal clk to export the n-th set signal ldn or n-th according to initial At least one signal in reverse phase set signal ldnb；I-th of set unit dffi keeps believing according to clock signal clk and i-th Number, generate at least one signal in the i-th set signal ldi or the i-th reverse phase set signal ldib.Due to initially keep signal and I-th holding signal is influenced by feedback signal, and the target set letter that counter 10 set number operation can be set by allowing for control It number can be by the control of feedback signal, in this way when can set counter 10 will carry out counting operation, it will be able to by anti- Feedback signal controls each target set signal to be stopped exporting in synchronization, to avoided well in previous target set signal After terminating output, adjacent latter set signal does not complete also and sets several situations, avoids the occurrence of the problem of logic operation mistake.

The above-mentioned structure for setting counter 10 is varied, specifically may include cascade multiple frequency units 20, each A frequency unit 20 is two-divider, and the positive output of each frequency unit 20 is used as adjacent next frequency unit 20 Clock input.When being converted into binary count value by the count value cnt that counter 10 exports can be set, the binary count value Multidigit binary number (0 or 1) including little-endian, each bit can be set included by counter 10 Each frequency unit 20 corresponds output.It is used for when counter 10 can be set according to initial set signal ld0, initial reverse phase set Signal ld0b, the 1st set signal ld1 are to the n-th set signal ldn and the 1st reverse phase set signal ld1b to the n-th reverse phase set Multiple signals in signal ldnb, carry out when setting number operation of multiple clock cycle, and the corresponding control of each signal can set counting number At least one frequency unit 20 in device 10 carries out setting several operations, and the frequency unit 20 of the corresponding control of each signal is not identical. It should be noted that can set counter 10 progress set number operation be it include each frequency unit 20 carry out set several behaviour Make, specifically, when each frequency unit 20 set number operation, preset division that each frequency unit 20 will will be previously set The corresponding output of signal, exports preset count value cnt to realize and can set counter 10.

Above-mentioned 40 realization of functions of first control signal generator are as follows: generated just according to initial M signal and feedback signal Begin to keep signal, keeps signal and first detection signal o_eoc1 generation initial input to control signal further according to initial, so that Several periods are being set, it can by the initial set signal ld0 or initial reverse phase set signal ld0b of initial set unit dff0 output Continue multiple clock cycle until first control signal generator 40 receives feedback signal.And first control signal generates Device 40 can be accomplished in several ways above-mentioned function, such as:

First way, first control signal generator 40 are used for the 1st set signal ld1 and initial reverse phase set signal Ld0b carries out logic or operation obtains corresponding intermediate result, then carries out logical not operation to the intermediate result, is initially kept Signal；First control signal generator 40 is also used to keep signal and first detection signal o_eoc1 to carry out logic or fortune to initial It calculates, obtains corresponding intermediate result, then logical not operation is carried out to the intermediate result, obtain initial input control signal.

The second way, first control signal generator 40 are used to carry out logical not operation to the 1st set signal ld1, obtain Logic and operation is carried out to the 1st reverse phase set signal ld1b, then to the 1st reverse phase set signal ld1b and initial set signal ld0 Corresponding intermediate result is obtained, then logical not operation is carried out to the intermediate result, obtains initially keeping signal；First control signal is raw It grows up to be a useful person and 40 is also used to keep signal and first detection signal o_eoc1 to carry out logic and operation obtaining corresponding intermediate result to initial, Logical not operation is carried out to the intermediate result again, obtains initial input control signal.

Based on above two mode, circuit composed by initial set unit dff0 and first control signal generator 40 Specific structure be it is diversified, only need to meet the operation logic of multi-mode programmable counter 1 provided in an embodiment of the present invention i.e. It can.Illustratively, the several of the circuit being made of initial set unit dff0 and first control signal generator 40 are shown below Kind specific structure, and its connection relationship is illustrated:

The first structure, referring to Fig. 6, initial set unit dff0 is d type flip flop, first control signal generator 40 is wrapped Include two nor gates；The in-phase output end of d type flip flop is connect with the first input end of first nor gate, and exports initial reverse phase Set signal ld0b, the reversed-phase output of d type flip flop export initial set signal ld0, the clock signal receiving end of d type flip flop with Clock-signal generator is connected, and can receive the clock signal clk issued by clock-signal generator, first nor gate Second input terminal is connected with the 1st set unit dff1 in setting circuit 60, can receive defeated by the 1st set unit dff1 The 1st set signal ld1 out, the output end of first nor gate are connected with the first input end of second nor gate, and second Second input terminal of nor gate is connected with count status detection circuit 30, can receive first detection signal o_eoc1, and second The output end of nor gate and the signal input part of d type flip flop connect.First nor gate is for the 1st set signal ld1 and just Beginning reverse phase set signal ld0b carries out logic or operation, obtains corresponding intermediate result, then carry out logic NOT fortune to the intermediate result It calculates, obtains initially keeping signal；Second nor gate is used to keep signal and first detection signal o_eoc1 to patrol to initial Volume or operation, obtain corresponding intermediate result, then logical not operation is carried out to the intermediate result, obtain initial input control signal, And initial input control signal is supplied to the signal input part of d type flip flop.

Second of structure, referring to Fig. 7, initial set unit dff0 is d type flip flop, first control signal generator 40 is wrapped It includes or door and NAND gate；The reversed-phase output of d type flip flop with or the first input end of door connect, and export initial reverse phase set letter Number ld0b, the in-phase output end of d type flip flop export initial set signal ld0, and the clock signal receiving end of d type flip flop and clock are believed Number generator is connected, and can receive the second input terminal and the of the clock signal clk or door that are issued by clock-signal generator 1 set unit dff1 is connected, and can receive the output end of the 1st set signal ld1 or door and the first input end phase of NAND gate Even, the second input terminal of NAND gate is connected with count status detection circuit 30, can receive first detection signal o_eoc1, and non- The output end of door and the signal input part of d type flip flop connect.Or door is used to believe the 1st set signal ld1 and initial reverse phase set Number ld0b carries out logic or operation, obtains initially keeping signal；NAND gate is used to keep signal and first detection signal to initial O_eoc1 carries out logic and operation, obtains corresponding intermediate result, then carry out logical not operation to the intermediate result, obtains initial defeated Enter and control signal, and initial input control signal is supplied to the signal input part of d type flip flop.

The third structure, referring to Fig. 8, initial set unit dff0 is d type flip flop, first control signal generator 40 is wrapped Include or door and with door；The in-phase output end of d type flip flop with or the first input end of door connect, and export initial reverse phase set signal The reversed-phase output of ld0b, d type flip flop export initial set signal ld0, the clock signal receiving end of d type flip flop and clock signal Generator is connected, and can receive the second input terminal and the 1st of the clock signal clk or door that are issued by clock-signal generator A set unit dff1 is connected, and can receive the output of the 1st set signal ld1 or door by the 1st set unit dff1 output End and it is connected with the first input end of door, is connected with the second input terminal of door with count status detection circuit 30, the can be received One detection signal o_eoc1, connect with the signal input part of the output end of door and d type flip flop.Or door is used for the 1st set signal Ld1 and initial reverse phase set signal ld0b carries out logic or operation, obtains initially keeping signal；It is used to keep believing to initial with door Number and first detection signal o_eoc1 carry out logic and operation, obtain initial input control signal, and by initial input control believe Number it is supplied to the signal input part of d type flip flop.

4th kind of structure, referring to Fig. 9, initial set unit dff0 is d type flip flop, first control signal generator 40 is wrapped Include nor gate and/or door；The reversed-phase output of d type flip flop is connected with the first input end of nor gate, and exports initial reverse phase set The in-phase output end of signal ld0b, d type flip flop export initial set signal ld0, the clock signal receiving end of d type flip flop and clock Signal generator is connected, and can receive the clock signal clk issued by clock-signal generator, the second input terminal of nor gate It is connected with the 1st set unit dff1, the 1st set signal ld1, the first input of the output end and/or door of nor gate can be received End is connected or the second input terminal of door is connected with count status detection circuit 30, can receive first detection signal o_eoc1, or The output end of door and the signal input part of d type flip flop connect.Nor gate is used for the 1st set signal ld1 and initial reverse phase set Signal ld0b carries out logic or operation, obtains corresponding intermediate result, then carry out logical not operation to the intermediate result, obtains initial Keep signal；Or door is used to keep signal and first detection signal o_eoc1 to carry out logic or operation to initial, obtains initial defeated Enter and control signal, and initial input control signal is supplied to the signal input part of d type flip flop.

5th kind of structure, referring to Fig. 10, initial set unit dff0 is d type flip flop, first control signal generator 40 Including reverser and two NAND gates；The in-phase output end of d type flip flop is connect with the first input end of first NAND gate, and defeated Initial set signal ld0 out, the reversed-phase output of d type flip flop export initial reverse phase set signal ld0b, the clock letter of d type flip flop Number receiving end is connected with clock-signal generator, and can receive the clock signal clk issued by clock-signal generator, reversely The input terminal of device is connected with the 1st set unit dff1, can receive the 1st set signal ld1, and to the 1st set signal ld1 into Row logical not operation, obtains the 1st reverse phase set signal ld1b, the second input terminal of first NAND gate and the output end of reverser Be connected, can receive by the 1st reverse phase set signal ld1b of reverser output, the output end of first NAND gate with second and The first input end of NOT gate is connected, and the second input terminal of second NAND gate is connected with count status detection circuit 30, Neng Goujie Receive first detection signal o_eoc1, the signal input part connection of the output end and d type flip flop of second NAND gate.First with it is non- Door is used to carry out logic and operation to the 1st reverse phase set signal ld1b and initial set signal ld0, obtains corresponding intermediate result, Logical not operation is carried out to the intermediate result again, obtains initially keeping signal；Second NAND gate is used to keep signal to initial Logic and operation is carried out with first detection signal o_eoc1, obtains corresponding intermediate result, then logic NOT is carried out to the intermediate result Operation obtains initial input control signal, and initial input control signal is supplied to the signal input part of d type flip flop.

6th kind of structure, please refers to Figure 11, and initial set unit dff0 is d type flip flop, first control signal generator 40 Including reverser and door and nor gate, the in-phase output end of d type flip flop exports initial reverse phase set signal ld0b, d type flip flop Reversed-phase output and it is connected with the first input end of door, and exports initial set signal ld0, the clock signal of d type flip flop receives End is connected with clock-signal generator, and can receive the clock signal clk issued by clock-signal generator；Reverser it is defeated Enter end to be connected with the 1st set unit dff1, the 1st set signal ld1 can be received, and logic is carried out to the 1st set signal ld1 Inverse obtains the 1st reverse phase set signal ld1b, is connected with the second input terminal of door with the output end of reverser, can receive The 1st reverse phase set signal ld1b exported by reverser, is connected with the first input end of the output end of door and nor gate, nor gate The second input terminal be connected with count status detection circuit 30, first detection signal o_eoc1, the output of nor gate can be received End is connect with the signal input part of d type flip flop.With door be used for the 1st reverse phase set signal ld1b and initial set signal ld0 into Row logic and operation obtains initially keeping signal；Nor gate be used for it is initial keep signal and first detection signal o_eoc1 into Row logic or operation obtain corresponding intermediate result, then carry out logical not operation to the intermediate result, obtain initial input control letter Number, and initial input is controlled into the signal input part that signal is supplied to d type flip flop.

7th kind of structure, please refers to Figure 12, and initial set unit dff0 is d type flip flop, first control signal generator 40 Including reverser, NAND gate and with door；The reversed-phase output of d type flip flop is connected with the first input end of NAND gate, and is exported just The in-phase output end of beginning set signal ld0, d type flip flop export initial reverse phase set signal ld0b, and the clock signal of d type flip flop connects Receiving end is connected with clock-signal generator, and can receive the clock signal clk issued by clock-signal generator；Reverser Input terminal is connected with the 1st set unit dff1, can receive the 1st set signal ld1, and patrol the 1st set signal ld1 Inverse is collected, the 1st reverse phase set signal ld1b is obtained；Second input terminal of NAND gate is connected with the output end of reverser, can It receives the 1st reverse phase set signal ld1b that is exported by reverser, the output end of NAND gate and is connected with the first input end of door, with Second input terminal of door is connected with count status detection circuit 30, can receive first detection signal o_eoc1, the output with door End is connect with the signal input part of d type flip flop.NAND gate is used for the 1st reverse phase set signal ld1b and initial set signal ld0 Logic and operation is carried out, corresponding intermediate result is obtained, then logical not operation is carried out to the intermediate result, obtains initially keeping letter Number；It is used to keep signal and first detection signal o_eoc1 to carry out logic and operation to initial with door, obtains initial input control Signal, and initial input is controlled into the signal input part that signal is supplied to d type flip flop.

8th kind of structure, please refers to Figure 13, and initial set unit dff0 is d type flip flop, first control signal generator 40 Including reverser and door and/or door；The reversed-phase output of d type flip flop exports initial reverse phase set signal ld0b, d type flip flop it is same Phase output terminal and it is connected with the first input end of door, and exports initial set signal ld0, the clock signal receiving end of d type flip flop It is connected with clock-signal generator, and the clock signal clk issued by clock-signal generator can be received；The input of reverser End is connected with the 1st set unit dff1, can receive the 1st set signal ld1, and carry out logic NOT to the 1st set signal ld1 Operation obtains the 1st reverse phase set signal ld1b, is connected with the second input terminal of door with the output end of reverser, can receive by Reverser output the 1st reverse phase set signal ld1b, be connected with the first input end of the output end of door and/or door or door second Input terminal is connected with count status detection circuit 30, and the output end and D that can receive first detection signal o_eoc1 or door trigger The signal input part of device connects.It is used to carry out logical AND fortune to the 1st reverse phase set signal ld1b and initial set signal ld0 with door It calculates, obtains initially keeping signal；Or door is used to keep signal and first detection signal o_eoc1 to carry out logic or operation to initial, Initial input control signal is obtained, and initial input control signal is supplied to the signal input part of d type flip flop.

It should be noted that the tool that above-mentioned initial set unit dff0 and first control signal generator 40 can select Body structure is not limited only to above-mentioned eight provided kind structure, as long as can satisfy the device or device of logic function requirement To select.Such as: reverser can select NOT gate, and initial set unit dff0 can select other tools in addition to d type flip flop There is the trigger of delay function.In addition, the logic gate applied in above-mentioned first control signal generator 40 can also be embedded into just In the corresponding trigger of beginning set unit dff0, the function of meeting the requirements equally can be realized.

When first control signal generator 40 is also used to generate i-th with i+1 M signal based on the feedback signal and keep letter Number, and by i-th holding signal be supplied to i-th of set unit dffi when；Optionally, first control signal generator 40 for pair Feedback signal carries out logical not operation, obtains inverted feedback signal (i.e. the 1st reverse phase set signal ld1b), then believes inverting feedback Number and i+1 set signal ld_i+1 carry out logic and operation, obtain the i-th holding signal；Or, first control signal generator 40 For carrying out logical not operation to i+1 set signal ld_i+1, i+1 reverse phase set signal ld_i+1b is obtained, then to i-th+ 1 reverse phase set signal ld_i+1b and feedback signal carry out logic or operation, obtain the i-th holding signal.

It is right in first control signal generator 40 when first control signal generator 40 keeps signal for generating i-th The circuit of part and i-th of set unit dffi composition that the i-th holding signal should be generated has various structures, is given below several The specific structure of the built-up circuit, and corresponding connection relationship is illustrated.

The first structure, please refers to Figure 14, and i-th of set unit dffi is d type flip flop, first control signal generator 40 The middle corresponding part for generating the i-th holding signal includes reverser and NAND gate；The wherein input terminal of reverser and the 1st set list First dff1 is connected, and carries out logical not operation for receiving the 1st set signal ld1, and to the 1st set signal ld1, it is anti-to obtain the 1st Phase set signal ld1b；The first input end of NAND gate is connected with the output end of reverser, the second input terminal of NAND gate and i-th + 1 set unit dff_i+1 is connected, and NAND gate is used for the 1st reverse phase set signal ld1b and i+1 set signal ld_i+1 Logic and operation is carried out, corresponding intermediate result is obtained, then logical not operation is carried out to the intermediate result, obtains the i-th holding signal； The signal input part of d type flip flop is connected with the output end of NAND gate, and d type flip flop is used to keep signal and clock signal according to i-th Clk, exports the i-th reverse phase set signal ldib from in-phase output end, exports the i-th set signal ldi from reversed-phase output.

Second of structure, please refers to Figure 15, and i-th of set unit dffi is d type flip flop, first control signal generator 40 The middle corresponding part for generating the i-th holding signal includes reverser and AND gate；The wherein input terminal of reverser and the 1st set unit Dff1 is connected, and carries out logical not operation for receiving the 1st set signal ld1, and to the 1st set signal ld1, obtains the 1st reverse phase Set signal ld1b；

It is connected with the output end of the first input end of door and reverser, the second input terminal and i+1 set list with door First dff_i+1 is connected, and is used to carry out logical AND fortune to the 1st reverse phase set signal ld1b and i+1 set signal ld_i+1 with door It calculates, obtains the i-th holding signal；The signal input part of d type flip flop and it is connected with the output end of door, d type flip flop is used to protect according to i-th Signal and clock signal clk are held, exports the i-th reverse phase set signal ldib from reversed-phase output, is set from in-phase output end output i-th Position signal ldi.

The third structure, please refers to Figure 16, and i-th of set unit dffi is d type flip flop, first control signal generator 40 The middle corresponding part for generating the i-th holding signal includes reverser and/or door；The wherein input terminal of reverser and i+1 set list First dff_i+1 is connected, and carries out logic NOT fortune for receiving i+1 set signal ld_i+1, and to i+1 set signal ld_i+1 It calculates, obtains i+1 reverse phase set signal ld_i+1b；The first input end of door be connected with the output end of reverser or door Two input terminals are connected with the 1st set unit dff1 or door is used for the 1st set signal ld1 and i+1 reverse phase set signal Ld_i+1b carries out logic or operation, obtains the i-th holding signal；The signal input part of d type flip flop and/or the output end of door are connected, D Trigger is used to keep signal and clock signal clk according to i-th, exports the i-th reverse phase set signal ldib from in-phase output end, from Reversed-phase output exports the i-th set signal ldi.

4th kind of structure, please refers to Figure 17, and i-th of set unit dffi is d type flip flop, first control signal generator 40 The middle corresponding part for generating the i-th holding signal includes reverser and nor gate, the wherein input terminal of reverser and i+1 set Unit dff_i+1 is connected, and carries out logic NOT for receiving i+1 set signal ld_i+1, and to i+1 set signal ld_i+1 Operation obtains i+1 reverse phase set signal ld_i+1b；The first input end of nor gate is connected or non-with the output end of reverser Second input terminal of door is connected with the 1st set unit dff1, and nor gate is for setting the 1st set signal ld1 and i+1 reverse phase Position signal ld_i+1b carries out logic or operation, obtains corresponding intermediate result, and carry out logical not operation to the intermediate result, obtains Signal is kept to i-th；The signal input part of d type flip flop is connected with the output end of nor gate, and d type flip flop is used to keep according to i-th Signal and clock signal clk, export the i-th reverse phase set signal ldib from reversed-phase output, export the i-th set from in-phase output end Signal ldi.

It should be noted that corresponding in above-mentioned i-th of set unit dffi and first control signal generator 40 generate i-th The specific structure for keeping the part of signal that can select, is not limited only to above-mentioned four provided kind structure, as long as can satisfy The device or device that logic function requires can be selected.Such as: reverser can select NOT gate, i-th of set unit dffi Other triggers with delay function in addition to d type flip flop can be selected.

Above-mentioned i-th of set unit dffi, can be with other than the mode being coupled with first control signal generator 40 It is directly coupled with i+1 set unit dff_i+1, please refers to Figure 18 and Figure 19, in Figure 18, using d type flip flop conduct I-th of set unit dffi connects a reverser, the input terminal of reverser in the signal input part of i-th of set unit dffi The i+1 set signal output end for connecting i+1 set unit dff_i+1, for being carried out to i+1 set signal ld_i+1 Negated, the signal input part of the output end connection d type flip flop of reverser, the in-phase output end of d type flip flop exports the i-th reverse phase set Signal ldib, reversed-phase output export the i-th set signal ldi.In Figure 19, using d type flip flop as i-th of set unit Dffi, the signal input part of d type flip flop directly receive i+1 set signal ld_i+1, the in-phase output end output of d type flip flop the I set signal ldi, reversed-phase output export the i-th reverse phase set signal ldib.It is of course not solely limited to both structures provided.

Please continue to refer to Fig. 2, there are various structures for above-mentioned count status detection circuit 30, as long as can be realized to can set number The count value cnt that counter 10 exports is detected, and is believed according to corresponding first detection of the specific count value cnt of detection output Number o_eoc1.Optionally, when count status detection circuit 30 detects that count value cnt is equal to default first object numerical value When, the first detection signal o_eoc1 that count status detection circuit 30 exports is high level signal, when count status detection circuit 30 when detecting that count value cnt is not equal to default first object numerical value, the first detection letter that count status detection circuit 30 exports Number o_eoc1 is low level signal；Or, when count status detection circuit 30 detects that count value cnt is equal to default first object number When value, the first detection signal o_eoc1 that count status detection circuit 30 exports is low level signal, when count status detects electricity When road 30 detects that count value cnt is not equal to default first object numerical value, the first detection of the output of count status detection circuit 30 Signal o_eoc1 is high level signal.

Above-mentioned count status detection circuit 30 is realizing that corresponding there are a variety of knots when meeting the logic function of above-mentioned requirements Structure, optionally, count status detection circuit 30 include low level logic gate group 31, middle position logic gate group 32 and high-order logic gate group 33。

Wherein, low level logic gate group 31 include several low level logic gates, the input terminal of several low level logic gates with several points Frequency unit 20 is correspondingly connected with, and the binary value that several low level logic gates are used to export several frequency units 20 is patrolled accordingly Operation is collected, first group of logical value is generated；Middle position logic gate group 32 includes position logic gate in first, the input of position logic gate in first End is connected with the output end of several low level logic gates, and position logic gate is used to carry out corresponding logic to first group of logical value in first Operation obtains the first intermediate logic values；High-order logic gate group 33 includes the first high-order logic gate, and the first of the first high-order logic gate Input terminal is connected with the output end for the lowest order frequency unit (zero level frequency unit) that can be set in counter 10, and first high position is patrolled The second input terminal for collecting door is connected with the output end of position logic gate in first, the output end of the first high-order logic gate and initial set Unit dff0 is connected；First high-order logic gate is used for the first intermediate logic values and the binary system exported by lowest order frequency unit Value carries out corresponding logical operation, exports first detection signal o_eoc1.

It should be noted that the type for several low level logic gates that low level logic gate group 31 includes can be according to actual needs It is selected, the input terminal of each low level logic gate is connected with corresponding frequency unit 20, is exported for receiving by frequency unit 20 Binary value, and low level logic gate can be made to receive 0 value or 1 value that are exported by frequency unit 20 according to actual needs, respectively Low level logic gate can generate corresponding logical value according to the binary value received, and the corresponding generation of each low level logic gate is patrolled Collect value first group of logical value of composition.

Referring to Fig. 2, above-mentioned count status detection circuit 30 is also used to whether be equal to default second mesh according to count value cnt Mark numerical value, the second detection of output signal o_eoc2；This function based on count status detection circuit 30, multi-mode programmable count Device 1 can also include: second control signal generator 50 and time window generator dffv；Wherein, second control signal generates Device 50 is coupled with count status detection circuit 30, and second control signal generator 50 is for receiving the second detection signal o_ Eoc2, window M signal and feedback signal, and window is generated according to window M signal and feedback signal and keeps signal, then root Signal and the second detection signal o_eoc2 is kept to generate window input control signal according to window, wherein window M signal includes: At least one of time window signal div0 or phase reversal time window signal divb；The control of time window generator dffv and second Signal generator 50 processed is coupled, and time window generator dffv is used for according to window input control signal and clock signal Clk generates window M signal.

It is worth noting that, default second target value can be set according to actual needs, and work as count status When detection circuit 30 detects that count value cnt is equal to default second target value, it is defeated that count status detection circuit 30 can be set The second detection signal o_eoc2 out is high level signal, when count status detection circuit 30 detects that count value cnt is not equal to When default second target value, the second detection signal o_eoc2 that count status detection circuit 30 exports is low level signal；Or, When count status detection circuit 30 detects that count value cnt is equal to default second target value, setting count status detects electricity The second detection signal o_eoc2 that road 30 exports is low level signal, when count status detection circuit 30 detects count value cnt When not equal to default second target value, the second detection signal o_eoc2 that count status detection circuit 30 exports is high level letter Number.

Above-mentioned second control signal generator 50 can realize its function by several working ways, optionally, the second control Signal generator 50 processed is used to carry out logic or operation to the 1st set signal ld1 and phase reversal time window signal divb, obtains phase Intermediate result is answered, then logical not operation is carried out to the intermediate result, window is obtained and keeps signal；Second control signal generator is also For keeping signal and the second detection signal o_eoc2 to carry out logic or operation window, corresponding intermediate result is obtained, then to this Intermediate result carries out logical not operation, obtains window input control signal；Or, second control signal generator 50 is used for the 1st Set signal ld1 carries out logical not operation, obtains the 1st reverse phase set signal ld1b, then to the 1st reverse phase set signal ld1b and when Between window signal div0 carry out logic and operation, obtain corresponding intermediate result, then logical not operation is carried out to the intermediate result, obtain Signal is kept to window；Second control signal generator 50 be also used to window keep signal and second detection signal o_eoc2 into Row logic and operation obtains corresponding intermediate result, then carries out logical not operation to the intermediate result, obtains window input control letter Number.The specific structure and connection type that second control signal generator 50 can be selected are varied, and for details, reference can be made to first Control the corresponding structure of signal generator 40 and connection type.

Below with when count value cnt is equal to default second target value, count status detection circuit 30 export second Detect signal o_eoc2 be high level signal for, to the work of time window generator dffv and second control signal generator 50 It is illustrated as process.

Fig. 2 and Fig. 3 are please referred to, time window generator dffv selects d type flip flop, and second control signal generator 50 includes Two nor gates.Specifically, when count value cnt is equal to default second target value, what count status detection circuit 30 exported Second detection signal o_eoc2 is high level signal, and first nor gate in second control signal generator 50 receives high electricity The second flat detection signal o_eoc2, and logic or operation and logical not operation are successively carried out to it, obtain low level window Input control signal；D type flip flop is delayed to low level window input control signal, and exports low level time window The phase reversal time window signal divb of signal div0 and high level；Second nor gate pair in second control signal generator 50 Low level time window signal div0 (or phase reversal time window signal divb, herein only for the connection side of Fig. 2 Formula) and low level 1st set signal ld1 carry out logic or operation, and obtain intermediate result, then logic is carried out to intermediate result Inverse, the window for obtaining high level keep signal；First nor gate keeps signal and low electricity further according to the window of high level Flat the second detection signal o_eoc2 (count value cnt has not been default second target value at this time) generates low level window again Mouth input control signal, d type flip flop is delayed again to the low level window input control signal generated again, and exports The phase reversal time window signal divb of low level time window signal div0 and high level；It repeats the above process, until second Until a nor gate receives the 1st set signal ld1 of high level, d type flip flop exports the time window signal div0 of high level With low level phase reversal time window signal divb.

By the course of work of above-mentioned time window generator dffv and second control signal generator 50 it is found that can lead to The generation time for crossing the 1st set signal ld1 of control (can correspond to level value, such as when the 1st set signal ld1 is high level is production It is raw, be to stop generating when being low level), accurately control the output of time window signal div0 and phase reversal time window signal divb Duration, this makes it possible to generate accurate time window signal div0 and phase reversal time window signal according to actual needs Divb is for using and (specifically can be applied in charge pump, but be not limited only to this).

Please continue to refer to Fig. 2, above-mentioned multi-mode programmable frequency divider can also include phase inverter, the input terminal of phase inverter and when Between window generator dffv be connected, phase inverter can be used in exporting time window signal according to phase reversal time window signal divb Div0, or phase reversal time window signal divb is exported according to time window signal div0.In more detail, above-mentioned time window produces Raw device dffv can export time window signal div0 and phase reversal time window signal divb simultaneously, and in actually connection, when Between the corresponding time window signal output end of window generator dffv or phase reversal time window signal output end may have it It is connected, and the time window signal output end that other connections will be present again in this case, which extracts, provides time window for outside Message div0, or the phase reversal time window signal output ends of other connections will be present and extract and provide phase reversal time window for outside Message divb can integrally have an impact multi-mode programmable frequency divider.Specifically, when there are it for time window signal output end He connect, and need using exported by time window signal output end time window signal div0 when, can be by phase inverter It is connected with phase reversal time window signal output end, so as to obtain time window signal div0 by phase inverter, then by reverse phase The output end of device, which extracts, provides time window signal div0 for outside, not only meets provide time window message for outside in this way Number div0, also largely reduces the influence to multi-mode programmable frequency divider entirety.

Above-mentioned first detection signal o_eoc1 can be supplied to first control signal generator 40 in a variety of forms, need to only expire Foot is when count status detection circuit 30 detects that count value cnt is equal to default first object numerical value, count status detection circuit The first detection signal o_eoc1 of 30 outputs is high level signal, when count status detection circuit 30 detects count value cnt not When equal to default first object numerical value, the first detection signal o_eoc1 that count status detection circuit 30 exports is low level letter Number；Or, when count status detection circuit 30 detects that count value cnt is equal to default first object numerical value, count status detection The first detection signal o_eoc1 that circuit 30 exports is low level signal, when count status detection circuit 30 detects count value When cnt is not equal to default first object numerical value, the first detection signal o_eoc1 that count status detection circuit 30 exports is high electricity The condition of ordinary mail number.

Based on the condition that above-mentioned first detection signal o_eoc1 should meet, above-mentioned first detection signal o_eoc1 be can wrap It includes: low level first detection signal o_eoc11 and high-order first detection signal o_eoc12；Specifically, count status detection circuit 30 For the minimum bit according to corresponding to the count value cnt that can set the output of counter 10, output low level first is detected Signal o_eoc11；Count status detection circuit 30 is also used to according to corresponding to count value cnt in addition to minimum bit Other bits, export high-order first detection signal o_eoc12.Further, optionally, when count status is examined When slowdown monitoring circuit 30 detects that count value cnt is equal to default first object numerical value, low level that count status detection circuit 30 exports the One detection signal o_eoc11 is high level signal, and the high-order first detection signal o_eoc12 of output is high level signal；Or, working as When count status detection circuit 30 detects that count value cnt is equal to default first object numerical value, count status detection circuit 30 is defeated Low level first detection signal o_eoc11 out is low level signal, and the high-order first detection signal o_eoc12 of output is low level Signal.

When first detection signal o_eoc1 includes low level first detection signal o_eoc11 and high-order first detection signal o_ When eoc12, first control signal generator 40 can be corresponded to there are various structures, several concrete conditions be given below, and to it Connection relationship and the course of work are illustrated:

The first situation, first control signal generator 40 are used for the 1st set signal ld1 and initial reverse phase set signal Ld0b carries out logic or operation, obtains corresponding intermediate result, then carry out logical not operation to the intermediate result, is initially kept Signal；First control signal generator 40 is also used to keep signal and low level first detection signal o_eoc11 to patrol to initial Volume or operation, obtain the first median, and keep signal and high position first detection signal o_eoc12 progress logic or fortune to initial It calculates, obtains the second median, then logic and operation is carried out to the first median and the second median and obtains initial input control letter Number.

Please refer to Figure 20, first control signal generator 40 include nor gate, two or and NAND gate, initial set Unit is d type flip flop；Specifically, first control signal generator 40 obtains initially keeping signal by nor gate, pass through two Or door respectively obtains the first median and the second median, then obtains initial input by NAND gate and control signal；D type flip flop connects It receives initial input and controls signal, and be delayed to initial input control signal, it is initial from the output of the in-phase output end of d type flip flop Reverse phase set signal ld0b exports initial set signal ld0 from the reversed-phase output of d type flip flop.

Please refer to Figure 22, first control signal generator 40 include nor gate, two or and with door, initial set list Member is d type flip flop；Specifically, first control signal generator 40 obtains initially keeping signal by nor gate, by two or Door respectively obtains the first median and the second median, then controls signal by obtaining initial input with door；D type flip flop receives just Beginning input control signal, and be delayed to initial input control signal, initial reverse phase is exported from the reversed-phase output of d type flip flop Set signal ld0b exports initial set signal ld0 from the in-phase output end of d type flip flop.

Second situation, first control signal generator 40 are used to carry out logical not operation to the 1st set signal ld1, obtain Logic and operation is carried out to the 1st reverse phase set signal ld1b, then to the 1st reverse phase set signal ld1b and initial set signal ld0, It obtains initially keeping signal；First control signal generator 40 is also used to keep signal and low level first detection signal o_ to initial Eoc11 carries out logic or operation, obtains third median, and keep signal and high-order first detection signal o_eoc12 to initial Logic or operation are carried out, obtains the 4th median, then logic and operation is carried out to third median and the 4th median and is obtained just Beginning input control signal.

Please refer to Figure 21, first control signal generator 40 include reverser, with door, two or and a NAND gate, Initial set unit is d type flip flop；Believe specifically, first control signal generator 40 obtains the 1st reverse phase set by reverser Number ld1b；By obtaining initially keeping signal with door, by two or third median and the 4th median are respectively obtained, then Initial input, which is obtained, by NAND gate controls signal；D type flip flop receives initial input and controls signal, and controls initial input and believe It number is delayed, initial reverse phase set signal ld0b is exported from the in-phase output end of d type flip flop, from the anti-phase output of d type flip flop End exports initial set signal ld0.

Please refer to Figure 23, first control signal generator 40 include reverser, with door, two or and one and door, just Beginning set unit is d type flip flop；Specifically, first control signal generator 40 obtains the 1st reverse phase set signal by reverser ld1b；By obtaining initially keeping signal with door, by two or third median and the 4th median are respectively obtained, then lead to It crosses and obtains initial input control signal with door；D type flip flop receive initial input control signal, and to initial input control signal into Line delay exports initial reverse phase set signal ld0b from the reversed-phase output of d type flip flop, defeated from the in-phase output end of d type flip flop Initial set signal ld0 out.

The third situation, first control signal generator 40 are used for the 1st set signal ld1 and initial reverse phase set signal Ld0b carries out logic or operation, obtains initially keeping signal；First control signal generator 40 is also used to keep signal to initial Logic and operation is carried out with low level first detection signal o_eoc11, obtains the 5th median, and keep signal and a high position to initial First detection signal o_eoc12 carries out logic and operation, obtains the 6th median, distinguishes the 5th median and the 6th median Logical not operation is carried out, it is corresponding to obtain the 7th median and the 8th median, then the 7th median and the 8th median are carried out Logic and operation obtains initial input control signal.

Please refer to Figure 24, first control signal generator 40 include one or and three NAND gates, initial set unit For d type flip flop；Specifically, first control signal generator 40 passes through or door obtains initially keeping signal, pass through two NAND gates The 7th median and the 8th median are respectively obtained, then initial input is obtained by third NAND gate and controls signal；D type flip flop It receives initial input and controls signal, and be delayed to initial input control signal, just from the output of the in-phase output end of d type flip flop Beginning reverse phase set signal ld0b exports initial set signal ld0 from the reversed-phase output of d type flip flop.

Please refer to Figure 26, first control signal generator 40 include one or, two NAND gates and one and door, initially Set unit is d type flip flop；Specifically, first control signal generator 40 passes through or door obtains initially keeping signal, pass through two A NAND gate respectively obtains the 7th median and the 8th median, then controls signal by obtaining initial input with door；D type flip flop It receives initial input and controls signal, and be delayed to initial input control signal, just from the output of the reversed-phase output of d type flip flop Beginning reverse phase set signal ld0b exports initial set signal ld0 from the in-phase output end of d type flip flop.

4th kind of situation, first control signal generator 40 are used to carry out logical not operation to the 1st set signal ld1, obtain Logic and operation is carried out to the 1st reverse phase set signal ld1b, then to the 1st reverse phase set signal ld1b and initial set signal ld0, Corresponding intermediate result is obtained, then logical not operation is carried out to the intermediate result, obtains initially keeping signal；First control signal is raw It grows up to be a useful person and 40 is also used to keep signal and low level first detection signal o_eoc11 to carry out logic and operation to initial, obtain in the 9th Between be worth, and keep signal and high position first detection signal o_eoc12 progress logic and operation to initial, obtain the tenth median, Logical not operation is carried out respectively to the 9th median and the tenth median, correspondence obtains among the 11st median and the 12nd Value, then logic and operation is carried out to the 11st median and the 12nd median, obtain initial input control signal；

Figure 25 is please referred to, first control signal generator 40 includes reverser and four NAND gates, and initial set unit is D Trigger；Specifically, first control signal generator obtains the 1st reverse phase set signal ld1b by reverser 40；Pass through first A NAND gate obtains initially keeping signal, respectively obtains the 11st median and the 12nd by second and third NAND gate Median, then initial input is obtained by third NAND gate and controls signal；D type flip flop receives initial input and controls signal, and It is delayed to initial input control signal, initial reverse phase set signal ld0b is exported from the in-phase output end of d type flip flop, from D The reversed-phase output of trigger exports initial set signal ld0.

Figure 27 is please referred to, first control signal generator 40 includes reverser, three NAND gates and one and door, is initially set Bit location is d type flip flop；Specifically, first control signal generator 40 obtains the 1st reverse phase set signal ld1b by reverser； It obtains initially keeping signal by first NAND gate, the 11st median is respectively obtained by second and third NAND gate With the 12nd median, then by with door obtain initial input control signal；D type flip flop receives initial input and controls signal, and It is delayed to initial input control signal, initial reverse phase set signal ld0b is exported from the reversed-phase output of d type flip flop, from D The in-phase output end of trigger exports initial set signal ld0.

5th kind of situation, first control signal generator 40 are used for the 1st set signal ld1 and initial reverse phase set signal Ld0b carries out logic or operation, obtains initially keeping signal；First control signal generator 40 is also used to keep signal to initial Logic and operation is carried out with low level first detection signal o_eoc11, obtains the 13rd median, and keep signal and height to initial Position first detection signal o_eoc12 carries out logic and operation, obtains the 14th median, then to the 13rd median and the 14th Median carries out logic or operation, obtains initial input control signal.

Please refer to Figure 28, first control signal generator 40 include two or and two and door, initial set unit be D Trigger；Specifically, first control signal generator 40 is by one or obtains initially keeping signal, passes through two and door divides It does not obtain the 13rd median and the 14th median, then obtains initial input by another or door and control signal；D type flip flop It receives initial input and controls signal, and be delayed to initial input control signal, just from the output of the in-phase output end of d type flip flop Beginning reverse phase set signal ld0b exports initial set signal ld0 from the reversed-phase output of d type flip flop.

Please refer to Figure 30, first control signal generator 40 include one or, two with door and a nor gate, initially Set unit is d type flip flop；Specifically, first control signal generator 40 passes through or door obtains initially keeping signal, pass through two It is a to respectively obtain the 13rd median and the 14th median with door, then initial input is obtained by nor gate and controls signal；D touching It sends out device and receives initial input control signal, and be delayed to initial input control signal, it is defeated from the reversed-phase output of d type flip flop Initial reverse phase set signal ld0b out exports initial set signal ld0 from the in-phase output end of d type flip flop.

6th kind of situation, first control signal generator 40 are used to carry out logical not operation to the 1st set signal ld1, obtain Logic and operation is carried out to the 1st reverse phase set signal ld1b, then to the 1st reverse phase set signal ld1b and initial set signal ld0, Corresponding intermediate result is obtained, then logical not operation is carried out to the intermediate result, obtains initially keeping signal；First control signal is raw It grows up to be a useful person and 40 is also used to keep signal and low level first detection signal o_eoc11 to carry out logic and operation to initial, obtain the 15th Median, and keep signal and high position first detection signal o_eoc12 to carry out logic and operation to initial, it obtains among the 16th Value, then logic or operation are carried out to the 15th median and the 16th median, obtain initial input control signal.

Please refer to Figure 29, first control signal generator 40 include reverser, NAND gate, two with door and one or, Initial set unit is d type flip flop；Believe specifically, first control signal generator 40 obtains the 1st reverse phase set by reverser Number ld1b；It obtains initially keeping signal by NAND gate, be respectively obtained in the 15th median and the 16th by two with door Between be worth, then pass through or door obtain initial input control signal；D type flip flop receives initial input and controls signal, and to initial input Control signal is delayed, and initial reverse phase set signal ld0b is exported from the in-phase output end of d type flip flop, from the anti-of d type flip flop Phase output terminal exports initial set signal ld0.

Please refer to Figure 31, first control signal generator 40 include reverser, NAND gate, two with door and one or non- Door, initial set unit are d type flip flop；Specifically, first control signal generator 40 obtains the 1st reverse phase set by reverser Signal ld1b；It obtains initially keeping signal by NAND gate, respectively obtains the 15th median and the 16th with door by two Median, then initial input is obtained by nor gate and controls signal；D type flip flop receives initial input and controls signal, and to initial Input control signal is delayed, and initial reverse phase set signal ld0b is exported from the reversed-phase output of d type flip flop, from d type flip flop In-phase output end export initial set signal ld0.

7th kind of situation, first control signal generator 40 are used for the 1st set signal ld1 and initial reverse phase set signal Ld0b carries out logic or operation, obtains corresponding intermediate result, then carry out logical not operation to the intermediate result, is initially kept Signal；First control signal generator 40 is also used to keep signal and low level first detection signal o_eoc11 to patrol to initial Volume or operation, obtain the 17th median, and to it is initial keep signal and high position first detection signal o_eoc12 progress logic or Operation obtains the 18th median, then carries out logical not operation respectively to the 17th median and the 18th median, to deserved Logic or operation are carried out to the 19th median and the 20th median, then to the 19th median and the 20th median, is obtained Signal is controlled to initial input.

Please refer to Figure 32, first control signal generator 40 include three nor gates and one or, initial set unit For d type flip flop；Specifically, first control signal generator 40 obtains initially keeping signal by a nor gate, by addition Two nor gates respectively obtain the 19th median and the 20th median, then pass through or door obtain initial input control signal；D Trigger receives initial input and controls signal, and is delayed to initial input control signal, from the in-phase output end of d type flip flop Initial reverse phase set signal ld0b is exported, exports initial set signal ld0 from the reversed-phase output of d type flip flop.

Figure 34 is please referred to, first control signal generator 40 includes four nor gates, and initial set unit is d type flip flop； Specifically, first control signal generator 40 obtains initially keeping signal by first nor gate, pass through second and third A nor gate respectively obtains the 19th median and the 20th median, then obtains initial input control by the 4th nor gate Signal；D type flip flop receives initial input and controls signal, and is delayed to initial input control signal, from the reverse phase of d type flip flop Output end exports initial reverse phase set signal ld0b, exports initial set signal ld0 from the in-phase output end of d type flip flop.

8th kind of situation, first control signal generator 40 are used to carry out logical not operation to the 1st set signal ld1, obtain Logic and operation is carried out to the 1st reverse phase set signal ld1b, then to the 1st reverse phase set signal ld1b and initial set signal ld0, It obtains initially keeping signal；First control signal generator 40 is also used to keep signal and low level first detection signal o_ to initial Eoc11 carries out logic or operation, obtains the 21st median, and keep signal and high-order first detection signal o_ to initial Eoc12 carries out logic or operation, obtains the 22nd median, then distinguish the 21st median and the 22nd median Carry out logical not operation, it is corresponding to obtain the 23rd median and the 24th median, then to the 23rd median and the 24 medians carry out logic or operation, obtain initial input control signal.

Figure 33 is please referred to, first control signal generator 40 includes reverser and door or door and two nor gates, initially Set unit is d type flip flop；Specifically, first control signal generator 40 obtains the 1st reverse phase set signal by reverser ld1b；By obtaining initially keeping signal with door, obtained among the 23rd median and the 24th by two nor gates Value, then pass through or door obtain initial input control signal；D type flip flop receives initial input and controls signal, and to initial input control Signal processed is delayed, and initial reverse phase set signal ld0b is exported from the in-phase output end of d type flip flop, from the reverse phase of d type flip flop Output end exports initial set signal ld0.

Figure 35 is please referred to, first control signal generator 40 includes reverser and door and three nor gates, initial set list Member is d type flip flop；Specifically, first control signal generator 40 obtains the 1st reverse phase set signal ld1b by reverser；Pass through It obtains initially keeping signal with door, obtains the 23rd median and the 24th median by two nor gates, then pass through Other nor gate obtains initial input control signal；D type flip flop receives initial input and controls signal, and controls initial input Signal is delayed, and initial reverse phase set signal ld0b is exported from the reversed-phase output of d type flip flop, from the same mutually defeated of d type flip flop Outlet exports initial set signal ld0.

The embodiment of the invention also provides a kind of implementation methods of multi-mode programmable counter, by above-mentioned multi-mode programmable meter Number device 1 is implemented, comprising:

Counter 10 of setting in multi-mode programmable counter 1 receives preset division signal and clock signal clk respectively, And counting operation, corresponding output count value cnt are carried out according to preset division signal and clock signal clk.

Count status detection circuit 30 in multi-mode programmable counter 1 detects whether count value cnt is equal to default first Target value, and export first detection signal o_eoc1.

First control signal generator 40 in multi-mode programmable counter 1 receives first detection signal o_eoc1, initial M signal and feedback signal, and initial holding signal is generated according to initial M signal and feedback signal, it is protected further according to initial It holds signal and first detection signal o_eoc1 generates initial input control signal；Initial M signal includes: initial set signal At least one of ld0 or initial reverse phase set signal ld0b.

Initial set unit dff0 in multi-mode programmable counter 1 controls signal and clock signal according to initial input Clk generates initial M signal.

Setting circuit 60 in multi-mode programmable counter 1 is according to initial M signal and clock signal clk, or according to first Begin to keep signal and clock signal, generate n set signal and n reverse phase set signal, wherein n set signal include: 1st set signal to the n-th set signal, n reverse phase set signal include: that the 1st reverse phase set signal to the n-th reverse phase set is believed Number, n is positive integer；1st set signal or the 1st reverse phase set signal are feedback signal, and feedback signal be setting circuit 60 most The signal exported afterwards.

Multi-mode programmable counter 1 utilizes initial set signal ld0, initial reverse phase set signal ld0b, the 1st set signal At least one of ld1 to the n-th set signal ldn and the 1st reverse phase set signal ld1b to the n-th reverse phase set signal ldnb Signal carries out setting several operations to that can set counter 10, and sets number and operate and continue multiple clock cycle.

The implementation method of multi-mode programmable counter provided in an embodiment of the present invention is real by above-mentioned multi-mode programmable counter 1 It applies, above-mentioned multi-mode programmable counter 1 can be by first control signal generator 40, so that initial set unit dff0 is being set The output of number period can continue the initial M signal of multiple clock cycle, until setting circuit 60 generates feedback signal. Moreover, the output of setting circuit 60 will receive initial M signal or the initial influence for keeping signal, so that setting circuit 60 is defeated There are at least one signals in n set signal and n reverse phase set signal out, equally can be to set several period lasts multiple Clock cycle.Therefore, can set counter 10 can be according to initial set signal ld0, initial reverse phase set signal ld0b, the 1st Set signal ld1 to the n-th set signal ldn and the 1st reverse phase set signal ld1b is into the n-th reverse phase set signal ldnb At least one signal, carry out multiple clock cycle sets several operations.Therefore, multi-mode programmable provided in an embodiment of the present invention counts The implementation method of device improves the working frequency that can set counter 10, so that multi-mode programmable counter 1 is with higher Working frequency, improve the operating rate of multi-mode programmable counter 1.

The implementation method of above-mentioned multi-mode programmable counter 1, further includes:

Count status detection circuit 30 in multi-mode programmable counter 1 also detects whether count value cnt is equal to default Two target values, the second detection of output signal o_eoc2.

Second control signal generator 50 in multi-mode programmable counter 1 receives the second detection signal o_eoc2, window M signal and feedback signal, and window is generated according to window M signal and feedback signal and keeps signal, it is protected further according to window It holds signal and the second detection signal o_eoc2 generates window input control signal, the window M signal includes: time window At least one of signal div0 or phase reversal time window signal divb.

Time window generator dffv in multi-mode programmable counter 1 is according to window input control signal and clock signal Clk generates window M signal.

By controlling the generation time of feedback signal, time window signal div0 and phase reversal time window signal are accurately controlled The output duration of divb, this makes it possible to generate accurate time window signal div0 and phase reversal time according to actual needs Window signal divb is for using and (specifically can be applied in charge pump, but be not limited only to this).

All the embodiments in this specification are described in a progressive manner, same and similar portion between each embodiment Dividing may refer to each other, and each embodiment focuses on the differences from other embodiments.Especially for method reality For applying example, since it is substantially similar to product embodiments, so describing fairly simple, related place is referring to product embodiments Part explanation.

It, can be according to actual needs from initial set signal in multi-mode programmable counter 1 provided in an embodiment of the present invention Ld0, the 1st set signal ld1 select multiple signals into the n-th set signal ldn, and control can set counter 10 and carry out setting several behaviour Make；Moreover, the first control signal generator 40, count status detection circuit 30 in multi-mode programmable counter 1 are in the presence of more Kind structure and a variety of connection relationships, for the work of clearer explanation multi-mode programmable counter 1 provided in an embodiment of the present invention Make process and can bring technical effect, several specific embodiments are given below.

Fig. 2 and Fig. 3 are please referred to, can set counter includes 9 cascade frequency units (TFF0~TFF8), each fraction The in-phase output end of frequency unit 20 is connected with the clock signal receiving end of next stage frequency unit 20 adjacent thereto, i.e., every level-one Clock signal of the signal of the in-phase output end output of frequency unit 20 as adjacent next stage frequency unit 20；Frequency unit The signal of the in-phase output end output of TFF0~TFF8 is corresponding in turn to are as follows: q<0>, q<1>, q<2>, q<3>, q<4>, q<6>, q<7 >, q<8>, and q<0>, q<1>, q<2>, q<3>, q<4>, q<6>, q<7>, the corresponding decimal value of q<8>be countdown when The count value cnt of output；The signal of the reversed-phase output output of frequency unit TFF0~TFF8 is successively are as follows: qb<0>, qb<1>, qb <2>,qb<3>,qb<4>,qb<6>,qb<7>,qb<8>；(correspondence is above-mentioned pre- for the corresponding set numerical value of frequency unit TFF0~TFF8 If fractional frequency signal) successively are as follows: n<0>, n<1>, n<2>, n<3>, n<4>, n<6>, n<7>, n<8>.

It include two set units, initial set unit dff0, the 1st set unit dff1 and the 2nd in setting circuit 60 A set unit dff2 selects d type flip flop, and these d type flip flops receive the same clock signal clk.By initial set list The initial set signal ld0 of first dff0 output and the 2nd set signal ld2 exported by the 2nd set unit dff2 are for controlling Counter 10 can be set to carry out setting several operations, and the corresponding control zero level frequency unit TFF0 to the 4th of initial set signal ld0 Level V frequency unit TFF5 to the 8th grades of frequency unit TFF8 of grade frequency unit TFF4, the 2nd set signal ld2 corresponding control. First control signal generator 40 includes two nor gates, and the signal of one of nor gate output can either be protected as initial It holds signal, and signal can be kept (for the holding signal that the 2nd set unit dff2 is provided, as the 2nd set as the 2nd 2nd input control signal of unit).Second control signal generator 50 includes two nor gates, time window generator dffv D type flip flop is selected, connects a NOT gate in the reversed-phase output of time window generator dffv.

Default first object numerical value is 4, and presetting the second target value is 36, and the low level in count status detection circuit 30 is patrolled Collecting door group 31 includes a NAND gate and four nor gates, and middle position logic gate group 32 includes two NAND gates, high-order logic gate group 33 include two nor gates.

NAND gate in low level logic gate group 31 for reversed-phase output signal qb corresponding to the 6th grade of frequency unit TFF6 < 6>, the corresponding reversed-phase output signal qb<7>of the 7th grade of frequency unit TFF7 and the 8th grade of corresponding reverse phase of frequency unit TFF8 are defeated Signal qb<8>carries out logic NAND operation out, obtains median；The 1st nor gate in low level logic gate group 31 is used for the The corresponding In-phase output signal q<1>of level-one frequency unit TFF1 and the corresponding reversed-phase output signal of second level frequency unit TFF2 Qb<2>carries out logic or non-operation, obtains the first result；2nd nor gate is for corresponding to third level frequency unit TFF3 The corresponding In-phase output signal q<5>of In-phase output signal q<3>and level V frequency unit TFF5 carries out logic or non-operation, Obtain the second result；3rd nor gate is used for In-phase output signal q<4>corresponding to fourth stage frequency unit TFF4, and intermediate Value carries out logic or non-operation, obtains third result；4th nor gate is used for the corresponding same phase of third level frequency unit TFF3 The corresponding reversed-phase output signal qb<5>of output signal q<3>and level V frequency unit TFF5 carries out logic or non-operation, obtains 4th result；First result, the second result and third result constitute first group of logical value, the first result, third result and the 4th As a result second group of logical value is constituted.

The 1st NAND gate in middle position logic gate group 32 is used to carry out logic NAND operation to first group of logical value, and defeated First intermediate logic values out；The 2nd NAND gate in middle position logic gate group 32 is used to carry out logical AND to second group of logical value non- Operation, and export the second intermediate logic values；The 1st nor gate in high-order logic gate group 33 is used for zero level frequency unit The corresponding In-phase output signal q<0>of TFF0 and the first intermediate logic values carry out logic or non-operation, and export first detection signal o_eoc1；The 2nd nor gate in high-order logic gate group 33 is for corresponding to zero level frequency unit TFF0 with mutually output letter Number q<0>and the second intermediate logic values carry out logic or non-operation, and export the second detection signal o_eoc2.

Referring to Fig. 3, count status detection circuit 30 detects default first object numerical value 4, and exports height in the P1 period The first detection signal o_eoc1 of level, first control signal generator 40 according to the first detection signal o_eoc1 of high level, Generate low level initial input control signal.

In the P2 period, initial set unit dff0 controls signal according to low level initial input, from initial set unit The in-phase output end of dff0 exports low level initial reverse phase set signal ld0b, and defeated from the reverse phase of initial set unit dff0 The initial set signal ld0 of outlet output high level；First control signal generator 40 is according to low level initial reverse phase set The initial holding signal of signal ld0b output high level；First control signal generator 40 is according to the initial holding signal of high level With low level first detection signal o_eoc1, low level initial input control signal is generated again.

In the P3 period, initial set unit dff0 controls signal according to low level initial input, again from initial set The in-phase output end of unit dff0 exports low level initial reverse phase set signal ld0b, and from the anti-of initial set unit dff0 The initial set signal ld0 of phase output terminal output high level；2nd set unit dff2 believes according to the initial holding of high level Number, from the 2nd set signal ld2 of the in-phase output end of the 2nd set unit dff2 output high level, and from the 2nd set unit The reversed-phase output of dff2 exports low level 2nd reverse phase set signal ld2b；First control signal generator 40 is according to low electricity The initial holding signal of flat initial reverse phase set signal ld0b output high level；First control signal generator 40 is according to high electricity Flat initial holding signal and low level first detection signal o_eoc1 generates low level initial input control letter again Number.

In the P4 period, initial set unit dff0 controls signal according to low level initial input, again from initial set The in-phase output end of unit exports low level initial reverse phase set signal ld0b, and defeated from the reverse phase of initial set unit dff0 The initial set signal ld0 of outlet output high level；2nd set unit dff2 believes again according to the initial holding of high level Number, from the 2nd set signal ld2 of the in-phase output end output high level of the 2nd set unit dff2, and from the 2nd set list The reversed-phase output of first dff2 exports low level 2nd reverse phase set signal ld2b；1st set unit dff1 is according to high level The 2nd set signal ld2, from the 1st set signal ld1 of the in-phase output end output high level of the 1st set unit dff1；The One control signal generator 40 is defeated according to the 1st set signal ld1 and low level initial reverse phase set signal ld0b of high level Low level initial holding signal out；First control signal generator 40 is according to low level initial holding signal and low level First detection signal o_eoc1, the initial input for generating high level again control signal.

In the P5 period, initial set unit dff0 controls signal according to the initial input of high level, from initial set unit The initial reverse phase set signal ld0b of the in-phase output end output high level of dff0, and it is defeated from the reverse phase of initial set unit dff0 Outlet exports low level initial set signal ld0；2nd set unit dff2 according to low level initial holding signal, from The in-phase output end of 2nd set unit dff2 exports low level 2nd set signal ld2, and from the anti-of the 2nd set unit The 2nd set signal ld2b of reverse phase of phase output terminal output high level；1st set unit dff1 is according to the 2nd set of high level Signal ld2, from the 1st set signal ld1 of the in-phase output end output high level of the 1st set unit dff1.

It is worth noting that, count status detection circuit 30 detects default first object numerical value 4 in the P1 period, P2, P3 and P4 period, the 2nd set unit dff2 and initial set unit dff0 export corresponding target to that can set counter 10 Set signal, counter 10 can be set by, which making, carries out setting several operations, since in the P4 period, the 1st set unit dff1 output the 1st is set Position signal ld1, so that the 2nd set signal ld2 and initial set signal ld0 are reduced to low level in the P5 period, to realize P2, P3 and P4 period multi-mode programmable counter 1 carries out setting number operation and several operations are set in releasing, and enters the meter that successively decreases in the P5 period Number state.Into after countdown status, counter can be set and opened by setting value N (corresponding setting value when set number operation) Begin to carry out countdown operation, and during carrying out countdown, 30 real-time detection of count status detection circuit is counted Value cnt, when detecting count value cnt is default first object numerical value 4, multi-mode programmable counter 1, which reenters, sets several shapes State.The circulation of multi-mode programmable counter 1 carries out setting number operation, releases and set number operation and countdown operation, until multimode can Program counter 1 is out of service.

It should be noted that setting number and operating corresponding period P2, P3, P4 to be equivalent to counting operation count value cnt is 3, Corresponding period when 2,1.So setting number operates corresponding three clock cycle and counting operation corresponding clock cycle altogether, It is equivalent to and completes N number of clock cycle altogether, to realize Fractional-N frequency (numerical value set is N).

When count status detection circuit 30 detects default second target value 36, the second detection letter of high level is exported Number o_eoc2, second control signal generator 50 and time window generator dffv cooperating are (raw referring to first control signal Grow up to be a useful person 40 and initial set unit dff0 day part the course of work), enable to time window generator dffv export when Between window signal div0 and phase reversal time window signal divb；Phase reversal time window signal divb lasting height in the present embodiment Level time is 35 clock cycle.

Fig. 4 and Fig. 5 are please referred to, can set counter includes 9 cascade frequency units (TFF0~TFF8), specific to connect Mode is the same as example 1；Setting circuit 60 includes 1 set unit, and 1 set unit is the 1st set unit Dff1, the 1st set unit dff1 and initial set unit dff0 select d type flip flop, and the 1st set unit dff1 and just Beginning set unit dff0 receives same clock signal clk, and the 1st set unit dff1 is zero level frequency unit TFF0 to the Level-one frequency unit TFF1 provides target set signal, and initial set unit dff0 is second level frequency unit TFF2 to the 8th grades Frequency unit TFF8 provides target set signal.

Defining the corresponding d type flip flop of the 1st set unit dff1 is the first d type flip flop, and initial set unit dff0 is corresponding D type flip flop be the second d type flip flop, the signal input part of the first d type flip flop is connected with the reversed-phase output of the second d type flip flop, The reversed-phase output of second d type flip flop exports initial set signal ld0, and the in-phase output end output of the second d type flip flop is initial anti- Phase set signal ld0b.

First control signal generator 40 includes two nor gates, and presetting first object numerical value is 4, presets the second number of targets Value is 36, the specific structure of count status detection circuit 30, second control signal generator 50 and time window generator dffv It is the same as example 1, no longer illustrates herein.

Referring to Fig. 5, count status detection circuit 30 detects default first object numerical value 4, and exports height in the P1 period The first detection signal o_eoc1 of level, first control signal generator 40 according to the first detection signal o_eoc1 of high level, Generate low level initial input control signal.

In the P2 period, initial set unit dff0 controls signal according to low level initial input, from initial set unit The in-phase output end of dff0 exports low level initial reverse phase set signal ld0b, and defeated from the reverse phase of initial set unit dff0 The initial set signal ld0 of outlet output high level；First control signal generator 40 is according to low level initial reverse phase set Signal ld0b exports the initial holding signal ld0 of high level, and first control signal generator 40 is according to the initial guarantor of high level Signal and low level first detection signal o_eoc1 are held, generates low level initial input control signal again.

In the P3 period, initial set unit dff0 controls signal according to low level initial input, again from initial set The in-phase output end of unit dff0 exports low level initial reverse phase set signal ld0b, and from the anti-of initial set unit dff0 The initial set signal ld0 of phase output terminal output high level；1st set unit dff1 is according to the initial set signal of high level Ld0, from the 1st set signal ld1 of the in-phase output end output high level of the 1st set unit dff1, and from the 1st set list The reversed-phase output of first dff1 exports low level 1st reverse phase set signal ld1b.First control signal generator 40 is according to height 1st set signal ld1 of level and low level initial reverse phase set signal ld0b export low level initial holding signal； First control signal generator 40 is raw further according to low level initial holding signal and low level first detection signal o_eoc1 Signal is controlled at the initial input of high level.

In the P4 period, initial set unit dff0 controls signal according to the initial input of high level, from initial set unit The initial reverse phase set signal ld0b of the in-phase output end output high level of dff0, and it is defeated from the reverse phase of initial set unit dff0 Outlet exports low level initial set signal ld0；1st set unit dff1 is according to the initial set signal ld0 of high level (the P3 period is corresponding), from the 1st set signal ld1 of the in-phase output end output high level of the 1st set unit dff1, and from The reversed-phase output of 1st set unit dff1 exports low level 1st reverse phase set signal ld1b.

In the P5 period, the initial reverse phase set signal of the in-phase output end output high level of initial set unit dff0 The reversed-phase output of ld0b, initial set unit dff0 export low level initial set signal ld0；1st set unit Dff1 is according to low level initial set signal ld0 (the P4 period is corresponding), from the in-phase output end of the 1st set unit dff1 Low level 1st set signal ld1 is exported, and the 1st from the reversed-phase output of the 1st set unit dff1 output high level is anti- Phase set signal ld1b.

It should be noted that zero level frequency unit TFF0 and first order frequency unit TFF1 are needed corresponding in Fig. 5 It completes to set several operations in shade section, this makes it possible to avoid individual frequency units 20 from being entered counted shape in advance by false triggering State ensure that normal operation logic.

Figure 36 is please referred to, can set counter includes 9 cascade frequency units (TFF0~TFF8)；In setting circuit 60 Including 2 set units, 2 set units and initial set unit dff0 select d type flip flop, and 2 set units and just Beginning set unit dff0 receives the same clock signal clk；1st set unit dff1, the 2nd set unit dff2 and just Beginning set unit dff0 is target set unit, and the 1st set unit dff1 is zero level frequency unit TFF0 and the first order Frequency unit TFF1 provides target set signal, and the 2nd set unit dff2 is second level frequency unit TFF2 to the fourth stage point Frequency unit TFF4 provides target set signal, and initial set unit dff0 is that level V frequency unit TFF5 to the 8th grades of frequency dividing is single First TFF8 provides target set signal.

First control signal generator 40, count status detection circuit 30, second control signal generator 50 and time window The specific structure of mouth generator dffv is the same as example 1, and is no longer illustrated herein.

Initially the in-phase output end of the corresponding d type flip flop of set unit dff0 is connected with first control signal generator 40, And the inverse output terminal output of the corresponding d type flip flop of the output initial set signal ld0b of reverse phase, initial set unit dff0 is initial Set signal ld0；The signal input part of the corresponding d type flip flop of 2nd set unit dff2 is corresponding with initial set unit dff0 D type flip flop inverse output terminal be connected, receive initial set signal ld0；The corresponding d type flip flop of 2nd set unit dff2 In-phase output end export the 2nd set signal ld2, the corresponding d type flip flop of the 2nd set unit dff2 reversed-phase output output 2nd reverse phase set signal ld2b；The signal input part and the 2nd set unit of the corresponding d type flip flop of 1st set unit dff1 The in-phase output end of the corresponding d type flip flop of dff2 is connected, the in-phase output end of the corresponding d type flip flop of the 1st set unit dff1 Export the 1st set signal ld1.

Figure 37 is please referred to, the embodiment of the invention also provides a kind of frequency dividers, including dual-modulus prescaler 91, gulp down counter 92 and above-mentioned multi-mode programmable counter 1；Wherein, dual-modulus prescaler 91 is for receiving input periodic signal and frequency dividing ratio control Signal processed, and signal is controlled according to input periodic signal and frequency dividing ratio, export the first fractional frequency signal and the second fractional frequency signal；Multimode Programmable counter 1 is coupled with dual-modulus prescaler 91, for the first fractional frequency signal of reception and the second fractional frequency signal, and according to First fractional frequency signal and the second fractional frequency signal output target fractional frequency signal and counting controling signal；Gulp down counter 92 respectively with bimodulus Pre-divider 91 and multi-mode programmable counter 1 are coupled, for receiving the first fractional frequency signal and counting controling signal, according to the Frequency dividing ratio control signal is supplied to bimodulus and divided in advance by one fractional frequency signal and counting controling signal, output frequency division than control signal Frequency device 91.

Specifically, dual-modulus prescaler 91 can be realized two continuous frequency dividing ratios, i.e., receive input periodic signal and After frequency dividing ratio controls signal, signal can be controlled according to input periodic signal and frequency dividing ratio, export the first fractional frequency signal and second Fractional frequency signal.When optionally, using frequency dividing ratio control signal as high level, dual-modulus prescaler 91 works in the first frequency dividing ratio, defeated First fractional frequency signal out, frequency dividing ratio controls signal when being low level, and the work of dual-modulus prescaler 91 is in the second frequency dividing ratio, output the For two divided-frequency signal；If multi-mode programmable counter 1 realizes countdown of the count value cnt from N~1, it is real to gulp down counter 92 Existing countdown of the count value cnt from S~1, and S < N.

The specific work process of frequency divider are as follows: it gulps down counter 92 and multi-mode programmable counter 1 while carrying out countdown, During gulping down the progress countdown of counter 92, the frequency dividing ratio control signal of high level is exported, thus dual-modulus prescaler 91 the first fractional frequency signals of output, gulp down counter 92 and multi-mode programmable counter 1 receives the first fractional frequency signal, and are based on first point Frequency signal carries out countdown operation；When gulping down counter 92 and counting down to 1, gulps down counter 92 and stop counting, and export low level Frequency dividing ratio control signal, thus dual-modulus prescaler 91 export the second fractional frequency signal, multi-mode programmable counter 1 be based on second Fractional frequency signal continues counting operation, until counting until 1；Multi-mode programmable counter 1 is based on the first fractional frequency signal and the Two divided-frequency signal exports target fractional frequency signal and counting controling signal, when multi-mode programmable counter 1 count down to 1, output Counting controling signal can control gulp down counter 92 again since S carry out countdown, and again export high level point Frequency ratio controls signal.Dual-modulus prescaler 91 gulps down counter 92 and multi-mode programmable counter 1 circulation industrial as procedure described above Make, until frequency divider is out of service.According to the course of work of above-mentioned frequency divider it is found that when dual-modulus prescaler 91 has carried out S First frequency dividing (work is in the first frequency dividing ratio) in clock period, the second frequency dividing for having carried out (P-S) a clock cycle (work second Frequency dividing ratio).

Frequency divider provided in an embodiment of the present invention includes above-mentioned multi-mode programmable counter 1, and above-mentioned multi-mode programmable Counter 1 can be realized higher working frequency, and therefore, frequency divider provided in an embodiment of the present invention can be realized biggish frequency dividing Than range, there is better noiseproof feature.

The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain Lid is within protection scope of the present invention.

Claims

1. a kind of multi-mode programmable counter characterized by comprising

Counter can be set, for receiving preset division signal and clock signal respectively, and according to the preset division signal and The clock signal carries out counting operation, exports count value；

It is coupled to the count status detection circuit that can set counter, the count status detection circuit is described for detecting Whether count value is equal to default first object numerical value, and exports first detection signal；

It is coupled to the first control signal generator of the count status detection circuit, the first control signal generator is used for The first detection signal, initial M signal and feedback signal are received, and according to the initial M signal and the feedback Signal generates initial holding signal, generates initial input control further according to the initial holding signal and the first detection signal Signal, the initial M signal include: at least one of initial set signal or initial reverse phase set signal；

It is coupled to the initial set unit of the first control signal generator, the initial set unit is used for according to described first Beginning input control signal and the clock signal generate the initial M signal；

Setting circuit, including cascade n set unit, the n set unit be used for according to the initial M signal and The clock signal, or according to the initial holding signal and the clock signal, generate n set signal and n reverse phase Set signal, wherein the n set signal includes: the 1st set signal to the n-th set signal, the n reverse phase set letter It number include: the 1st reverse phase set signal to the n-th reverse phase set signal, n is positive integer, and the n set unit cascade is last The set unit of position generates the 1st set signal and the 1st reverse phase set signal, the 1st set signal or described 1st reverse phase set signal is the feedback signal；

The counter of setting is also used to according to the initial set signal, and the initial reverse phase set signal, the described 1st sets Position signal to the n-th set signal and the 1st reverse phase set signal into the n-th reverse phase set signal at least One signal, carry out multiple clock cycle sets several operations.

2. multi-mode programmable counter according to claim 1, which is characterized in that set for n-th in the setting circuit Bit location is coupled with the initial set unit, and n-th of the set unit is used for according to the initial M signal and institute It states clock signal and exports at least one signal in the n-th set signal or the n-th reverse phase set signal；

I-th of set unit in n set unit is coupled with i+1 set unit, and i-th of the set unit is used for At least one of the i-th set signal or the i-th reverse phase set signal letter are generated according to the clock signal and i+1 M signal Number；The i+1 M signal includes: at least one of i+1 set signal or i+1 reverse phase set signal；The value of i Since n-1, subtract 1 every time, until being recycled to i=1；

Or, i-th of the set unit is coupled with the first control signal generator, i-th of the set unit is used for Signal is kept according to the clock signal and i-th, generates at least one of the i-th set signal or the i-th reverse phase set signal letter Number；The first control signal generator is also used to according to the feedback signal and the i+1 M signal, generates described the I keeps signal, and the i-th holding signal is supplied to i-th of the set unit；The value of i subtracts every time since n-1 1, until being recycled to i=1.

3. multi-mode programmable counter according to claim 1, which is characterized in that set for n-th in the setting circuit Bit location is coupled with the first control signal generator, and n-th of the set unit is used to be believed according to the initial holding Number and the clock signal export at least one signal in the n-th set signal or the n-th reverse phase set signal；

4. multi-mode programmable counter according to claim 2 or 3, which is characterized in that the counter of setting includes Cascade multiple frequency units, when the counter of setting is for according to the initial set signal, the initial reverse phase to be set Position signal, the 1st set signal to the n-th set signal and the 1st reverse phase set signal to n-th reverse phase Multiple signals in set signal carry out when setting number operation of multiple clock cycle, can set number described in the corresponding control of each signal At least one frequency unit in counter carries out setting several operations, and the frequency unit of the corresponding control of each signal is not identical.

5. multi-mode programmable counter according to claim 2 or 3, which is characterized in that

The first control signal generator is used to carry out logic to the 1st set signal and the initial reverse phase set signal Or operation and logical not operation, obtain the initial holding signal；The first control signal generator is also used to described It is initial that signal and the first detection signal is kept to carry out logic or operation and logical not operation, obtain the initial input control Signal processed；

Or, the first control signal generator is used to carry out logical not operation to the 1st set signal, the described 1st is obtained Reverse phase set signal, then logic and operation and logic NOT fortune are carried out to the 1st reverse phase set signal and initial set signal It calculates, obtains the initial holding signal；The first control signal generator is also used to the initial holding signal and described First detection signal carries out logic and operation and logical not operation, obtains the initial input control signal.

6. multi-mode programmable counter according to claim 2 or 3, which is characterized in that

The first control signal generator is also used to carry out logical not operation to the feedback signal, obtains inverting feedback letter Number, then logic and operation is carried out to the inverted feedback signal and the i+1 set signal, it obtains described i-th and keeps signal； Or, the first control signal generator is also used to carry out logical not operation to the i+1 set signal, it is anti-to obtain i+1 Phase set signal, then logic or operation are carried out to the i+1 reverse phase set signal and the feedback signal, obtain described i-th Keep signal.

7. multi-mode programmable counter according to claim 1, which is characterized in that when the count status detection circuit is examined When measuring the count value equal to default first object numerical value, the first detection letter of the count status detection circuit output It number is high level signal, when the count status detection circuit detects the count value not equal to the default first object number When value, the first detection signal of the count status detection circuit output is low level signal；

Or, when the count status detection circuit detects that the count value is equal to default first object numerical value, the counting The first detection signal of state detection circuit output is low level signal, when the count status detection circuit detects institute When stating count value not equal to the default first object numerical value, the first detection letter of the count status detection circuit output Number be high level signal.

8. multi-mode programmable counter according to claim 1, which is characterized in that

The count status detection circuit is also used to whether be equal to according to the count value default second target value, output second Detect signal；

The multi-mode programmable counter further include:

It is coupled to the second control signal generator of the count status detection circuit, the second control signal generator is used for Receive the second detection signal, window M signal and the feedback signal, and according to the window M signal and described Feedback signal generates window and keeps signal, keeps signal and the second detection signal to generate window input further according to the window Signal is controlled, the window M signal includes: at least one of time window signal or phase reversal time window signal；

It is coupled to the time window generator of the second control signal generator, the time window generator is used for according to institute Window input control signal and the clock signal are stated, the window M signal is generated.

9. multi-mode programmable counter according to claim 8, which is characterized in that the second control signal generator is used In carrying out logic or operation and logical not operation to the 1st set signal and the phase reversal time window signal, institute is obtained It states window and keeps signal；The second control signal generator is also used to keep the window signal and the second detection letter Number logic or operation and logical not operation are carried out, obtains the window input control signal；

Or, the second control signal generator is used to carry out logical not operation to the 1st set signal, the described 1st is obtained Reverse phase set signal, then logic and operation and logic are carried out to the 1st reverse phase set signal and the time window signal Inverse obtains the window and keeps signal；The second control signal generator be also used to the window keep signal and The second detection signal carries out logic and operation and logical not operation, obtains the window input control signal.

10. multi-mode programmable counter according to claim 8 or claim 9, which is characterized in that when the count status detects electricity When road detects that the count value is equal to default second target value, second inspection of the count status detection circuit output Survey signal is high level signal, when the count status detection circuit detects the count value not equal to default second mesh When marking numerical value, the second detection signal of the count status detection circuit output is low level signal；

Or, when the count status detection circuit detects that the count value is equal to default second target value, the counting The second detection signal of state detection circuit output is low level signal, when the count status detection circuit detects institute When stating count value not equal to default second target value, the second detection letter of the count status detection circuit output Number be high level signal.

11. multi-mode programmable counter according to claim 2 or 3, which is characterized in that the first detection signal packet It includes: low level first detection signal and high-order first detection signal；

The count status detection circuit is used to set lowest order two corresponding to the count value of counter output according to System number exports the low level first detection signal；

The count status detection circuit is also used to its according to corresponding to the count value in addition to minimum bit Its bit exports the high-order first detection signal；

When the count status detection circuit detects that the count value is equal to default first object numerical value, the count status The low level first detection signal of detection circuit output is high level signal, and the high-order first detection signal of output is height Level signal；Or, when the count status detection circuit detects that the count value is equal to default first object numerical value, it is described The low level first detection signal of count status detection circuit output is low level signal, high-order first detection of output Signal is low level signal；

The first control signal generator is used to carry out logic to the 1st set signal and the initial reverse phase set signal Or operation and logical not operation, obtain the initial holding signal；The first control signal generator is also used to described It is initial that signal and the low level first detection signal is kept to carry out logic or operation, the first median is obtained, and to described initial It keeps signal and the high-order first detection signal to carry out logic or operation, obtains the second median, then among described first Value and second median carry out logic and operation and obtain the initial input control signal；

Or, the first control signal generator is used to carry out logical not operation to the 1st set signal, the 1st reverse phase is obtained Set signal, then logic and operation is carried out to the 1st reverse phase set signal and the initial set signal, it obtains described initial Keep signal；The first control signal generator is also used to the initial holding signal and the low level first detection signal Logic or operation are carried out, obtains third median, and carry out to the initial holding signal and the high-order first detection signal Logic or operation obtain the 4th median, then carry out logic and operation to the third median and the 4th median and obtain Signal is controlled to the initial input；

Or, the first control signal generator is used to carry out the 1st set signal and the initial reverse phase set signal Logic or operation obtain the initial holding signal；The first control signal generator is also used to believe the initial holding Number and the low level first detection signal carry out logic and operation, obtain the 5th median, and to initial the holdings signal with The high position first detection signal carries out logic and operation, the 6th median is obtained, to the 5th median and the described 6th Median carries out logical not operation respectively, corresponding to obtain the 7th median and the 8th median, then to the 7th median and 8th median carries out logic and operation, obtains the initial input control signal；

Or, the first control signal generator is used to carry out logical not operation to the 1st set signal, the 1st reverse phase is obtained Set signal, then logic and operation and logic NOT fortune are carried out to the 1st reverse phase set signal and the initial set signal It calculates, obtains the initial holding signal；The first control signal generator is also used to the initial holding signal and described Low level first detection signal carries out logic and operation, obtains the 9th median, and to the initial holding signal and the high position First detection signal carries out logic and operation, obtains the tenth median, to the 9th median and the tenth median point Not carry out logical not operation, correspondence obtains the 11st median and the 12nd median, then to the 11st median and institute It states the 12nd median and carries out logic and operation, obtain the initial input control signal；

Or, the first control signal generator is used to carry out the 1st set signal and the initial reverse phase set signal Logic or operation obtain the initial holding signal；The first control signal generator is also used to believe the initial holding Number and the low level first detection signal carry out logic and operation, obtain the 13rd median, and to the initial holding signal Carry out logic and operation with the high-order first detection signal, obtain the 14th median, then to the 13rd median and 14th median carries out logic or operation, obtains the initial input control signal；

Or, the first control signal generator is used to carry out logical not operation to the 1st set signal, the 1st reverse phase is obtained Set signal, then logic and operation and logic NOT fortune are carried out to the 1st reverse phase set signal and the initial set signal It calculates, obtains the initial holding signal；The first control signal generator is also used to the initial holding signal and described Low level first detection signal carries out logic and operation, obtains the 15th median, and to the initial holding signal and the height Position first detection signal carries out logic and operation, obtains the 16th median, then to the 15th median and the described tenth Six medians carry out logic or operation, obtain the initial input control signal；

Or, the first control signal generator is used to carry out the 1st set signal and the initial reverse phase set signal Logic or operation and logical not operation obtain the initial holding signal；The first control signal generator is also used to pair The initial holding signal and the low level first detection signal carry out logic or operation, obtain the 17th median, and to institute It states initial holding signal and the high-order first detection signal carries out logic or operation, obtain the 18th median, then to described 17th median and the 18th median carry out logical not operation respectively, and correspondence obtains the 19th median and the 20th Median, then logic or operation are carried out to the 19th median and the 20th median, obtain the initial input Control signal；

Or, the first control signal generator is used to carry out logical not operation to the 1st set signal, the 1st reverse phase is obtained Set signal, then logic and operation is carried out to the 1st reverse phase set signal and the initial set signal, it obtains described initial Keep signal；The first control signal generator is also used to the initial holding signal and the low level first detection signal Logic or operation are carried out, obtains the 21st median, and to the initial holding signal and the high-order first detection signal Logic or operation are carried out, obtains the 22nd median, then to the 21st median and the 22nd median Carry out logical not operation respectively, it is corresponding to obtain the 23rd median and the 24th median, then in the described 23rd Between value and the 24th median carry out logic or operation, obtain the initial input control signal.

12. a kind of implementation method of multi-mode programmable counter characterized by comprising

Counter of setting in the multi-mode programmable counter receives preset division signal and clock signal respectively, and according to The preset division signal and the clock signal carry out counting operation, export count value；

The multi-mode programmable counter detects whether the count value is equal to default first object numerical value, and exports the first detection Signal；

The multi-mode programmable counter receives the first detection signal, initial M signal and feedback signal, and according to institute It states initial M signal and the feedback signal generates initial holding signal, further according to the initial holding signal and described first It detects signal and generates initial input control signal, the initial M signal includes: initial set signal or initial reverse phase set At least one of signal；

The multi-mode programmable counter controls signal and the clock signal according to the initial input, generate it is described it is initial in Between signal；

Setting circuit in the multi-mode programmable counter according to the initial M signal and the clock signal, or according to The initial holding signal and the clock signal generate n set signal and n reverse phase set signal, wherein the n A set signal includes: the 1st set signal to the n-th set signal, and the n reverse phase set signal includes: the 1st reverse phase set letter Number to the n-th reverse phase set signal, n is positive integer；The 1st set signal or the 1st reverse phase set signal are the feedback Signal, and the feedback signal is the signal that the setting circuit finally exports；

The multi-mode programmable counter utilizes the initial set signal, the initial reverse phase set signal, the 1st set Signal to the n-th set signal and the 1st reverse phase set signal into the n-th reverse phase set signal at least one A signal carries out setting several operations to the counter of setting, and the number of setting operates lasting multiple clock cycle.

13. the implementation method of multi-mode programmable counter according to claim 12 characterized by comprising

The multi-mode programmable counter also detects whether the count value is equal to default second target value, and exports the second inspection Survey signal；

The multi-mode programmable counter also receives the second detection signal, window M signal and the feedback signal, and Window is generated according to the window M signal and the feedback signal and keeps signal, keeps signal and institute further according to the window It states the second detection signal and generates window input control signal, when the window M signal includes: time window signal or reverse phase Between at least one of window signal；

The multi-mode programmable counter generates the window also according to the window input control signal and the clock signal M signal.

14. a kind of frequency divider, which is characterized in that including dual-modulus prescaler, gulp down counter and as appointed in claim 1~11 Multi-mode programmable counter described in one；Wherein,

The dual-modulus prescaler controls signal for receiving input periodic signal and frequency dividing ratio, and is believed according to the input period Number and the frequency dividing ratio control signal, export the first fractional frequency signal and the second fractional frequency signal；

The multi-mode programmable counter is coupled with the dual-modulus prescaler, for receiving first fractional frequency signal and institute The second fractional frequency signal is stated, and according to first fractional frequency signal and second fractional frequency signal output target fractional frequency signal and counting Control signal；

The counter that gulps down is coupled with the dual-modulus prescaler and the multi-mode programmable counter respectively, for receiving The first fractional frequency signal and the counting controling signal are stated, according to first fractional frequency signal and the counting controling signal, output The frequency dividing ratio controls signal, and frequency dividing ratio control signal is supplied to the dual-modulus prescaler.