JPH1117527A - Variable divider - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent count processing of wrong data and also to shorten the lockup time by producing a load signal for a counting operation even to the load enable signal which fetches the data. SOLUTION: A load enable signal LE is kept at an H level for a fixed time by an external signal showing the change of data. The output signal LD12 of a load signal generation circuit 8 is changed to an L level from an H level after a fixed time of the rise of the signal LE and then reset at an H level synchronously with the rise of a clock signal P-CK. The output signal LD11 of a load signal generation circuit 6 is set at an L level when the division output fp of a programmable counter 4 is outputted. Then the output LD of an AND circuit 9 is set twice at L levels when the output fp is outputted and when the signal LD12 is set at an L level. Under such conditions, the latest data are loaded and the count processing is started synchronously with the signal P-CK with no mistake at the second rise.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable frequency divider which constitutes a PLL (Phase-Locked Loop) circuit used for a communication device such as a cellular phone, and more particularly to a variable frequency divider having a shift register, a latch circuit and a programmable counter. Of the frequency divider. Mobile phones and PHS (Personal Handyphone Sist
The demand for communication devices such as em) is steadily increasing, and PLL circuits used therein are required to have improved performance, particularly improved communication accuracy by reducing lock-up time.

[0002]

2. Description of the Related Art First, a basic configuration of a PLL will be described with reference to FIG. The PLL has two frequencies f, as shown in FIG.
a phase comparator 31 for comparing r and fp, and a phase comparator 31
Low-pass filter (LPF) 32 that converts the output signal from the DC level to a DC level, a voltage-controlled oscillator (VCO) 33 that can change the output frequency with a voltage, a prescaler 34 that operates as a frequency divider, and a variable frequency divider 35
It is composed of

The variable frequency divider 35 can arbitrarily set the frequency division ratio N. The frequency divider 35 divides the output frequency from the VCO 33 to 1 / N and inputs the frequency to the phase comparator 31. However, if the frequency used, that is, the output frequency of the VCO 33 increases, it becomes difficult to directly divide the frequency, so that a prescaler 34 that can perform frequency division at high speed operation is interposed. ing.

The PLL having such a configuration operates so that the reference frequency fr from a crystal oscillator or the like and the comparison frequency fp fed back through the loop are always constant, thereby obtaining a desired frequency. Among the above-mentioned PLLs, the variable frequency divider is an important part because it has a large circuit scale and the greatest influence on the lockup time.

The configuration and operation of the conventional variable frequency divider will be described below. As shown in FIG. 9, the variable frequency divider according to the present invention includes a shift register 41, a latch circuit 42, and a variable frequency divider 44, and uses a clock signal CLK, a data signal D, and a load enable signal LE. By being controlled, an arbitrary frequency division ratio is set. Thereby, the output frequency P-CK of the prescaler is set to the predetermined frequency fp.
Divided by

The shift register 41 has a general configuration, and serial data D is sequentially output by a clock signal CLK.
(D1 to D6). Latch circuit 42
Represents a plurality of flip-flops (F
F) The circuit 43 receives the data fetched into the shift register 41 by the load enable signal LE as parallel data D1 to D6.

[0007] The programmable counter 44
A binary counter circuit composed of a plurality of flip-flop (FF) circuits 45 and receiving a clock signal P-CK from a prescaler performs the following operation.
A load signal generation circuit 46 generates a load signal LD based on the divided frequency fp output from the programmable counter 44 itself, and outputs the load signal LD to each of the FF circuits 45 constituting the programmable counter 44.
Enter

The plurality of FF circuits 45, to which the load signals LD1 to LD6 are input, respectively, perform a load process for capturing the output data signals D1 'to D6' of the latch circuit 42, and then perform a clock signal P-CK from the prescaler. In this case, the frequency division signal fp based on the data of the latch circuit 42 is always output by performing the count processing of the data fetched according to.

FIG. 10 is a timing chart of each signal in the circuit of FIG. 9. FIG. 10 (a) shows an output timing of a signal of interest, and FIG. 10 (b) shows a specific FF of the program counter 44. 9 shows an example of data change timing in the circuit 45. As shown in FIG. 10 (a), a load signal L (hereinafter simply referred to as a clock signal) P-CK from a prescaler is applied.
D is synchronized, but an external load enable signal LE
Is input regardless of the timing of the clock signal P-CK and the load signal LD.

A problem in the signal generation at such a timing will be described with reference to FIG. The load signal L generated by the load signal generating circuit 46 by the load enable signal LE from the outside and the divided frequency fp.
When D is input, for example, at the timing shown in FIG. 10B, the load signals and data in the second and fifth FF circuits are as follows.

The load signal LD from the load signal generation circuit 46 is an inverted signal of the frequency-divided signal fp. When the frequency-divided signal fp at the “H” (high) level is output,
When the level becomes “L” (low) level, as shown in FIG. 10B, the second and fifth stage load signals LD2 and LD5
At the same time. The plurality of FF circuits included in the programmable counter 44 may have different electrical characteristics due to different wiring distances from the latch circuit 42 due to restrictions on the circuit configuration.

[0012] From such a difference in electrical characteristics, FIG.
As shown in (b), the data rewrite timing for the load enable signal LE differs. That is, while the data D5 'is rewritten immediately after the generation of the load enable signal LE ("H" level), the data D2' is rewritten a little later. The programmable counter 44 starts the counting process at the rise of the load signals LD2 and LD5 of each FF circuit. In the case of FIG. 10B, the counting is performed in a state where old and new data are mixed.

[0013]

In the conventional programmable counter, as described above, when the external load enable signal LE overlaps with the load signal LD, new and old data are mixed at a certain probability in each bit. May start the counting process. The fact that new and old data are mixed in bit units means that the data is different from the desired frequency, and locks up to the wrong frequency once, causing lock-up time redundancy. become.

Even if the timings of the load enable signal LE and the load signal LD are different, after the rewriting to the new data is completed, the count processing using the old data is performed until the divided signal fp is output. In order to continue
The lock-up time becomes longer accordingly. SUMMARY OF THE INVENTION It is an object of the present invention to provide a variable frequency divider that solves the above-mentioned problems and can improve the communication accuracy by shortening the lock-up time.

[0015]

According to the present invention, there is provided a shift register 1 for taking in serial data D by inputting a clock signal CLK, and converting the data of the shift register 1 into parallel data by a load enable signal LE. Latch circuit 2 received as D1 to D6
And a programmable frequency divider 4 which receives the data of the latch circuit 2 and outputs a predetermined frequency by performing a count process on the data, and outputs the output signal fp after the count process in the programmable counter 4 is completed. And a load signal generating circuit 6 for generating a load signal LD11.
A reset circuit that stops counting by the load signal LD11 and starts counting of new data rewritten by the load enable signal LE when E is input to the latch circuit 2. And

According to the variable frequency divider of the present invention, the load signal LD12 based on the frequency-divided signal fp and the load signal LD12 for the counter operation are also supplied to the load enable signal LE for executing the data fetch. Therefore, the counting operation for erroneous data or old data can be immediately stopped, and the counting operation for new data can be started.

By such an operation, the lock-up time can be shortened.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram for explaining an embodiment of the variable frequency divider of the present invention. The variable frequency divider of the present embodiment has a shift register 1 having a general configuration, a latch circuit 2 having a flip-flop (FF) circuit 3 for each bit, and an FF circuit 5 for each bit, and stores data. After being fetched, it comprises a programmable counter 4 for outputting a predetermined frequency fp by performing a count process, a load signal generating circuit 6 and a reset circuit 7.

In such a variable frequency divider, every time the clock signal CLK is inputted, the binary serial data D is sequentially taken into the shift register 1, and the data taken in by the load enable signal LE is converted into parallel data D1 to D6. Is transferred to the latch circuit 2. On the other hand, the programmable counter 4 is composed of a plurality of FF circuits 5 and performs a frequency division operation by a subtraction count. That is, the parallel data D1 to D6 of the latch circuit 2
Are loaded as data D1 'to D6' based on the load signals LD1 to LD6, and the data D1 'to D6' are input to the clock signal P- corresponding to the output frequency of the prescaler.
In accordance with CK, the count signal is subtracted, and a frequency-divided signal fp having an “H” (high) level is output when the count processing in which the data becomes 0 is completed.

The frequency-divided signal fp is sent to a phase comparator (not shown), and is also input to a load signal generating circuit 6.
Using this as a trigger, the load signal generation circuit 6 creates the first load signal LD11. Also, the reset circuit 7
Is a load signal generation circuit 8 that generates a second load signal LD12 by using the load enable signal LE as a trigger.
A logic circuit 9 which receives the second load signal LD12 and the first load signal LD11 and outputs a load signal LD0 to the programmable counter 4 according to a predetermined logic.
It is composed of

When the load enable signal LE is input, the reset circuit 7
This is a circuit for stopping the counting process with the load signal LD11 performed in step (1) and newly starting the loading process with new data and the counting process. Hereinafter, an operation example of the variable frequency divider of the present embodiment will be described with reference to the timing chart of FIG.

In this embodiment, the programmable counter 4
A description will be given of a case where the output signal fp and the load enable signal LE for fetching new data become “H” (high) level at substantially the same timing. The operation in the programmable counter 4 is performed by loading signals LD2 and LD5 and data D2 'and D2 to the second and fifth stage FF circuits.
This will be described by taking 5 'as an example.

First, a frequency-divided signal fp of the programmable counter 4 is supplied to a clock signal P-CK having a constant period at a timing based on data from the shift register 1.
Becomes "H" level for one clock. The load signal generation circuit 6 includes a load signal LD which is an inverted signal of the frequency-divided signal fp.
11, and receives the "H" level of the frequency-divided signal fp, so that the load signal LD11 becomes "L" (low) level.

At this time, the load enable signal LE rises, and the "H" level continues for a certain time. Then, after a certain time from the rise of the load enable signal LE, the load signal LD12 of the load signal generation circuit 8 changes from the “H” level to the “L” level, and returns to the “H” level in synchronization with the rise of the clock signal P-CK. . The details of this operation will be described later with reference to FIG.

The logic circuit 9 in the reset circuit 7
The load signal LD0, which is an output signal of the ND logic, includes first and second load signals LD11 and LD11.
Receiving LD12, it outputs twice "L" level. This load signal LD0 is applied to each F of the programmable counter 4.
It is input to the F circuit and controls the load processing and the count processing.

That is, in response to the "L" level of the load signal LD0, each FF circuit starts the load processing at the fall of the load signals LD1 to LD6, and starts the count processing at the rise. The load signal LD0 (LD1 to L
While D6) is at the "L" level, the loading process with the latest data is always performed. If the latest data is obtained at the rising point of the load signal LD0, the counting process with the latest data can be performed. .

The data D2 'of the second-stage FF circuit and the data D5' of the fifth-stage FF circuit in the programmable counter 4 are rewritten in response to the rise of the load enable signal LE. As described in the technique, the rewriting timing may be different due to the difference in the electrical characteristics as shown in FIG.

On the other hand, first, the 1 of the load signal LD0 is
By the second "L" level, the load signals LD2, LD5
Becomes "L" level, the load process is started at the falling point t1, and the loading process is started at the rising point t2. At this time, the data D2 'is new data,
Since the data D5 'remains the old data, if the load processing is continued, an operation for adjusting to an undesired frequency due to erroneous data will be performed.

In the present embodiment, however, the load signal LD0 is set to the "L" level again by the fall of the load enable signal LE.
2, the LD5 also goes to the "L" level again, and at this falling point t3, the counting process is stopped and the loading process is restarted from the beginning. Therefore, at the second “L” level rising point t4, as shown in FIG.
Both 2 'and D5' have been rewritten with new data, and a count process for adjusting to a desired frequency is performed.

Therefore, it is possible to prevent the execution of the count processing with erroneous data, and to eliminate the delay of the lock-up time caused by the count processing. Further, the rising of the load enable signal LE is later than in this embodiment, and the output signal fp of the programmable counter 4 is
In the case where the "L" level of the load signal LD0 and the "H" level of the load enable signal LE do not overlap, the lock-up time can be reduced as compared with the related art.

When the rise of the load enable signal LE is later than that of FIG. 2, the rewriting points of the data D2 'and D5' are also delayed, and the rising points t of the load signals LD2 and LD5 are increased.
In the case of No. 2, the old data remains unchanged. Therefore, the programmable counter 4 starts loading processing with old data. Thereafter, when the load enable signal LE changes to "H" level, the data D2 'and D5' are rewritten. In the conventional case, since the load signal LD0 is controlled only by the frequency-divided signal fp, the load process is continued until the next divided signal fp based on the old data is at the "H" level, and the count process with the new data is performed by the load operation. The signal LD0 (LD2,
It starts at the rising point t5 of LD5). In this case, the frequency-divided signal fp and the load signals LD11, LD0, LD2,
The output of LD5 is shown by the dotted line.

On the other hand, in the present embodiment, since the load signal LD0 is also controlled by the load enable signal LE, the count processing with the old data is stopped after the rise of the load enable signal LE (t3). Then, the loading process (t3) and the counting process (t4) of the new data are started immediately. Therefore, from t4 to t5 shown in FIG.
The lock-up time can be shortened by the amount of "T". Note that it is actually assumed that the load enable signal LE becomes "H" level later, so that the point t4 is delayed accordingly.

FIG. 3 is a diagram for explaining a first embodiment of the reset circuit according to the present invention. FIG. 3 (a) is a circuit diagram, and FIG. 3 (b) is a timing chart for explaining operation. It is. As described with reference to FIG. 1, the reset circuit 7 includes the load signal generation circuit 8 and the logic circuit 9. The load signal generation circuit 8 according to the present embodiment includes the FF circuit 10 that receives the load enable signal LE and the FF circuit 10. , This F
An FF circuit 11 that inputs the output signal Q of the F circuit 10 and the clock signal P-CK, and a reset signal RST and an output signal XQ of the FF circuit 11 that input a logical signal RS
An AND circuit 12 for inputting T ′ to the FF circuit 10 is provided.

As the logic circuit 9, an AND circuit is used. The load signal LD11 generated by the frequency-divided signal fp and the load signal L
D12 is input. In such a circuit, the load enable signal LE is an external signal for instructing data change, and is asynchronously input to the clock signal P-CK as shown in FIG.

The reset signal RST is a power save signal for controlling the current in the standby state and the use state, for example, and is asynchronously input to the clock signal P-CK. 3B, when the load enable signal LE and the reset signal RST are input, the output signal Q (FF1Q) of the FF circuit 10 rises in synchronization with the rise of the load enable signal LE. ,
It falls in synchronization with the fall of the output signal XQ (FF2XQ) of the FF circuit 11.

The output signal XQ of the FF circuit 11 (FF2X
Q) falls after the output signal Q (FF1Q) of the FF circuit 10 falls in synchronization with the rise of the clock signal P-CK after the rise of the output signal Q (FF1Q) of the FF circuit 10 Rise in synchronization with the rise of the clock signal P-CK. The output signal XQ (FF2X
The “L” level of Q) sets the output signal LD0 of the AND circuit 9 to the “L” level, and starts loading processing with new data.

FIG. 4 is a circuit diagram for explaining a second embodiment of the reset circuit according to the present invention, and the same parts as those in FIG. 3 are denoted by the same reference numerals. Reset circuit 7 of this embodiment
1 differs from the first embodiment in that the load signal generation circuit 81
In that a time setting FF circuit 13 for controlling the generation timing of the load signal is interposed between the two-stage FF circuits 10 and 11.

That is, the time from when the load enable signal LE is input to the first-stage FF circuit 10 until the signal is sent to the subsequent-stage FF circuit 11 is delayed by the time-setting FF circuit 13. By appropriately selecting the number of FF circuits 13, it is possible to arbitrarily set the load signal generation timing. FIG. 5 is a circuit diagram for explaining a third embodiment of the reset circuit according to the present invention.

The present embodiment is adapted to a PLL in which the frequency division ratio of the reference frequency fr is also variable.
It is used for both the r side and the comparison frequency fp side.
The reset circuit 72 of the present embodiment includes the load signal generation circuit 8
And a fr-side logic circuit 91 and an fp-side logic circuit 92.

The fp side logic circuit 92 is, like the AND circuit 9 in the second and third embodiments, a load signal obtained from the divided signal fp of the programmable counter 4 (see FIG. 1) and a load signal generated by the load signal generation circuit 8. Is entered. However, the signs of the load signals are LDfp1 and L, respectively.
Dfp2. On the other hand, the fr side logic circuit 91
Is a load signal LDfr1 obtained from the output signal of the programmable counter corresponding to the reference frequency fr, and has an AND logic with the load signal LD12 from the load signal generating circuit 8. Is to load a programmable counter corresponding to the reference frequency fr.

The load signal generating circuit 8 has the same configuration as that of the first or second embodiment. FIG. 6 is a circuit diagram for explaining a fourth embodiment of the reset circuit according to the present invention, and corresponds to a dual circuit including two PLLs having different frequency ranges.

The reset circuit 73 of this embodiment includes a high frequency side logic circuit 14 for inputting a load signal LD12 which is an output signal of the load signal generation circuit, and a low frequency side logic circuit 1
5 is provided. The high frequency side logic circuit 14 and the low frequency side logic circuit 15 have the same configuration,
ND circuits 93, 94 (95, 96) and OR circuit 16
(17).

The AND circuit 93 in the high-frequency side logic circuit 14 inputs the load signal LDfr11 based on the output signal of the programmable counter corresponding to the reference frequency fr and the load signal LD12 from the load signal generating circuit 8. , And an AND circuit 94 are provided with a load signal LDfp11 based on the output signal of the programmable counter corresponding to the comparison frequency fp and a load signal L from the load signal generation circuit 8.
D12 is input. However, the load signal LD12 of the load signal generation circuit 8 is once input to the OR circuit 16 together with the select signal S1, and an output signal based on the OR logic is input to both AND circuits 93 and 94.

The select signal S1 is a signal for selecting the counter on the high frequency side, and in the case of this embodiment,
The selection is made at the “L” level. The low-frequency side logic circuit 15 has the same configuration as that of the high-frequency side logic circuit 14, and a description thereof will be omitted. FIG. 7 is a circuit diagram illustrating a reset circuit according to a fifth embodiment of the present invention, in which a clock circuit to be input to a load signal generation circuit can be selected.

The reset circuit 74 of this embodiment includes a load signal generation circuit 8, a fr-side logic (AND) circuit 91, an fp-side logic (AND) circuit 92, and a clock signal selection circuit, as in the third embodiment. The circuit 18 is provided. The clock signal selection circuit 18 includes a pair of AND circuits 19, 2
0 and an OR circuit 22 for inputting these output signals. A reference frequency OSC from a crystal oscillator or the like and a selection signal S are supplied to the
The signal inverted by 1 is input, and the other AND circuit 20 receives the comparison frequency fin and the selection signal S from the prescaler. The selection signal S selects either the reference frequency OSC or the comparison frequency fin. It has a configuration that can be used.

The clock signal selected by the clock signal selection circuit 18 is input to the load signal generation circuit 8 together with the load enable signal LE and the reset signal RST as a load processing control signal.

[0047]

According to the variable frequency divider of the present invention described above, a load signal for counting operation is also generated in response to a load enable signal for fetching data. The counting operation on the data or the old data can be immediately stopped, and the counting operation on the new data can be started.

As a result, the lock-up time can be reduced, which contributes to the improvement of the functions of a communication device such as a mobile phone.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining an embodiment of a variable frequency divider according to the present invention.

FIG. 2 is a timing chart of each signal for explaining the operation of the variable frequency divider of the present invention.

FIG. 3 is a circuit diagram and a timing chart for explaining a first embodiment of the reset circuit according to the present invention.

FIG. 4 is a circuit diagram illustrating a second embodiment of the reset circuit according to the present invention.

FIG. 5 is a circuit diagram for explaining a third embodiment of the reset circuit according to the present invention.

FIG. 6 is a circuit diagram for explaining a fourth embodiment of the reset circuit according to the present invention.

FIG. 7 is a circuit diagram for explaining a reset circuit according to a fifth embodiment of the present invention.

FIG. 8 is a basic configuration diagram of a PLL.

FIG. 9 is a diagram for explaining a conventional variable frequency divider.

FIG. 10 is a timing chart of each signal for explaining the operation of the conventional variable frequency divider.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Shift register 2 Latch circuit 4 Programmable counter 3, 5 FF circuit 6.8 Load signal generation circuit 7 Reset circuit 9 Logic circuit (AND circuit)

Claims (6)

[Claims] 1. A shift register that captures serial data by inputting a clock signal, a latch circuit that receives data of the shift register as parallel data by a load enable signal, and captures data of the latch circuit and counts the data. A variable frequency divider having a programmable counter that outputs a predetermined frequency according to the following: a load signal generating circuit that generates a first load signal based on an output signal after completion of the count processing in the programmable counter; And a reset circuit for stopping the count processing by the first load signal and starting the count processing of new data rewritten by the load enable signal when the data is input to the latch circuit. Variable frequency division . A reset circuit configured to generate a second load signal based on the load enable signal; a second load signal generated by the load signal generation circuit; and a count process performed by the programmable counter. 2. The variable frequency divider according to claim 1, further comprising: a logic circuit which inputs a first load signal generated based on the output signal after completion, and performs a logic output of both load signals. 3. A load signal generation circuit for generating the second load signal, a first flip-flop circuit outputting a fixed data signal in response to the load enable signal, and the first flip-flop circuit A second flip-flop circuit that outputs the data signal in response to a clock signal, using the output signal of the second flip-flop circuit as a data signal, an output signal of the second flip-flop circuit, and a reset signal to the second flip-flop circuit 3. A variable frequency divider according to claim 2, further comprising: a logic circuit for inputting a logic output signal and transmitting the logic output signal as a reset signal to the first flip-flop circuit. 4. A method for adjusting a time between a first flip-flop circuit and a second flip-flop circuit in the load signal generation circuit, from generation of a load enable signal to start of load processing by the programmable counter. 4. The variable frequency divider according to claim 3, further comprising at least one third flip-flop circuit. 5. The second load signal output from the load signal generation circuit based on the load enable signal includes a plurality of logics to which different load signals generated based on different frequency-divided signals are respectively input. 5. The variable frequency divider according to claim 2, wherein the variable frequency divider is input to the circuit as a common signal. 6. The clock signal input to the load signal generation circuit is selected from a plurality of frequency signals by a clock signal selection circuit.
The variable frequency divider according to any one of claims 1 to 5.