CN108832805B - Switching power supply, charging pile, inverter, frequency converter, UPS and protection circuit thereof - Google Patents

Switching power supply, charging pile, inverter, frequency converter, UPS and protection circuit thereof Download PDF

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Publication number
CN108832805B
CN108832805B CN201810372369.3A CN201810372369A CN108832805B CN 108832805 B CN108832805 B CN 108832805B CN 201810372369 A CN201810372369 A CN 201810372369A CN 108832805 B CN108832805 B CN 108832805B
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circuit
gate
pwm
signal
semiconductor device
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CN108832805A (en
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袁沛华
李化良
刘丹
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Santak Electronic Shenzhen Co Ltd
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Santak Electronic Shenzhen Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/539—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency
    • H02M7/5395—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency by pulse-width modulation
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H02M1/325—Means for protecting converters other than automatic disconnection with means for allowing continuous operation despite a fault, i.e. fault tolerant converters

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

The invention relates to a switching power supply, a charging pile, an inverter, a frequency converter, a UPS and a protection circuit for preventing a bridge arm from being directly connected, wherein the bridge arm comprises a first semiconductor device driven by a PWM-A signal and a second semiconductor device driven by a PWM-B signal, and the protection circuit comprises: the first current detection circuit is connected with the bridge arm and used for detecting the leakage current of the second semiconductor device, and the first judgment circuit is connected with the first current detection circuit; the first judgment circuit is used for judging whether the PWM-A signal is allowed to drive the first semiconductor device or not according to the detection result of the first current detection circuit and the PWM-B signal.

Description

Switching power supply, charging pile, inverter, frequency converter, UPS and protection circuit thereof
Technical Field
The invention relates to the technical field of power electronics, in particular to a switching power supply, a charging pile, an inverter, a frequency converter, a UPS and a protection circuit thereof.
Background
With the technical development in the field of power electronics, the requirements on the safety of semiconductor switching devices are also higher and higher, for example, for circuit topologies such as half-bridge, full-bridge or push-pull, if the semiconductor switching tubes of the upper and lower bridge arms are directly connected, the bridge arms are short-circuited, even the switching tubes are exploded, and safety problems are caused.
Due to the semiconductor switching devices (e.g., IGBTs), there is typically some junction capacitance, which causes the switching devices to experience turn-on and turn-off delays. In the prior art, a software programming method is generally adopted, for example, a certain dead time is set in the PWM control signal to avoid short circuit caused by the above reasons. However, if the dead time is set too long, the overall working efficiency of the circuit is affected, and if the dead time is set too short, the safety of the circuit is reduced due to individual differences of different switching devices; this way of avoiding a through short on the bridge arms by means of setting the dead time only by software still lacks reliability.
Therefore, there is a need for a switching power supply, a charging pile, an inverter, a frequency converter, a UPS, and a protection circuit thereof.
Disclosure of Invention
In view of the above problems in the prior art, the present invention provides a protection circuit for preventing a bridge arm from being cut-through, the bridge arm including a first semiconductor device driven by a PWM-a signal and a second semiconductor device driven by a PWM-B signal, the protection circuit including: the first current detection circuit is connected with the bridge arm and used for detecting the leakage current of the second semiconductor device, and the first judgment circuit is connected with the first current detection circuit; the first judgment circuit is used for judging whether the PWM-A signal is allowed to drive the first semiconductor device or not according to the detection result of the first current detection circuit and the PWM-B signal.
Preferably, the protection circuit further includes: the second current detection circuit is connected with the bridge arm and used for detecting the leakage current of the first semiconductor device, and the second judgment circuit is connected with the second current detection circuit; the second judgment circuit is used for judging whether the PWM-B signal is allowed to drive the first semiconductor device according to the detection result of the second current detection circuit and the PWM-A signal.
Preferably, the first current detection circuit includes a first current sensor and a first comparator connected to the bridge arm in sequence, the first current sensor is configured to detect a leakage current of the second semiconductor device, and the first comparator compares a detection result of the first current sensor with a reference voltage and outputs a comparison result to the first judgment circuit;
the second current detection circuit comprises a second current sensor and a second comparator which are sequentially connected to the bridge arm, the second current sensor is used for detecting leakage current of the first semiconductor device, and the second comparator compares a detection result of the second current sensor with a reference voltage and outputs a comparison result to the second judgment circuit;
preferably, the first judging circuit includes a first or gate and a first flip-flop connected in sequence, an input end of the first or gate is connected to an output end of the first comparator and an input end of the PWM-B signal, respectively, and an output end of the first or gate is connected to a set end of the first flip-flop;
the second judgment circuit comprises a second or gate and a second trigger which are connected in sequence, wherein the input end of the second or gate is connected to the output end of the second comparator and the input end of the PWM-A signal respectively, and the output end of the second or gate is connected to the position end of the second trigger.
Preferably, the protection circuit further includes a first logic circuit for controlling the PWM-a signal to drive the first semiconductor device according to a determination result of the first determination circuit, and a second logic circuit for controlling the PWM-B signal to drive the second semiconductor device according to a determination result of the second determination circuit.
Preferably, the first logic circuit includes a first and gate, an input end of the first and gate is connected to the input end of the PWM-a signal and the output end QN of the first flip-flop, respectively, and an output end of the first and gate is connected to the driving end of the first semiconductor device; the second logic circuit comprises a second AND gate, the input end of the second AND gate is respectively connected to the input end of the PWM-B signal and the output end QN of the second trigger, and the output end of the second AND gate is connected to the driving end of the second semiconductor device.
Preferably, the protection circuit further includes a clock signal generation circuit that generates clock signals for the first flip-flop and the second flip-flop according to detection results of the first current detection circuit and the second current detection circuit, and the PWM-a signal and the PWM-B signal.
Preferably, the clock signal generating circuit includes a first not gate and a second not gate respectively connected to the first or gate output terminal and the second or gate output terminal, and a third and gate connected to the first not gate output terminal and the second not gate output terminal, and output terminals of the third and gate are respectively connected to the clock signal input terminal of the first flip-flop and the clock signal input terminal of the second flip-flop.
According to another aspect of the present invention, there is also provided a switching power supply including the protection circuit as described above.
According to another aspect of the invention, a charging pile is also provided, which comprises the protection circuit.
According to another aspect of the present invention, there is also provided an inverter including the protection circuit as described above.
According to another aspect of the present invention, there is also provided a frequency converter including the protection circuit as described above.
According to another aspect of the present invention, there is also provided an Uninterruptible Power Supply (UPS) including the protection circuit as described above.
The protection circuit for preventing the bridge arm from being directly connected controls the PWM signal to drive the complementary device by monitoring the PWM signal and the current on the bridge arm, can effectively ensure that the first device forming the bridge arm is driven, and only when the PWM driving signal B of the second device complementary to the first device is at a low level and the bridge arm end current of the second device is 0, the PWM driving signal A of the first device is allowed to drive the first device, so that the bridge arm formed by the complementary device is effectively prevented from being directly connected; meanwhile, the protection circuit provided by the invention can realize double interlocking of the PWM driving signal and the bridge arm current, improves the reliability of circuit interlocking, can ensure that the bridge arm direct connection phenomenon cannot occur even if the PWM driving signal has a fault (for example, the PWM signal for driving the complementary device generates a high level simultaneously) or the current detection device fails, and improves the use safety of the complementary device; in addition, different from the dead time set by software, the protection circuit provided by the invention is not influenced by the parameters of the semiconductor device, and can be suitable for bridge arm structures formed by complementary semiconductor devices.
Drawings
Fig. 1 is a schematic diagram of a conventional half-bridge inverter circuit composed of IGBTs.
Fig. 2 is a schematic diagram of the turn-off timing of the IGBT in the circuit shown in fig. 1.
Fig. 3 is a schematic diagram of a protection circuit for a half-bridge inverter according to a preferred embodiment of the present invention.
Fig. 4 is a schematic diagram of a clock signal generating circuit of a D flip-flop according to a preferred embodiment of the present invention.
Fig. 5 is a schematic diagram of a protection circuit for a full-bridge inverter according to another embodiment of the present invention.
Fig. 6 is a detailed circuit schematic of the protection circuit for the full bridge inverter shown in fig. 5.
Fig. 7 is a schematic diagram of a protection circuit for a push-pull structure according to another embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail by embodiments with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In the prior art, dead time is usually set in the PWM control signal to prevent short circuit phenomenon of the circuit topology with complementary structure, but the inventor has found that due to individual difference of the semiconductor switching devices, this method can not completely ensure that one of the switching devices is completely disconnected before the other switching device complementary to the one is turned on.
Taking a half-bridge inverter composed of IGBTs as an example, fig. 1 is a schematic diagram of a common half-bridge inverter circuit composed of IGBTs, fig. 2 is a schematic diagram of turn-off timing of the IGBTs in the circuit shown in fig. 1, as shown in fig. 2, in order to turn off the IGBTs, for example, at time t6, PWM-a will send a falling edge to control the corresponding IGBTs to start to perform turn-off, and due to miller effect, the driving voltage U is drivengeFirstly, the miller platform is descended in a time period from t6 to t7 and is continued to a time t 8; accordingly, at time t7, collector-emitter voltage UceStarting rising until reaching the bus voltage at the time t 8; at this time, at time t8, collector-emitter current IceStarts to fall, does not fall to 0 until time t11, and as early as time t10, the driving voltage UgeHas dropped to a specified turn-off negative voltage, the inventors therefore believe that relying on the PWM drive signal alone is unreliable and requires leakage thereof when determining whether the IGBT is fully turned offCurrent, i.e. collector-emitter current IceAnd (6) detecting.
Based on the above principle, the inventor proposes a protection circuit, which can not only interlock the PWM driving signals of the switching devices, but also realize the interlock by monitoring the current on the bridge arm formed by the complementary devices, so as to provide double safety guarantees for the on and off of the complementary devices, and the following description will take a half-bridge inverter circuit formed by IGBTs as an example.
Fig. 3 is a schematic diagram of a protection circuit for a half-bridge inverter according to a preferred embodiment of the present invention, and as shown in fig. 3, the interlock circuit includes: the circuit comprises a logic AND gate 11 and a logic AND gate 21 which are respectively connected with grid driving ends of an IGBT10 and an IGBT20 in a half-bridge inverter through an optical coupling isolation circuit, a current detection circuit 1A and a current detection circuit 1B which are connected with a bridge arm of the half-bridge inverter, and a judgment circuit 2A and a judgment circuit 2B which are respectively connected with output ends of the current detection circuits 1A and 1B;
wherein the current detection circuit 1A comprises a current I connected to the emitter of the IGBT10 for monitoring the collector-emitter currentceA current sensor 12 for detecting whether the current is 0, and a comparator 13 connected to the output terminal of the current sensor 12 via a filter capacitor, if the I of the IGBT10 isce0, the comparator 13 outputs a low level to the determination circuit 2A after comparing with a reference voltage (e.g., 10 mv) connected to the other input terminal of the comparator 13; if I of IGBT10ceIf not 0, the comparator 13 will output a high level to the judgment circuit 2A;
the judgment circuit 2A includes a logic or gate 14 and a D flip-flop 15, wherein one input terminal of the logic or gate 14 is connected to the output terminal of the comparator 13, the other input terminal is connected to the input terminal of the PWM-a signal for driving the IGBT10, the output terminal of the logic or gate 14 is connected to the set terminal of the D flip-flop 15, and the output terminal QN of the D flip-flop is connected to one input terminal of the logic and gate 21.
The current detection circuit 1B has the same circuit as the current detection circuit 1A, and includes a current sensor 22 and a comparator 23 provided complementarily to the current sensor 12 and the comparator 13 in the current detection circuit 1A; the circuit of the judgment circuit 2B is identical to that of the judgment circuit 2A, and includes a logic or gate 24 and a D flip-flop 25 which are provided complementarily to the logic or gate 14 and the D flip-flop 15 in the judgment circuit 2A; the difference is that the output QN of the D flip-flop of the decision circuit 2B is connected to one input of the logic and gate 11.
If at least one of the PWM-a or the signal output from the comparator 13 to the or gate 14 is at a high level, the or gate 14 will output a high level to the set terminal of the D flip-flop 15 to set the D flip-flop 15, and at this time, the output terminal QN of the D flip-flop will output a low level to the and gate 21, so that the and gate 21 will prevent the IGBT20 from being driven regardless of whether the PWM-B signal input to the other input terminal of the and gate 21 is at a high level or a low level;
if both the PWM-A signal and the signal output from the comparator 13 to the logic OR gate 14 are low, i.e., the PWM-A signal is 0, and the collector-emitter current I of the IGBT10 isceIf the signal is also 0, the or gate 14 will output a low level to the set end of the D flip-flop 15, at this time, if the clock signal CL of the D flip-flop is a rising edge, the output end QN will output a high level to the and gate 21, the and gate 21 will allow the PWM-B signal at the other input end to pass through, and if the PWM-B signal at this time is a high level, the IGBT20 will be driven to operate;
similarly, based on the monitoring of the collector-emitter current of the IGBT20 by the current detection circuit 1B and the determination of the PWM-B signal and the monitoring of the current detection circuit 1B by the determination circuit 2B, the logic and gate 11 provided complementary to the logic and gate 21 may control whether or not to allow the PWM-a signal to perform driving of the IGBT10 based on the determination result output by the determination circuit 2B.
By utilizing the protection circuit provided by the invention, the drive interlocking of the half-bridge inverter circuit can be realized according to the PWM signal, and the drive interlocking can also be realized according to the current on the inverter bridge arm, so that the problem of inconsistent change time sequences of the grid drive voltage, the collector-emitter voltage and the collector-emitter current when the IGBT is switched on and switched off is effectively solved, and the working reliability of the complementary IGBT on the bridge arm is improved.
In one embodiment of the present invention, the above-described timing for D flip-flop 15 and D flip-flop 25The clock signal CL may be generated by a clock signal generation circuit, and specifically, the clock signals CL for the D flip-flop 15 and the D flip-flop 25 described above may be associated with the PWM signal and the current detection result of the current detection circuit. Fig. 4 is a schematic diagram of a clock signal generating circuit of a D flip-flop according to a preferred embodiment of the present invention, and as shown in fig. 4, the clock signal CL generating circuit includes a not gate 16 connected to the output terminal of the or gate 14 shown in fig. 3, a not gate 26 connected to the output terminal of the or gate 24 shown in fig. 3, and a and gate 17 connected to the output terminal of the not gate 16 and the output terminal of the not gate 26; when the outputs of the logic OR gate 14 and the logic OR gate 24 are both low, i.e., both PWM-A and PWM-B are low, and the collector-emitter I of the IGBT10 and the IGBT20ceWhen both are 0, the clock signal CL output by the logic and gate 17 will be a rising edge.
By utilizing the clock signal CL generated by the circuit, the control signal output to the logic AND gate by the judgment circuit can be further considered, the condition whether the direct current exists on the inverter bridge arm is further considered, and the reliability of the circuit is improved.
In one embodiment of the invention, the circuit topology shown in FIG. 3 may also use other electronic devices to achieve the same functionality. For example, the current sensors 12 and 22 may be replaced by current dividers, and current signals detected by the current dividers are processed and amplified by the isolation operational amplifier, and then transmitted to the comparator for comparison; the power supply voltage of the comparators 13 and 23 in fig. 3 can adopt plus or minus 15 volts or 12 volts, or adopt a single power supply operational amplifier to replace the operational amplifier in fig. 3 to be used as the comparator; the D flip-flop in fig. 3 may be replaced with a JK flip-flop; the setting end and the resetting end of the D trigger can be exchanged, and the output end Q and the output end QN can also be exchanged; in addition, in the circuit topology shown in fig. 3, all logic gates may be replaced by a combination of one or more nand gates, the logic and gates 11 and 12 may also be replaced by a triode or a MOS transistor, and accordingly, the on/off of the output Q of the D flip-flop may be controlled.
In an embodiment of the present invention, the interlock circuit can also be used to prevent the inverter bridge arm of the full-bridge inverter circuit from generating a through short circuit. Fig. 5 is a schematic structural diagram of a protection circuit for a full-bridge inverter according to another embodiment of the present invention, and as shown in fig. 5, the known full-bridge inverter includes two bridge arm structures consisting of four IGBTs, an inverter bridge arm consisting of an IGBT10 and an IGBT20, and an inverter bridge arm consisting of an IGBT30 and an IGBT 40; wherein, the IGBT10 and the IGBT30 are controlled by PWM-A, and the IGBT20 and the IGBT40 are controlled by PWM-B;
similar to the protection circuit for a half-bridge inverter shown in fig. 3, the protection circuit shown in fig. 5 includes a current detection circuit and a judgment circuit corresponding to four IGBTs, respectively, wherein the current detection circuit 1A and the judgment circuit 1B are connected to the emitters of the IGBTs 10 in sequence; the current detection circuit 2A and the judgment circuit 2B are sequentially connected to the collector of the IGBT 20; the current detection circuit 3A and the judgment circuit 3B are sequentially connected to the collector of the IGBT 30; the current detection circuit 4A and the judgment circuit 4B are sequentially connected to the emitter of the IGBT 40;
the current detection circuit 1A-4A and the judgment circuit 1B-4B for the protection circuit of the full-bridge inverter shown in fig. 5 have the same circuit structure as the current detection circuit 1A and the judgment circuit 1B for the protection circuit shown in fig. 3, and have the same working mode and principle, and the difference is mainly that the logic and gate 31 and the logic and gate 41 for controlling the PWM-a and the PWM-B to drive the IGBT have three inputs; taking logic circuit 31 for controlling PWM-a signal as an example, its input terminals are connected to input terminal of PWM-a, and output terminal of judgment circuit 2B corresponding to IGBT20 and output terminal of judgment circuit 4B corresponding to IGBT40, respectively; that is, only when the determination circuit 2B and the determination circuit 4B output high levels at the same time, the logic and gate 31 allows the PWM-a signal at its input terminal to pass and drive the IGBT10 and the IGBT 30; accordingly, only when the determination circuit 1B and the determination circuit 3B output high levels at the same time, the logic and gate 41 allows the PWM-B signal at its input terminal to pass through and drive the IGBT20 and the IGBT 40.
FIG. 6 is a further circuit schematic of the protection circuit for a full-bridge inverter shown in FIG. 5, wherein the current detection circuit 1A corresponding to the IGBT10 includes a current sensor and a comparator connected in sequence to the emitter of the IGBT10, the protection circuit corresponding to the IGBT10The judgment circuit 1B includes an or gate and a flip-flop which are connected to the current detection circuit 1A in sequence; the current detection circuits 2A-4A and the judgment circuits 2B-4B corresponding to the IGBTs 20, 30, and 40 are similar to the current detection circuit 1A and the judgment circuit 1B corresponding to the IGBT10, and are not described again here; as shown in fig. 6, if it is necessary for the determination circuit 2B and the determination circuit 4B to output high level simultaneously, it means that PWM-B must be set to low level and corresponds to the collector-emitter current I of the IGBT20ceIs 0, corresponding to the collector-emitter current I of the IGBT40ceThe value is 0, the logic AND gate 31 can allow the PWM-A to drive the IGBT10 and the IGBT30 to work; conversely, if the PWM-B is at a high level, or the collector-emitter current of at least one of the IGBT20 and the IGBT40 does not drop to zero, the logic and gate 31 will prevent the PWM-a from driving the IGBT10 and the IGBT30, so as to prevent the bridge arm from going through, and ensure the operation safety of the IGBT.
Similarly, since the and logic gate 41 and the and logic gate 31 are symmetrically arranged in a complementary manner, the control principle of the and logic gate 41 for the PWM-B signal is the same as the control principle of the and logic gate 31 for the PWM-a signal, and the description thereof is omitted.
In an embodiment of the present invention, the clock signal CL1 for the judgment circuits 1B and 2B and the clock signal CL2 for the judgment circuits 3B and 4B may be generated by using a clock signal generation circuit shown in fig. 4, respectively, wherein two not gates of the CL1 clock signal generation circuit are connected to or gate outputs of the judgment circuits 1B and 2B, respectively, and two not gates of the CL2 clock signal generation circuit are connected to or gate outputs of the judgment circuits 3B and 4B, respectively.
When both PWM-a and PWM-B are low and the collector-emitter currents corresponding to IGBT10 and IGBT20 are 0, clock signal CL1 is a rising edge; correspondingly, the judgment circuit 1B and the judgment circuit 2B will output high levels to the logic and gate 41 and the logic and gate 31, respectively; similarly, the clock signal CL2 is a rising edge only when both PWM-a and PWM-B are low and the collector-emitter currents corresponding to IGBT30 and IGBT40 are both 0; accordingly, the judgment circuit 3B and the judgment circuit 4B will output high levels to the logic and gate 31 and the logic and gate 41, respectively. Although the half-bridge inverter and the full-bridge inverter are used to illustrate the protection circuit provided by the present invention in the above embodiments, it should be understood by those skilled in the art that the protection circuit provided by the present invention can also be used in other complementary bridge arm structures controlled by PWM, for example, fig. 7 is a schematic diagram of the protection circuit provided by the present invention for a push-pull structure, as shown in fig. 7, according to the design concept of the protection circuit provided by the present invention, the locking of the driving can be realized not only according to the PWM driving signal of the push-pull circuit, but also according to the current magnitude on the push-pull bridge arm by using two complementary logic and gates 51 and 61 arranged at the PWM input end of the push-pull circuit, and the current detection circuit and the judgment circuit complementarily arranged on the push-pull bridge arm, for example, the current detection circuit 1A and the judgment circuit 1B in fig. 7, the direct short circuit of the push-pull bridge arm is effectively prevented, and the reliability of the push-pull circuit is improved.
In an embodiment of the present invention, there is also provided a switching power supply including the protection circuit for preventing bridge arm shoot-through in the above-described embodiment.
In an embodiment of the present invention, there is also provided a charging pile including the protection circuit for preventing bridge arm shoot-through in the above embodiment.
In an embodiment of the present invention, there is also provided an inverter including the protection circuit for preventing bridge arm shoot-through in the above-described embodiment.
In an embodiment of the present invention, there is also provided a frequency converter including the protection circuit for preventing bridge arm shoot-through in the above-described embodiment.
In an embodiment of the present invention, there is also provided an Uninterruptible Power Supply (UPS), and the UPS apparatus includes the protection circuit for preventing bridge arm shoot-through in the above-described embodiment.
Although the present invention has been described by way of preferred embodiments, the present invention is not limited to the embodiments described herein, and various changes and modifications may be made without departing from the scope of the present invention.

Claims (13)

1. A protection circuit for preventing leg shoot-through, the leg including a first semiconductor device driven by a PWM-a signal and a second semiconductor device driven by a PWM-B signal, the protection circuit comprising: the first current detection circuit is connected with the bridge arm and used for detecting the leakage current of the second semiconductor device, and the first judgment circuit is connected with the first current detection circuit; the first judging circuit comprises a first OR gate and a first trigger which are connected in sequence, the input end of the first OR gate is respectively connected with the output end of the first current detecting circuit and the input end of the PWM-B signal, the output end of the first OR gate is connected with the position end of the first trigger, and the first judging circuit is used for judging whether the PWM-A signal is allowed to drive the first semiconductor device or not according to the detection result of the first current detecting circuit and the PWM-B signal; the first current detection circuit comprises a first current sensor and a first comparator which are sequentially connected to the bridge arm, the first current sensor is used for detecting leakage current of the second semiconductor device, and the first comparator compares a detection result of the first current sensor with a reference voltage and outputs a comparison result to the first judgment circuit.
2. The protection circuit of claim 1, further comprising: the second current detection circuit is connected with the bridge arm and used for detecting the leakage current of the first semiconductor device, and the second judgment circuit is connected with the second current detection circuit; the second judgment circuit is used for judging whether the PWM-B signal is allowed to drive the first semiconductor device according to the detection result of the second current detection circuit and the PWM-A signal.
3. The protection circuit according to claim 2, wherein the second current detection circuit includes a second current sensor and a second comparator connected to the bridge arm in this order, the second current sensor is configured to detect a leakage current of the first semiconductor device, and the second comparator compares a detection result of the second current sensor with a reference voltage and outputs the comparison result to the second determination circuit.
4. The protection circuit of claim 3, wherein the second determination circuit comprises a second or gate and a second flip-flop connected in sequence, an input terminal of the second or gate is connected to the output terminal of the second comparator and the input terminal of the PWM-A signal, respectively, and an output terminal of the second or gate is connected to the set terminal of the second flip-flop.
5. The protection circuit according to claim 4, further comprising a first logic circuit for controlling the PWM-A signal to drive the first semiconductor device according to a judgment result of the first judgment circuit, and a second logic circuit for controlling the PWM-B signal to drive the second semiconductor device according to a judgment result of the second judgment circuit.
6. The protection circuit according to claim 5, wherein the first logic circuit comprises a first AND gate, inputs of the first AND gate are respectively connected to the input terminal of the PWM-A signal and the output terminal QN of the first flip-flop, and an output of the first AND gate is connected to the driving terminal of the first semiconductor device; the second logic circuit comprises a second AND gate, the input end of the second AND gate is respectively connected to the input end of the PWM-B signal and the output end QN of the second trigger, and the output end of the second AND gate is connected to the driving end of the second semiconductor device.
7. The protection circuit according to claim 4, further comprising a clock signal generation circuit that generates clock signals for the first flip-flop and the second flip-flop according to detection results of the first current detection circuit and the second current detection circuit, and the PWM-A signal and the PWM-B signal.
8. The protection circuit of claim 7, wherein the clock signal generating circuit comprises a first not gate and a second not gate connected to the first or gate output and the second or gate output, respectively, and a third and gate connected to the first not gate output and the second not gate output, the outputs of the third and gate being connected to the clock signal input of the first flip-flop and the clock signal input of the second flip-flop, respectively.
9. A switching power supply comprising the protection circuit according to any one of claims 1 to 8.
10. A charging pile comprising the protection circuit according to any one of claims 1 to 8.
11. An inverter characterized by comprising the protection circuit according to any one of claims 1 to 8.
12. A frequency converter, characterized in that it comprises a protection circuit according to any one of claims 1 to 8.
13. An uninterruptible power supply comprising the protection circuit according to any one of claims 1 to 8.
CN201810372369.3A 2018-04-24 2018-04-24 Switching power supply, charging pile, inverter, frequency converter, UPS and protection circuit thereof Active CN108832805B (en)

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