CN100594679C - A dual-mode frequency divider - Google Patents
A dual-mode frequency divider Download PDFInfo
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- CN100594679C CN100594679C CN200710099548A CN200710099548A CN100594679C CN 100594679 C CN100594679 C CN 100594679C CN 200710099548 A CN200710099548 A CN 200710099548A CN 200710099548 A CN200710099548 A CN 200710099548A CN 100594679 C CN100594679 C CN 100594679C
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Abstract
The invention discloses a double-mode frequency divider, which comprises the following parts: double-mode frequency predivider, which divides frequency for high-frequency signal input by exterior to output the frequency dividing signal to programmable counter; programmable counter, which counts the input frequency dividing signal to generate output metering signal to signal selector at the first signal output end when the counter reaches N or generate output metering signal to signal selector at the second signal output end when the counter reaches M; signal selector, which gates the first orsecond signal output ends of programmable counter under mode control signal to continuously invert the condition of output end acted by clock to output the mode control signal. The invention realizesthe function of programming frequency division, which elevates the working speed of circuit and simplifies the circuit structure.
Description
Technical field
The present invention relates to electronic technology field, can be applicable in the frequency synthesizer of phase locking in the radio frequency transceiver, relate in particular to a kind of frequency divider that uses single counter to realize the bimodulus frequency division.
Background technology
Important function such as frequency synthesizer of phase locking plays in communication system synchronously, frequency conversion and channel switching are one of indispensable parts of modern communication.As shown in Figure 1, Fig. 1 is the frequency synthesizer of phase locking structural representation.Frequency synthesizer of phase locking is made up of phase frequency detector and charge pump (PFD/CP), loop filter (LPF), voltage controlled oscillator (VCO) and programmable frequency divider.
Wherein, phase frequency detector and charge pump are phase comparison devices.It compares the phase place of the output signal of input signal and voltage controlled oscillator, produces the error voltage corresponding to two signal phase differences.
The effect of loop filter is radio-frequency component and the noise in the filtering error voltage, to guarantee the desired performance of loop, increases the stability of system.
The control of the controlled voltage of voltage controlled oscillator makes the frequency of voltage controlled oscillator draw close to the frequency of input signal, locks until eliminating frequency difference.
Programmable frequency divider removes the frequency of the high-frequency signal of VCO output in N, to reach purpose identical with reference frequency when locking.
The frequency divider of frequency synthesizer must provide a frequency dividing ratio M that can programme, and under low frequency, it can be realized with a programmable counter.But when the output frequency of frequency synthesizer was very high, high-speed counter was to be difficult to realize, and can power consumption very big.The frequency divider of big power consumption makes the stand-by time of communication system shorten.
In order to address this problem, the common bimodulus frequency splitting technology that adopted of modern people, as shown in Figure 2, Fig. 2 is the structural representation of traditional dual-mode frequency divider.Traditional dual-mode frequency divider is by a dual-modulus prescaler and two counters (count value is respectively P and S and P＞S, and they all can be programmed) composition.Dual-modulus prescaler carries out frequency division to the output signal of VCO, and its frequency dividing ratio can be selected between N or N+1.During beginning, dual-modulus prescaler carries out the N+1 frequency division to the VCO output signal, S and P counter all count to the output pulse of dual-modulus prescaler, when a predetermined S value reaches, it changes the frequency dividing ratio of dual-modulus prescaler into N, after this, the S counter stops counting, and the P counter continues the output pulse of dual-modulus prescaler is counted, after its counter value reaches a certain predetermined P value, it is with itself and S counter reset, and the frequency dividing ratio with dual-modulus prescaler reverts to N+1 again simultaneously.Whole process begins again.The frequency dividing ratio of the module of being made up of P counter, S counter and dual-modulus prescaler is: M=(N+1) S+N (P-S)=PN+S changes frequency dividing ratio by changing S.When frequency process dual-modulus prescaler frequency division, after frequency greatly reduced, the design of follow-up sub-frequency divider just was reduced to the programmable counter of design, had reduced the power consumption of whole system.
In order further to reduce power consumption, dwindle the shared chip area of circuit.United States Patent (USP) 6,035,182 pairs of dual-mode frequency dividers have as shown in Figure 2 carried out further simplification.Circuit structure after the simplification as shown in Figure 3, Fig. 3 is a United States Patent (USP) 6,035, the structural representation of 182 dual-mode frequency dividers that propose.
Circuit structure after this simplification can be described as: a single counter bimodulus frequency divider has used a programmable frequency divider 308, the input 301 of this programmable frequency divider connects the RF input signal, another input termination mode control signal, this control signal is produced by programmable counter.This control signal is being controlled the frequency dividing ratio of programmable frequency divider, is exported by 314 ends of the signal behind the frequency division.This device also comprises a switch 312, and its 304 and 306 inputs are used for receiving the first and second programming indications respectively, to produce a counting controling signal 318.This counting controling signal has determined the value of counter.This programmable counter is counted 314 input signal, and produces an output signal at the output of this frequency divider.
Its principle is a frequency division in system in the cycle, and counter is carried out twice programming, makes its count value be respectively U or L.Use U still is that L is as its count value, by the state decision of output frequency division signal 302 actually.Therefore, a frequency division cycle, total frequency dividing ratio is: N=U * (P+1)+L * P.
United States Patent (USP) 6,035, the shortcoming of 182 dual-mode frequency dividers that propose is in the cycle, need carry out twice programming at a frequency division to counter, therefore needs outside (in communication system, this signal is produced by base band usually) that two path control signal is provided.This makes that the design of communication system base band is complicated, also can realize just that with control signal of Modern Communication System the general case of frequency switching is different.And, after control switch has been selected a certain signal, also needing counter is preset, this process has certain time delay, has reduced the operating rate of programmable frequency divider.
Summary of the invention
(1) technical problem that will solve
In view of this, main purpose of the present invention is to provide a kind of frequency divider that uses single counter to realize the bimodulus frequency division, counter is programmed by a control signal with realization, promote the operating rate of circuit, further simplify circuit structure, reduce circuit power consumption, dwindle chip area.
(2) technical scheme
For achieving the above object, the invention provides a kind of dual-mode frequency divider, this dual-mode frequency divider comprises:
One bimodulus pre-divider 100 is used under the control of the mode control signal that is received from trigger or latch 400 outputs, and the high-frequency signal that the outside is imported carries out frequency division, and the fractional frequency signal that obtains is exported to programmable counter 200;
One programmable counter 200 is used for the fractional frequency signal of dual-modulus prescaler 100 inputs is counted, and when rolling counters forward arrives N, produces an output count signal at first signal output part and export to signal selector 300; When rolling counters forward arrives M, produce an output count signal at the secondary signal output and export to signal selector 300, wherein, M and N are natural number, this a pair of natural concrete numerical value is by the logic state decision of the control signal able to programme of outside;
One signal selector 300, be used under the control of the mode control signal that is received from trigger or latch 400 outputs, first signal output part of gating programmable counter 200 or secondary signal output produce one and select signal to export to trigger or latch 400;
One trigger or latch 400, with the selection signal that is received from signal selector 300 is input clock, under the effect of this input clock, and the state of the output that constantly overturns, the output mode control signal, this mode control signal while is as the output signal of this dual-mode frequency divider.
In the such scheme, described dual-modulus prescaler 100 comprises a high-frequency signal input 401, a mode control signal input 412 and a fractional frequency signal output 402; When described dual-mode frequency divider was applied to phase-locked loop, described high-frequency signal input 401 was connected with voltage controlled oscillator, received the high-frequency signal that voltage controlled oscillator produces; Described mode control signal input 412 is connected with trigger or latch 400, receives the mode control signal that trigger or latch 400 produce; Described fractional frequency signal output 402 is connected with programmable counter 200, and the fractional frequency signal that dual-modulus prescaler 100 carries out obtaining behind the frequency division is exported to programmable counter 200.
In the such scheme, described programmable counter 200 comprises a fractional frequency signal input 403, a counting controling signal input 404, a reseting controling signal input 405, first signal output part 406 and secondary signal output 407; Described fractional frequency signal input 403 connects the fractional frequency signal output 402 of described dual-modulus prescaler 100; Described counting controling signal input 404 connects the control signal able to programme of outside input; Described reseting controling signal input 405 connects the selection signal output part 410 of described signal selector 300.
In the such scheme, described signal selector 300 is made of following circuit: a not gate has an output and an input, first signal output part 406 of the described programmable counter 200 of described input termination; First with the door, its first input end connects the output of not gate, second input connects the output 414 of trigger or latch 400; Second with door, secondary signal output 407, the second inputs that its first input end connects described programmable counter 200 connect the output 414 of trigger or latch 400; One or, its input connect respectively first with door, second with output, the signal of its output is respectively as the clock and the reset signal of trigger or latch 400 and programmable counter 200.
In the such scheme, described signal selector 300 comprises first signal input part 408, secondary signal input 409, signal selection control end 411 and selects signal output part 410; Described first signal input part 408 connects first signal output part 406 of described programmable counter 200; Described secondary signal input 409 connects the secondary signal output 407 of described programmable counter 200; Described signal selects control end 411 to connect the output 414 of trigger or latch 400, and it is being controlled signal selector and is selecting first signal or secondary signal actually; Described selection signal output part 410 connects the input end of clock 413 of trigger or latch 400.
In the such scheme, described trigger or latch 400 comprise a clock input 413 and an output 414; Described input end of clock 413 connects the selection signal output part 410 of described signal selector 300; The signal that described output 414 connects described signal selector 300 is selected the mode control signal input 412 of control end 411 and described dual-modulus prescaler 100.
(3) beneficial effect
From technique scheme as can be seen, the present invention has following beneficial effect:
The single counter of this use provided by the invention is realized the frequency divider of bimodulus frequency division, its counter can produce at least two count values under the control of one road programmable signal, and made full use of dual-modulus prescaler pattern state of a control, under different states, select different count values, thereby reach the purpose of bimodulus frequency division.It, outside all advantages of 182 and is still programmed to counter by a control signal except possessing United States Patent (USP) 6,035, has promoted the operating rate of circuit, has also further simplified circuit structure, has reduced circuit power consumption, has dwindled chip area.
Description of drawings
Fig. 1 is the frequency synthesizer of phase locking structural representation;
Fig. 2 is the structural representation of traditional dual-mode frequency divider;
Fig. 3 is a United States Patent (USP) 6,035, the structural representation of 182 dual-mode frequency dividers that propose;
Fig. 4 is the structural representation that the single counter of use provided by the invention is realized the frequency divider of bimodulus frequency division;
Fig. 5 is the sequential chart that the single counter of use provided by the invention is realized output port in the frequency divider of bimodulus frequency division;
Symbol description is as follows:
In Fig. 3:
301: the input port of dual-modulus prescaler;
302: the output port of dual-mode frequency divider;
304: control signal 1;
306: control signal 2;
308: dual-modulus prescaler;
312: switch;
314: the output port of dual-modulus prescaler;
In Fig. 4:
100: dual-modulus prescaler;
200: programmable counter;
300: signal selector;
400: trigger or latch;
401: the high-frequency signal input;
402: the fractional frequency signal output;
403: the fractional frequency signal input;
404: the counting controling signal input;
405: the reseting controling signal input;
406: the first signal output parts;
407: the secondary signal output;
408: the first signal input parts;
409: the secondary signal input;
410: select signal output part;
411: signal is selected control end;
412: the mode control signal input;
413: input end of clock;
414: the output of dual-mode frequency divider;
In Fig. 5:
CLK: the input clock of expression frequency divider.
Q: represent 4/5 dual-modulus prescaler output port waveform.
OUT1: the counter first output port waveform.
OUT2: the counter second output port waveform.
SOUT: signal selector output port waveform.
DOUT: whole frequency divider output port waveform.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
As shown in Figure 4, Fig. 4 is the structural representation that the single counter of use provided by the invention is realized the frequency divider of bimodulus frequency division, and this dual-mode frequency divider comprises dual-modulus prescaler 100, programmable counter 200, signal selector 300 and trigger or latch 400.
Wherein, dual-modulus prescaler 100 is used under the control of the mode control signal that is received from trigger or latch 400 outputs, and the high-frequency signal that the outside is imported carries out frequency division, and the fractional frequency signal that obtains is exported to programmable counter 200.
Trigger or latch 400, with the selection signal that is received from signal selector 300 is input clock, under the effect of this input clock, and the state of the output that constantly overturns, the output mode control signal, this mode control signal while is as the output signal of this dual-mode frequency divider.
Above-mentioned dual-modulus prescaler 100 comprises a high-frequency signal input 401, a mode control signal input 412 and a fractional frequency signal output 402.When described dual-mode frequency divider was applied to phase-locked loop, described high-frequency signal input 401 was connected with voltage controlled oscillator, received the high-frequency signal that voltage controlled oscillator produces.Mode control signal input 412 is connected with trigger or latch 400, receives the mode control signal that trigger or latch 400 produce.Fractional frequency signal output 402 is connected with programmable counter 200, and the fractional frequency signal that dual-modulus prescaler 100 carries out obtaining behind the frequency division is exported to programmable counter 200.The input of this dual-modulus prescaler connects radiofrequency signal usually, such as: in frequency synthesizer of phase locking, it is connected to the output of voltage controlled oscillator.This dual-modulus prescaler, under the effect of pattern control end signal, frequency dividing ratio can be P/P+ 1, and wherein P is a natural number.
Above-mentioned programmable counter 200 comprises a fractional frequency signal input 403, a counting controling signal input 404, a reseting controling signal input 405, first signal output part 406 and secondary signal output 407.Fractional frequency signal input 403 connects the fractional frequency signal output 402 of described dual-modulus prescaler 100.Counting controling signal input 404 connects the control signal able to programme of outside input.Reseting controling signal input 405 connects the selection signal output part 410 of described signal selector 300.
The input of this programmable counter is connected to the output of dual-modulus prescaler, the counting control end is connected to outside base band control circuit, reseting controling end is received the output of the signal selector that will mention the back, and under the effect of reset signal, its state can be changed to 0 or 1.This programmable counter is counted the output signal of dual-modulus prescaler, when rolling counters forward during to N or M, respectively first or the secondary signal output produce a pulse signal, wherein, the value of M and N is controlled by counting controling signal.To use M still be N actually as the count value of counter, depends on signal selector 300.
Above-mentioned signal selector 300 is made of following circuit:
A not gate has an output and an input, first signal output part 406 of the described programmable counter 200 of described input termination;
First with the door, its first input end connects the output of not gate, second input connects the output 414 of trigger or latch 400;
Second with door, secondary signal output 407, the second inputs that its first input end connects described programmable counter 200 connect the output 414 of trigger or latch 400;
One or, its input connect respectively first with door, second with output, the signal of its output is respectively as the clock and the reset signal of trigger or latch 400 and programmable counter 200.
Above-mentioned signal selector 300 comprises first signal input part 408, secondary signal input 409, signal selection control end 411 and selects signal output part 410.First signal input part 408 connects first signal output part 406 of described programmable counter 200.Secondary signal input 409 connects the secondary signal output 407 of described programmable counter 200.Signal selects control end 411 to connect the output 414 of trigger or latch 400, and it is being controlled signal selector and is selecting first signal or secondary signal actually.Whom selects decide by the state of control signal, when control signal is low level, after it becomes high level by a not gate earlier actually, pass through one and door together with first signal, again by one or, produce a pulse at signal selector 300 outputs, first signal is just selected.When control signal was high level, it selected secondary signal.Select signal output part 410 to connect the input end of clock 413 of trigger or latch 400.
The first input end of signal selector and second input are connected to first output and the second end output of programmable counter, and its selection control end is connected to the trigger that will mention the back or the output of latch.Under the effect of selecting control signal, optional the amounting to of signal selector counted to M (or N) and produced a selection signal at its output.
Above-mentioned trigger or latch 400 comprise a clock input 413 and an output 414.Input end of clock 413 connects the selection signal output part 410 of described signal selector 300; Output 414 connects the signal selection control end 411 of described signal selector 300 and the mode control signal input 412 of described dual-modulus prescaler 100.The output 414 of trigger or latch 400 also is the output of whole frequency divider, the output low frequency signal.
The single counter of this use provided by the invention is realized the frequency divider of bimodulus frequency division, has only used single counter to realize, and is as good as with traditional frequency divider (using two counters) on division control signal.A lot of relevant for frequency divider at the realization document of frequency synthesizer of phase locking, application in whole wireless transceiver system and control signal, do not repeat them here.
The principle of this frequency divider of brief description now is called for short the output signal of trigger or latch 400 outputs 414, and just the mode control signal of dual-modulus prescaler 100 is MC.If when MC=0, when just being low level, the frequency dividing ratio of dual-mode frequency divider (dual-module divider) is P, selector gating signal N, just first signal; Work as MC=1, when just being high level, frequency dividing ratio is P+1, selector gating signal M, and secondary signal just, and establish M＞N, MC=1 when establishing at the beginning again.So have:
N * when (P+1) input port 401 of dual-modulus prescaler 100 was arrived in individual pulse, it was counted these input pulses when the VCO input, and P+1 pulse of every input will produce a pulse at its output 402, therefore have N pulse to produce.Programmable counter is counted the output pulse of dual-modulus prescaler 100, and has two kinds of possible count values, just N and M.When the N that an is produced pulse is input to the input of programmable counter, it will produce an output pulse at first signal output part, but owing to MC=1 this moment, so signal selector will not allow this pulse by (because it is first signal, and when MC=1, gating first signal not), just the signal selector output is not exported pulse.Up to importing M * (P+1) individual pulse as VCO, when the programmable counter output just produced an output pulse, the signal selector output just had the output pulse.This pulse makes d type flip flop overturn (MC=0), and afterwards, the frequency dividing ratio of dual-modulus prescaler is changed to P; Simultaneously, programmable counter is reset, and restarts counting.When VCO exports N * P signal period, a pulse signal will appear in the output of signal selector again.Owing to MC=0 this moment, so selected passing through, this pulse makes d type flip flop overturn again (MC=1), and afterwards, the frequency dividing ratio of dual-modulus prescaler is changed to P+1, and programmable counter is reset again, and restarts counting.Thus repeatedly.Therefore, total frequency dividing ratio is: A=M * (P+1)+N * P.
Below further specify the frequency division principle of this structure frequency divider with a concrete former example.Fig. 5 is the sequential chart that the single counter of use provided by the invention is realized output port in the frequency divider of bimodulus frequency division.The pre-frequency division of the bimodulus of this frequency divider is 4/5 frequency division, when MC=1, is 5 frequency divisions, during MC=0, is 4 frequency divisions.Counter is one three digit counter, comes temporarily when reset signal, and its output is changed to zero.
According to formula: A=M * (P+1)+N * P, utilize 4/5 frequency division, in order to realize 44 frequency divisions, optional M=4, N=6.Dotted line begins to analyze sequential from figure, because MC=DOUT=1, so the frequency dividing ratio of dual-modulus prescaler is 5,
When clock CLK process M * 5=4 * 5=20 week after date, first output port of counter will have a pulse output, pulse among the figure just (1).Owing to MC=1 this moment, so one pulse output, the pulse among the figure just (2) are also arranged at the output port of signal selector.Pulse (2) makes trigger overturn, MC=0.The frequency dividing ratio of dual-modulus prescaler becomes 4, when clock CLK through M * 4=4 * 4=16 week after date, at first output port of counter a pulse output, pulse among the figure just (3) will be arranged.Yet owing to MC=0 this moment, so signal selector is not selected this pulse, just the output port at signal selector does not have pulse to occur.Through N * 4=6 * 4=24 week after date, a pulse output, pulse among the figure just (4) will be arranged up to clock CLK at second output port of counter.Owing to MC=0 this moment, so one pulse output, the pulse among the figure just (5) are also arranged at the output port of signal selector.Pulse (5) makes trigger overturn, MC=1.Finish task of using a counter to realize the bimodulus frequency division thus repeatedly.The frequency of CLK among the figure is 2.2GHz, and behind 44 frequency divisions, frequency becomes 50M, and its cycle is 20ns just.
In sum, the present invention uses a counter to realize the bimodulus frequency division, and need not external circuit is done any change, and the frequency divider that can be used as the transceiver frequency synthesizer of phase locking uses.Obviously, circuit structure has been simplified in this invention, has dwindled chip area, has reduced power consumption, has comparatively significantly practical value and economic worth.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1, a kind of dual-mode frequency divider is characterized in that, this dual-mode frequency divider comprises:
One bimodulus pre-divider (100) is used under the control of the mode control signal that is received from trigger or latch (400) output, and the high-frequency signal that the outside is imported carries out frequency division, and the fractional frequency signal that obtains is exported to programmable counter (200);
One programmable counter (200) is used for the fractional frequency signal of dual-modulus prescaler (100) output is counted, and when rolling counters forward arrives N, produces an output count signal at first signal output part and export to signal selector (300); When rolling counters forward arrives M, produce an output count signal at the secondary signal output and export to signal selector (300), wherein, M and N are natural number;
One signal selector (300), be used under the control of the mode control signal that is received from trigger or latch (400) output, first signal output part of gating programmable counter (200) or secondary signal output produce one and select signal to export to trigger or latch (400);
One trigger or latch (400), with the selection signal that is received from signal selector (300) is input clock, under the effect of this input clock, and the state of the output that constantly overturns, the output mode control signal, this mode control signal while is as the output signal of this dual-mode frequency divider.
2, dual-mode frequency divider according to claim 1 is characterized in that, described dual-modulus prescaler (100) comprises a high-frequency signal input (401), a mode control signal input (412) and a fractional frequency signal output (402);
When described dual-mode frequency divider was applied to phase-locked loop, described high-frequency signal input (401) was connected with voltage controlled oscillator, received the high-frequency signal that voltage controlled oscillator produces;
Described mode control signal input (412) is connected with trigger or latch (400), receives the mode control signal that trigger or latch (400) produce;
Described fractional frequency signal output (402) is connected with programmable counter (200), and the fractional frequency signal that dual-modulus prescaler (100) carries out obtaining behind the frequency division is exported to programmable counter (200).
3, dual-mode frequency divider according to claim 1, it is characterized in that described programmable counter (200) comprises a fractional frequency signal input (403), a counting controling signal input (404), a reseting controling signal input (405), first signal output part (406) and secondary signal output (407);
Described fractional frequency signal input (403) connects the fractional frequency signal output (402) of described dual-modulus prescaler (100);
Described counting controling signal input (404) connects the control signal able to programme of outside input;
Described reseting controling signal input (405) connects the selection signal output part (410) of described signal selector (300).
4, dual-mode frequency divider according to claim 1 is characterized in that, described signal selector (300) is made of following circuit:
A not gate has an output and an input, first signal output part (406) of the described programmable counter of described input termination (200);
First with the door, its first input end connects the output of not gate, second input connects the output (414) of trigger or latch (400);
Second with the door, its first input end connects the secondary signal output (407) of described programmable counter (200), second input connects the output (414) of trigger or latch (400);
One or, its input connect respectively first with the door, second with output, the signal of its output is respectively as trigger or latch (400), and the clock and the reset signal of programmable counter (200).
5, dual-mode frequency divider according to claim 1 is characterized in that, described signal selector (300) comprises first signal input part (408), secondary signal input (409), signal selection control end (411) and selects signal output part (410);
Described first signal input part (408) connects first signal output part (406) of described programmable counter (200);
Described secondary signal input (409) connects the secondary signal output (407) of described programmable counter (200);
Described signal selects control end (411) to connect the output (414) of trigger or latch (400), and it is being controlled signal selector and is selecting first signal or secondary signal actually;
Described selection signal output part (410) connects the input end of clock (413) of trigger or latch (400).
6, dual-mode frequency divider according to claim 1 is characterized in that, described trigger or latch (400) comprise a clock input (413) and an output (414);
Described input end of clock (413) connects the selection signal output part (410) of described signal selector (300);
Described output (414) connects the signal selection control end (411) of described signal selector (300) and the mode control signal input (412) of described dual-modulus prescaler (100).
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| CN101465645B (en) * | 2007-12-19 | 2010-12-15 | 中国科学院微电子研究所 | Decimals/integer frequency divider |
| CN101478307B (en) * | 2009-01-16 | 2012-05-23 | 复旦大学 | Dual mode 4/4.5 pre-divider |
| CN102664624B (en) * | 2012-03-29 | 2014-05-28 | 杭州电子科技大学 | Throughput pulse frequency divider circuit with low power consumption |
| CN102739239B (en) * | 2012-06-15 | 2014-11-05 | 江苏物联网研究发展中心 | High-speed low power consumption true single-phase clock 2D type two-thirds dual-mode frequency divider |
| CN103684425A (en) * | 2012-09-12 | 2014-03-26 | 比亚迪股份有限公司 | Dual-mode frequency divider circuit |
| CN103138747B (en) * | 2013-01-27 | 2016-08-03 | 长春理工大学 | SCM Based can the arbitrary integer frequency divider of preset divider ratio |
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| CN117254805B (en) * | 2023-11-20 | 2024-05-28 | 深圳市华普微电子股份有限公司 | SUB-1G full-frequency coverage frequency integrated circuit |
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| US6035182A (en) * | 1998-01-20 | 2000-03-07 | Motorola, Inc. | Single counter dual modulus frequency division apparatus |
| US6385276B1 (en) * | 2001-06-12 | 2002-05-07 | Rf Micro Devices, Inc. | Dual-modulus prescaler |
| US20060017473A1 (en) * | 2004-07-22 | 2006-01-26 | Wei Hu | Divider having dual modulus pre-scaler and an associated method |
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| CN101079631A (en) | 2007-11-28 |
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