CN202998069U - Frequency following data acquisition circuit for harmonic detection - Google Patents
Frequency following data acquisition circuit for harmonic detection Download PDFInfo
- Publication number
- CN202998069U CN202998069U CN 201220726634 CN201220726634U CN202998069U CN 202998069 U CN202998069 U CN 202998069U CN 201220726634 CN201220726634 CN 201220726634 CN 201220726634 U CN201220726634 U CN 201220726634U CN 202998069 U CN202998069 U CN 202998069U
- Authority
- CN
- China
- Prior art keywords
- frequency
- digital code
- high pass
- pass filter
- comb filter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Landscapes
- Measuring Frequencies, Analyzing Spectra (AREA)
Abstract
The utility model discloses a frequency following data acquisition circuit for harmonic detection. The frequency following data acquisition circuit comprises an oversampling modulator, a first comb filter, a first high pass filter, a frequency calculation circuit, a frequency divider, a second comb filter and a second high pass filter which are connected sequentially. The oversampling modulator is connected with the second comb filter, and the frequency calculation circuit comprises a counter which connects the first high pass filter and the frequency divider and a zero cross detection circuit which connects the first high pass filter and the counter. According to the frequency following data acquisition circuit, input data changes oversampling rate in a comb filter circuit of oversampling AD conversion through frequency following, so that the oversampling rate is enabled to change according to the frequency of an input signal, the number of input data of harmonic detection is fixed in a unit period, and calculation error is small.
Description
Technical field
The utility model relates to the harmonic wave detection field, relates in particular to a kind of frequency for the harmonic wave detection and follows data acquisition circuit.Specifically, carry out harmonic wave for electric energy metered system and detect, be mixed with the not accurate enough situation of input signal of harmonic component and frequency shift (FS), the proportion technology of following realizes that harmonic wave detects the accurate collection of input data.
Background technology
In electrical network, along with being on the increase of frequency conversion equipment and non-linear equipment, voltage is not single frequency, be mixed with increasing radio-frequency component, these high fdrequency components can cause other equipment in electrical network and seriously influence, when radio-frequency component acquires a certain degree, serious harm might appear, therefore, more and more important to the control that produces radio-frequency component in electrical network, measure so that in electrical network, harmonic components also comes into one's own accordingly.
Voltage in electrical network is meeting generation deviation more or less in production process, be not always to be desirable 50Hz, can fluctuate near 50Hz, voltage fundamental frequency in possible actual electric network is 49～51Hz, data acquisition will encounter difficulties so, or the data that collect can not accurately reflect actual conditions, can cause larger error in the subsequent calculations process.
In existing power measuring system, always there is error in measurement to harmonic wave, cause the reason of error to have a lot, a most important source of error is exactly the acquired original data of inputting when harmonic wave detects not accurate enough, so no matter how how accurate the calculating of back is, there is larger error in the capital, therefore, proposes a kind of method that improves input image data accuracy and just seems most important.
Summary of the invention
The purpose of this utility model is to provide a kind of frequency for the harmonic wave detection to follow data acquisition circuit, realizes the harmonic wave of frequency change is detected the accurate collection of input data, thus convenient follow-up harmonic wave detection computations.
The technical scheme that realizes above-mentioned purpose is:
A kind of frequency for the harmonic wave detection is followed data acquisition circuit, gather analog signal, comprise the over-sampling modulator, the first comb filter, the first high pass filter, frequency computation part circuit, frequency divider, the second comb filter and the second high pass filter that connect successively, described over-sampling modulator also connects described the second comb filter, wherein:
Described frequency computation part circuit comprises the counter that connects described the first high pass filter and frequency divider, and the zero cross detection circuit that connects described the first high pass filter sum counter.
The above-mentioned frequency that is used for the harmonic wave detection is followed data acquisition circuit, wherein,
Described over-sampling modulator receives described analog signal and with its quantification, is converted to the pulse density modulated signal, exports to respectively described the first comb filter and the second comb filter;
The first comb filter is carried out integration according to fixing over-sampling rate to the described pulse density modulated signal that receives, and obtains the first digital code, exports to described the first high pass filter;
The first high pass filter, the DC component in described the first digital code of filtering is exported to described zero cross detection circuit sum counter with filtered the first digital code;
Zero cross detection circuit carries out zero crossing to filtered the first digital code and detects, and produces the zero passage control signal to described counter;
Counter, the coupling system clock is counted filtered the first digital code, the value of output counter when receiving described zero passage control signal, i.e. the frequency of filtered the first digital code, and with counter O reset;
Frequency divider obtains corresponding divider ratio according to the frequency of described filtered the first digital code, and system clock is carried out frequency division, obtains the over-sampling clock, and this over-sampling clock is exported to described the second comb filter;
The second comb filter according to described over-sampling clock, is carried out integration to described pulse density modulated signal, obtains the second digital code, exports to described the second high pass filter;
The second high pass filter, the DC component in described the second digital code of filtering, the second digital code after output filtering.
The above-mentioned frequency that is used for the harmonic wave detection is followed data acquisition circuit, and wherein, described the first digital code and the second digital code all adopt the complement of two's two's complement.
The above-mentioned frequency that is used for the harmonic wave detection is followed data acquisition circuit, and wherein, described pulse density modulated signal is the PDM code.
The above-mentioned frequency that is used for the harmonic wave detection is followed data acquisition circuit, and wherein, described frequency is followed data acquisition circuit and comprised that also one is connected to the delay circuit between described over-sampling modulator and the second comb filter.
The beneficial effects of the utility model are: electric energy metered system (especially electronic power meter) carries out harmonic wave and detects, the utility model is for the input signal that is mixed with harmonic component and frequency shift (FS), proportion is followed technology, namely change AD(mould/number according to the input signal fundamental frequency) over-sampling rate in transfer process, make AD conversion output data data amount check in the fundamental signal one-period the same, realize the accurate collection to the input signal of frequency change.Simultaneously, the utility model noise immunity is strong, and accuracy is high.
Description of drawings
Fig. 1 is the structural representation that the frequency for the harmonic wave detection of the present utility model is followed data acquisition circuit;
Fig. 2 is the structural representation of the utility model medium frequency counting circuit;
Fig. 3 is the principle schematic of frequency divider in the utility model.
Embodiment
The utility model is described in further detail below in conjunction with accompanying drawing.
the utility model is to realize that analog signal is to the conversion of digital signal on the whole, but due to the skew of input frequency analog signal, if use fixedly over-sampling rate, the output digit signals data amount check changes along with the variation of frequency in unit period, normal use FFT conversion (fast Fourier transform) now in harmonic wave detects, require the input data amount check to fix, if in unit period, data amount check is unfixing, FFT conversion input data are inaccurate so, will make result of calculation that very large error is arranged, and this error can not fundamentally be revised, have a strong impact on certainty of measurement, therefore use over-sampling rate with frequency change to obtain that in unit period, the fixing sampled data of data amount check will reduce the error that harmonic wave detects greatly, improve precision.
See also Fig. 1, frequency for the harmonic wave detection of the present utility model is followed data acquisition circuit, gather analog signal, comprise the over-sampling modulator 1, the first comb filter 2, the first high pass filter 3, frequency computation part circuit 4, frequency divider 5, the second comb filter 6 and the second high pass filter 7 that connect successively, over-sampling modulator 1 also connects the second comb filter 6, wherein:
Over-sampling modulator 1 receives analog signal and with its quantification, is converted to PDM code (Pluse DensityModulation Signal, pulse density modulated signal), exports to respectively the first comb filter 2 and the second comb filter 6; The PDM code has reflected the mean value of the analog signal of input, the value of PDM code or be 0, or be 1, its density has reflected the size of input signal values, PDM code closeer (more than 1), and the value of input signal is larger, on the contrary, PDM code thinner (more than 0), the value of input signal is less;
The first comb filter 2 is carried out integration according to fixing over-sampling rate to the pulse density modulated signal that receives, and obtains the first digital code, exports to the first high pass filter 3; The centre frequency (in the present embodiment, centre frequency is 50Hz, corresponding mains frequency) of the analog signal that described fixing over-sampling rate correspondence is inputted;
DC component in first high pass filter 3 filtering the first digital codes reduces the dc error that the AD conversion brings, and then filtered the first digital code is exported to frequency computation part circuit 4; So that frequency computation part circuit 4 is the judgement zero crossing accurately, when making frequency computation part, counting accurately;
Frequency computation part circuit 4 is used for the frequency (that is: the frequency of the analog signal of input) of the first digital code after calculation of filtered, and this frequency is exported to frequency divider 5; See also Fig. 2, frequency computation part circuit 4 comprises the counter 41 that connects the first high pass filter 3 and frequency divider 5, and the zero cross detection circuit 42 that connects the first high pass filter 3 sum counters 41, wherein: 42 pairs of filtered the first digital codes of zero cross detection circuit are carried out zero crossing and are detected, and produce for the zero passage control signal of counting to counter 41; Counter 41 is according to the zero passage control signal that receives, and the coupling system clock is counted filtered the first digital code, the frequency of output the first digital code, and the frequency of the analog signal of namely inputting, concrete principle is as follows:
Signal has zero passage twice in one-period, be once from negative value on the occasion of, be once from the occasion of to negative value, All the time alternately occurs for the zero cross signal of whole the first digital code.In the present embodiment, digital code adopts complement of two's two's complement form to represent, highest order is-symbol position, 1 expression negative, 0 expression positive number.By judging that continuous two digital code highest orders (in the present embodiment, use 24 complement of two's two's complement representative digit codes, highest order is the 24th) produce zero cross signal.Digital code can realize the time-delay of a clock through a register, can produce foundation as control signal without register and two data of passing through register.Digital code from negative value change on the occasion of the time produce the zero passage control signal, and from being not produce the zero passage control signal on the occasion of changing to negative value, be one-period between so continuous two zero passage control signals.The coupling system clock, 41 pairs of filtered the first digital codes of counter are counted, the value of output counter when receiving the zero passage control signal, and with counter O reset, the counting of beginning next cycle, counter 41 output valves are the frequency of the analog signal of input;
Frequency divider 5 obtains corresponding divider ratio according to the frequency that receives, and system clock is carried out frequency division, obtains the over-sampling clock, and this over-sampling clock is exported to the second comb filter 6; The frequency divider that frequency divider 5 adopts in the existing market; In the present embodiment, frequency divider 5 is made of frequency division of the frequency number conversion circuit 51 and frequency dividing circuit 52, sees also Fig. 3, wherein, frequency division of the frequency number conversion circuit 51 is divider ratio with the frequency inverted that receives, and then according to divider ratio, system clock is carried out frequency division by frequency dividing circuit 52, obtains the over-sampling clock; In the present embodiment, in fact frequency division of the frequency number conversion circuit 51 is exactly a decoding circuit, with the frequency values of different range section corresponding to different divider ratios, so the divider ratio that frequency values obtains in certain error range is actually a value, therefore, the first comb filter 2 is used fixing over-sampling rates can not have influence on divider ratio and also is based on this reason, as long as the frequency values that the digital code that obtains according to fixing over-sampling rate calculates is in the resolution of required precision;
The second comb filter 6 is carried out integration according to the over-sampling clock to the pulse density modulated signal that receives, and obtains the second digital code, exports to the second high pass filter 7; The second comb filter 6 is used two clocks, one is system clock, one is the over-sampling clock, the over-sampling clock is that the frequency change of analog signal according to input changes, so no matter how how frequency analog signal changes, the number of the second digital code in the analog signal unit period of input of the second comb filter 6 outputs always fixed, thereby realizes the fixedly purpose of the interior sampled data of unit period.
DC component in second high pass filter 7 filtering the second digital codes, the second digital code after output filtering makes the data of input follow-up harmonic wave test section only contain harmonic components, makes its computing more accurate.
In addition, in fact the over-sampling clock of the second comb filter 6 needs is not and its input data (pulse density modulated signal) Complete Synchronization, that is to say, the second comb filter 6 over-sampling clock used is that the data of former input signal (pulse density modulated signal) calculate, but the actual electric network frequency offset change slow, be far smaller than the needed time of frequency computation part process, the time-delay that causes of frequency computation part just there is no impact like this.If strict being consistent can add the delay circuit (not shown) before the second comb filter 6.
The utility model realizes by adding the frequency computation part module and the frequency values that obtains is fed back to comb filter on the basis of original oversampling A/D converter, i.e. each parts product or existing techniques in realizing of all commonly using and be easy to purchase by the market.
Above embodiment is only for illustration of the utility model, but not to restriction of the present utility model, person skilled in the relevant technique, in the situation that do not break away from spirit and scope of the present utility model, can also make various conversion or modification, therefore all technical schemes that are equal to also should belong to category of the present utility model, should be limited by each claim.
Claims (5)
1. a frequency that is used for the harmonic wave detection is followed data acquisition circuit, gather analog signal, it is characterized in that, comprise the over-sampling modulator, the first comb filter, the first high pass filter, frequency computation part circuit, frequency divider, the second comb filter and the second high pass filter that connect successively, described over-sampling modulator also connects described the second comb filter, wherein:
Described frequency computation part circuit comprises the counter that connects described the first high pass filter and frequency divider, and the zero cross detection circuit that connects described the first high pass filter sum counter.
2. the frequency for the harmonic wave detection according to claim 1 is followed data acquisition circuit, it is characterized in that,
Described over-sampling modulator receives described analog signal and with its quantification, is converted to the pulse density modulated signal, exports to respectively described the first comb filter and the second comb filter;
The first comb filter is carried out integration according to fixing over-sampling rate to the described pulse density modulated signal that receives, and obtains the first digital code, exports to described the first high pass filter;
The first high pass filter, the DC component in described the first digital code of filtering is exported to described zero cross detection circuit sum counter with filtered the first digital code;
Zero cross detection circuit carries out zero crossing to filtered the first digital code and detects, and produces the zero passage control signal to described counter;
Counter, the coupling system clock is counted filtered the first digital code, the value of output counter when receiving described zero passage control signal, i.e. the frequency of filtered the first digital code, and with counter O reset;
Frequency divider obtains corresponding divider ratio according to the frequency of described filtered the first digital code, and system clock is carried out frequency division, obtains the over-sampling clock, and this over-sampling clock is exported to described the second comb filter;
The second comb filter according to described over-sampling clock, is carried out integration to described pulse density modulated signal, obtains the second digital code, exports to described the second high pass filter;
The second high pass filter, the DC component in described the second digital code of filtering, the second digital code after output filtering.
3. the frequency for the harmonic wave detection according to claim 2 is followed data acquisition circuit, it is characterized in that, described the first digital code and the second digital code all adopt the complement of two's two's complement.
4. the frequency for the harmonic wave detection according to claim 2 is followed data acquisition circuit, it is characterized in that, described pulse density modulated signal is the PDM code.
5. the frequency for the harmonic wave detection according to claim 1 and 2 is followed data acquisition circuit, it is characterized in that, described frequency is followed data acquisition circuit and comprised that also one is connected to the delay circuit between described over-sampling modulator and the second comb filter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220726634 CN202998069U (en) | 2012-12-25 | 2012-12-25 | Frequency following data acquisition circuit for harmonic detection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220726634 CN202998069U (en) | 2012-12-25 | 2012-12-25 | Frequency following data acquisition circuit for harmonic detection |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202998069U true CN202998069U (en) | 2013-06-12 |
Family
ID=48569194
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220726634 Expired - Lifetime CN202998069U (en) | 2012-12-25 | 2012-12-25 | Frequency following data acquisition circuit for harmonic detection |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202998069U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103067014A (en) * | 2012-12-25 | 2013-04-24 | 上海贝岭股份有限公司 | Frequency following data acquisition circuit used for harmonic detection |
| CN103745726A (en) * | 2013-11-07 | 2014-04-23 | 中国电子科技集团公司第四十一研究所 | Self-adaptive variable-sampling rate audio frequency sampling method |
| CN111083615A (en) * | 2018-10-19 | 2020-04-28 | 知微电子有限公司 | Sound producing apparatus |
-
2012
- 2012-12-25 CN CN 201220726634 patent/CN202998069U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103067014A (en) * | 2012-12-25 | 2013-04-24 | 上海贝岭股份有限公司 | Frequency following data acquisition circuit used for harmonic detection |
| CN103745726A (en) * | 2013-11-07 | 2014-04-23 | 中国电子科技集团公司第四十一研究所 | Self-adaptive variable-sampling rate audio frequency sampling method |
| CN103745726B (en) * | 2013-11-07 | 2016-08-17 | 中国电子科技集团公司第四十一研究所 | A kind of adaptive variable sampling rate audio sample method |
| CN111083615A (en) * | 2018-10-19 | 2020-04-28 | 知微电子有限公司 | Sound producing apparatus |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103248356B (en) | A kind of counter and implementation method based on adopting phase-locked loop pulse interpolation technology | |
| CN101876693B (en) | Electric energy metering chip-based terminal calibration system | |
| CN102819004B (en) | Comprehensive detecting and analyzing platform for performance of digital electric energy metering systems of intelligent transformer substations | |
| CN201327517Y (en) | Integrated detection device of electric power terminal | |
| CN203149027U (en) | Voltage fluctuation and flicker detection apparatus based on energy operator and frequency spectrum correction | |
| CN102565673B (en) | Highly-reliable pulse counting test system based on FPGA (Field Programmable Gate Array) | |
| CN103852637B (en) | Intelligent electric meter with fundamental wave metering function and measurement method thereof | |
| CN103067014A (en) | Frequency following data acquisition circuit used for harmonic detection | |
| CN202998069U (en) | Frequency following data acquisition circuit for harmonic detection | |
| CN102928677A (en) | Nano pulse signal acquiring method | |
| CN103543333A (en) | High-frequency signal phase difference measurement method and device | |
| CN102680728A (en) | Motor rotation speed measuring method used in precise electromechanical equipment | |
| CN104062617B (en) | Combining unit meter characteristic filed detection system and method thereof | |
| CN102538914A (en) | Electronic water meter with correction function | |
| CN103645457A (en) | On-site inspection device for electric energy meter | |
| CN103901391A (en) | Novel analog standard meter with digital electric energy meter detection function and detection method | |
| CN103135650B (en) | Current/frequency conversion circuit linearity and symmetry digital compensation method | |
| CN103983930B (en) | Electronic mutual inductor harmonic wave tester calibration equipment and method of calibration | |
| CN101556325B (en) | Method for quickly verifying electric energy error | |
| CN201707114U (en) | High-precision rapid pulse metering device | |
| CN203950131U (en) | A kind of high precision time interval measurement device based on FPGA | |
| CN103728501B (en) | A kind of continuous iron loss measurement mechanism of electrical sheet and method | |
| CN108490380A (en) | A kind of voltage current transformer on-line testing system | |
| CN100353172C (en) | Group delay test method and device thereof | |
| CN205450247U (en) | Watt -hour meter calibrating |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130612 |