WO1997027494A1

WO1997027494A1 - Delay time measuring method and pulse generator for measuring delay time for use in said measuring method

Info

Publication number: WO1997027494A1
Application number: PCT/JP1997/000154
Authority: WO
Inventors: Tadahiko Baba
Original assignee: Advantest Corporation
Priority date: 1996-01-25
Filing date: 1997-01-24
Publication date: 1997-07-31
Also published as: GB9720222D0; GB2316493A; KR19980703081A; TW320686B; DE19780113T1; JPH09203772A

Abstract

A method for accurately measuring the delay time of a signal path (10) constituted by an IC of a CMOS structure in a state which is the same as, or approximate to, the actual operation state. A loop oscillation circuit including the signal path (10) is constittuted, and is brought into a loop oscillation state by feeding a start pulse ST to the circuit. An interpolation pulse P1 having a frequency which is the same as, or approximate to, the frequency of the pulse signal propagated with the signal path is in an actual operation state, is inserted, this interpolation pulse P1 and the loop oscillation signal PLO are fed to the signal path, and the signal path is brought into the substantially same temperature state as that of the actual operation state. The cycle of the loop oscillation signal PLO is measured under this state so as to measure the delay time of the signal path.

Description

Description: Delay time measuring method and delay time measuring pulse generator used for implementing this method

The present invention generally relates to a delay time measuring method suitable for use in measuring a delay time of a signal transmitted through each signal path in an apparatus having a plurality of signal paths. A delay time measuring method for measuring the delay time of each signal path with the signal path being almost the same as or close to the actual operation state and measuring the delay time of this signal path, and the delay time measurement used for implementing this method BACKGROUND OF THE INVENTION 1. Field of the Invention

For example, in an IC test apparatus (generally called an IC tester) for testing various semiconductor integrated circuits (hereinafter referred to as Ic), a test signal of a predetermined pattern is applied to each input terminal of an IC under test (IC under test). The response output signal is compared with the expected value signal, and a failure (FAIL) signal is generated each time the two signals do not match. Based on the generated failure signal, the I under test is Therefore, the IC test apparatus is provided with at least the number of test signal supply paths, ie, signal paths, equal to the number of input terminals of the IC under test. It is configured to test a large number of ICs under test, such as 16, 32, and 64, so that a large number of ICs can be tested in a short time. Therefore, in practice, the signal path of channel 100 Incidentally, the phase of the test signal of a predetermined pattern given to each input terminal of the IC under test needs to be adjusted to the intended phase according to the purpose of the test. For this purpose, the delay time in the signal path of each test signal must be given as a known value, and preferably, the signal paths of all test signals have the same delay time ( ^s ). Therefore, conventionally, in the field of IC test equipment, measuring the delay time of each test signal supply path is regularly performed, and the variation of the delay time is measured based on the measurement result. To get the same delay time Cleaning work is also underway.

Not only IC test equipment, but also electronic devices and integrated circuit devices that are configured to supply signals (pulses) such as clock signals to subsequent circuits or elements (components) through each of a plurality of signal paths. Also, in a test device or various measuring devices for other electronic components and elements other than an IC having a plurality of signal paths, the delay time of a signal propagating through each signal path is measured, and based on the measurement result. Therefore, it is necessary to perform an adjustment operation for eliminating the variation of the delay time to make the same delay time, and an operation for adjusting the delay time so that the signal is supplied to a subsequent circuit or element with a predetermined phase.

The work of adjusting the delay time so as to eliminate the variation in the delay time of each signal path and the work of adjusting the delay time so that a signal is supplied at a predetermined phase are generally called skew adjustment.

An example of a conventional delay time measuring method will be described with reference to FIG. FIG. 3 shows a circuit configuration in which the delay time measuring device 20 used for carrying out this delay time measuring method is connected to one signal path 10. In general, each signal path 10 is composed of a signal path 11 in which a plurality of logic elements are cascade-connected, and a variable delay means 12 inserted in the signal path. The variable delay means 12 is provided for adjusting the delay time of the signal path 10. This signal path 10 can be regarded as one of a plurality of signal paths for supplying a clock signal (timing signal) from the timing signal generator to the device under test, for example, in various measuring apparatuses. Further, in the IC test apparatus, it can be regarded as one of a plurality of signal paths for supplying a test signal of a predetermined pattern from the pattern generator to the IC under test.

In order to measure the delay time of the signal path 10, a delay time measuring device 20 is connected to the input terminal 14 of the signal path 10. The output terminal 13 of the signal path 10 is connected to the delay time measuring device 20 via the connection line 21, and the signal path 10 → the output terminal 13 → the connection line 21 → the delay time measuring device 20 → A loop of the input end 14 of the signal path 10 is formed. The delay time measuring device 20 includes a start pulse generator 22 that supplies a start pulse ST for loop oscillation to the signal iTO10, and a counter 23 that measures the period of the pulse circulating in the loop. ing. Next, a delay time measuring method will be described. When one start pulse ST is input to the input terminal 14 of the signal path 10 from the start pulse generator 22, the start pulse ST is output to the output terminal 13 after a delay time τ seconds generated by the signal path 10 has elapsed. Assuming that the delay time of the connection path 21 is sufficiently smaller than the delay time of the signal path S 10 and can be ignored, the pulser ^s ′ which has propagated through the signal path 10 to the input terminal 14 after τ seconds is fed back. The returned pulse is output again at the output terminal 13 of the signal path 10 a second later, and is returned to the input terminal 14 again. Loop circuit including a signal path 10 by the repetition, as shown in FIG. 4, a loop oscillation state having a period of delay time τ with the signal path 10 force ⁵ '. The counter 23 measures the cycle of the loop oscillation signal P LO and obtains the delay time τ of the signal path 10.

In the above conventional delay time measurement method, the delay time τ of the signal path 10 is short, and the frequency of the loop oscillation signal PLO is close to the frequency of the actual operation of the signal path 10 (hereinafter referred to as actual operation). With frequency, it is possible to measure a delay time that is quite close to the delay time of the signal path during actual operation. But force ^s et al., Since the miniaturization and low power consumption 'is required as a recent trend, various measuring devices, IC (MOS · IC) of MOS structure in the circuit, such as a test device, in particular CMOS ( There is a tendency to make heavy use of complementary MOS (IC) structure ICs. CMOS-structured ICs have the advantage that they consume much less power and can be more compact, so they can be made smaller, which is convenient in this respect.

However, the signal path circuit constituted by 1 C having the 105 \ 105 structure has a relatively long signal propagation delay time. Therefore, when the signal path 10 as described above is constituted by an IC having a CMOS structure, When the above-described conventional delay time measuring method is applied to measure the delay time τ and the loop circuit including the signal path 10 is loop-oscillated, the loop oscillation frequency becomes a relatively low frequency.

As an example, if a circuit from the generation of a test signal waveform of a predetermined pattern in the IC test equipment to the supply of the test signal to the terminal of the IC under test is composed of a CMOS structure, the delay time Is about 100 η s If the delay time is 100 ns, the loop oscillation frequency is l / 100 ns = 10 MHz.

On the other hand, in IC test equipment, the frequency of the test signal is as high as about 100 MHz. Is set to For this reason, a large difference force ^s occurs between the frequency of the loop oscillation and the frequency of the actual operation.

For example, when a high-frequency timing (clock) signal is used in various measuring devices and electronic devices, if the signal path to be supplied with the timing signal power ⁵ 'is constituted by an IC having a CMOS structure, the above-described IC test is performed. As in the case of the device, there is a large difference between the loop oscillation frequency and the frequency in actual operation.

Another disadvantage of the IC of the CMOS structure is that power consumption varies depending on the operation speed because it has a characteristic of consuming power only when the state of the active element is inverted. For example, when the signal path 10 operating at 10 Ο Μ 時に時に at the time of operation is loop-oscillated at 1 ある周波数周波数 which is the 1/10 frequency, and the delay time is measured. In other words, the temperature inside the IC is different from that during actual operation because the power consumption is different between 10Ο Μ Μ ζ and 1Ο Μ Η ζ. Since the IC delay time τ of the CMOS structure changes depending on the internal temperature of the IC, there is a disadvantage that a correct delay time during actual operation cannot be measured. Disclosure of the invention

A first object of the present invention is to provide a delay time measuring method capable of measuring a delay time substantially equal to a delay time of a signal path in an actual operation state. A second object of the present invention is to provide a pulse generator for measuring a delay time used for implementing the above-described method for measuring a delay time according to the present invention.

According to the present invention, a loop oscillation circuit including a signal path for measuring a delay time is configured, and when the signal path is in an actual operation state within a cycle of a loop oscillation signal of the loop oscillation circuit. A signal having a frequency equal to or close to the frequency of a signal propagating through this signal path is inserted into the signal path, and the above-described loop signal and a signal inserted within the cycle of the loop oscillation signal are propagated through the signal path. The signal path is set to substantially the same state as the actual operation state, the loop oscillation signal of the loop oscillation circuit is taken out, the cycle is measured, and the measured cycle is set as the delay time of the signal path. A method is provided for achieving the first objective.

In a preferred embodiment, the above-mentioned circuit is constituted by an IC having a CMOS structure. It is, within the period of the loop oscillation signal substantially equal interpolated pulse power to the frequency of the signal which the signal path to propagate the signal path to the actual operating conditions near ^Rutoki? Is揷input.

In addition, when the number of interpolation pulses inserted in the cycle of the loop oscillation signal is set in the storage means in advance and the counting means counts one more interpolation pulse than the set number of interpolation pulses, The counting means generates an output signal, and measures the delay time of the signal path from the period of the output signal of the counting means.

Furthermore, according to the present invention, a start pulse generator for generating a start pulse for causing a loop oscillation circuit including a signal path whose delay time is to be measured to oscillate in a loop, and in synchronization with the loop oscillation signal of the loop oscillation circuit A synchronous oscillation that oscillates and oscillates a pulse signal having a frequency equal to or close to the frequency of the pulse signal propagating through the signal path when the signal path is in an actual operation state within the cycle of the loop oscillation signal. a circuit, a storage means for storing the number of pulses signal oscillating in a cycle of the synchronous oscillator ^power? the loop oscillator signal, the synchronizing oscillation circuit of a pulse signal that oscillates in a circumferential phase of the loop oscillator signal A counter for counting the number of pulses, and counting the number of pulse signals oscillated in the cycle of the loop oscillation signal by the number stored in the storage means by the power counter. Later, when one more pulse signal is counted, the gate means for stopping the oscillation of the synchronous oscillation circuit, the loop oscillation signal propagating along the signal path and fed back, and the period of the loop oscillation signal A pulse extracting means for extracting only the loop oscillation signal from the pulse train composed of the pulse signal oscillated in the step, and returning the counter to an initial state by the loop oscillation signal extracted by the pulse extracting means; And a control means for restarting the oscillation of the oscillation circuit. A pulse generation device for delay time measurement used to carry out the delay time measurement method is provided, and the second object is achieved.

According to the delay time measuring method of the present invention, the signal path whose delay time is to be measured is substantially the same as the actual operation state, and the delay time of the signal path is measured in the same operation state as the actual operation state. . Therefore, a correct delay time substantially equal to the delay time in the actual operation state of the signal path can be obtained.

According to the pulse generator for measuring delay time of the present invention, a relatively simple The signal path can be brought into the same state as the actual operation state by the circuit configuration. Therefore, the implementation of the delay time measuring method according to the present invention is facilitated. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram showing a circuit configuration of a delay time measuring pulse generator used for carrying out the delay time measuring method according to the present invention. .

FIG. 2 is a timing chart for explaining the operation of the delay time measuring pulse generator shown in FIG.

FIG. 3 is a block diagram showing a circuit configuration of a delay time measuring device used for implementing the conventional delay time measuring method.

Figure 4 is the best mode for carrying out the _c invention is a timing Chiya one bets for explaining the operation of the delay time measuring device shown in FIG. 3

Hereinafter, the delay time measurement pulse generator 3 0 which is used for _c Figure 1 to implement the delay time measuring method according to the invention to be described in detail with reference to FIGS. 1 and 2 for the embodiment of the present invention 1 shows a circuit configuration connected to one signal line 10. In this embodiment, as in the case of the signal path 10 shown in FIG. 3, each signal path 10 has a signal path in which a plurality of logic elements are connected in cascade and a variable delay means inserted in this signal path. It is composed of Further, each signal i 0 can be regarded as one of a plurality of signal paths for supplying a timing signal from a timing signal generator to a device under test in various measurement circuits, and in an IC test apparatus, It can be regarded as one of a plurality of signal paths for supplying a test signal of a predetermined pattern from the pattern generator to the IC under test.

In order to use the delay time measurement method according to the present invention, a pulse generator 30 for delay time measurement is connected to the input terminal 14 of the signal path 10 and the signal path 10 has the same frequency as that of the signal propagating during actual operation. Supply a pulse with a frequency close to it.

Since the output terminal 13 of the signal path 10 is connected to the delay time measuring pulse generator 30 by the connection path 21, the signal path 10 → the output terminal 13 → the connection path 2 1—delay A loop consisting of a pulse generator for delay time measurement 30 → an input terminal 14 of the signal path 10 is formed.

The pulse generator for delay time measurement 30 includes a start pulse generator 35 for generating a start pulse ST for loop oscillation, and a counter 41 for receiving a loop oscillation signal PLO fed back through the connection path 21. , and that the counter 4 1 and the control hand stage 4 2 for controlling is supplied to the connection path 2 1 loop oscillation signal PLO force ^s' non-inverting input is fed back through the output of the counter 4 1 is supplied to the inverting input Gate 31; storage means 38 for storing the number of interpolation pulses PI that can be entered within the loop oscillation cycle; output of AND gate 31 and output power ^{s of} start pulse generator 35 The value of the interpolation pulse PI stored in the storage means 38 is preset in the synchronous oscillating circuit 36, the counter 39 supplied with the output power of the synchronous oscillating circuit 36, and the power counter 39. And control means 40 for .

The synchronous oscillating circuit 36 includes an output of the AND gate 31, an output of the start pulse generator 35, an output of the synchronous oscillating circuit 36, an OR gate 32 supplied with a power of ⁵ ft, and an OR gate 32. A pulse shaping circuit 33 for shaping the output; and an AND gate 34 to which the output of the pulse shaping circuit 33 and the output of the counter 39 are input, and the output power ^s signal path of the AND gate 34 Supplied to input terminal 14 of 10. Therefore, since the AND gate 31 and the synchronous oscillation circuit 36 form a part of the feedback loop, the signal path 10, the connection path 21, the AND gate 31, and the synchronous oscillation circuit 36 (OR gate 3) 2. The pulse shaping circuit 33 and AND gate 34) constitute a loop oscillation circuit. Thus, when the start pulse ST is supplied from the start pulse generator 35 to the synchronous oscillation circuit 36, loop oscillation starts and is determined by the delay time τ of the signal path 10 as shown in FIG. 2A. The loop oscillation state in which the loop oscillation signal PL0 goes around the above-mentioned loop in a cycle.

In the delay time measuring method according to the present invention, as shown in FIG.

In Te period of P _{L 0} (thus, between two adjacent loops oscillation signal PLO) to揷入interpolation pulse P i. The frequency of the interpolation pulse PI is selected to be equal to or close to the frequency of the signal propagating through the signal path 10 in the actual operation state. Therefore, the frequency of the interpolation pulse P i may differ by the apparatus ^power?, Known Value.

When an interpolation pulse PI having a frequency equal to or close to the frequency of the signal transmitted on the signal path 10 in the actual operation state is inserted within the period of the loop oscillation signal PLO, the interpolation pulse PI becomes the loop oscillation signal PL. The signal propagates along the signal path 10 together with 0. Therefore, the signal path 10 is in the same state as the actual state or a state close thereto. As a result, the power consumed in the signal path 10 is substantially the same as the power consumed in the actual operation, so that the temperature fluctuation of the signal 10 is also substantially the same as in the actual operation. Therefore, according to the delay time measuring method of the present invention, the delay time of the signal path 10 can be measured in a temperature fluctuation state substantially the same as the temperature fluctuation of the signal path 10 in the actual operation state. be constituted by eg signal path 1 0 force IC of ^S CM 0 S structure, it is possible to measure the delay time of the signal path 1 0 in the actual operation is substantially the same as the correct delay time.

The synchronous oscillation circuit 36 includes a return path 37 for immediately returning the pulse obtained at the output of the AND gate 34 to the OR gate 32, an OR gate 32, a pulse shaping circuit 33, and an AND gate 34. Here, the case where the synchronous oscillation circuit is configured by the loop configured by the above is shown. Therefore, the short loop circuit including the feedback path 37 generates the interpolation pulse PI having a frequency equal to or close to the frequency of the signal propagating through the signal path 10 in the actual operation state. The pulse shaping circuit 33 shapes the waveform of the input pulse into a pulse having a constant pulse width, and performs an operation of amplifying the peak value of the pulse to a predetermined value. The loop oscillation operation power is maintained by this amplification operation.

The number of interpolation pulses PI inserted in the oscillation period τ of the loop oscillation circuit including the signal path 10 is stored in the storage means 38 of the pulse generator 30 for measuring delay time. The oscillation cycle of the loop oscillation circuit is a force obtained by measurement.This measured value may be an approximate value.c Assuming that the number of interpolation pulses PI inserted in the oscillation cycle τ is N, the numerical value is stored in the storage means 38. Set N. This value N is first preset in the counter 39 by the start pulse ST under the control of the control means 40. The counter 39 counts the interpolation pulse PI, which is the oscillation output of the synchronous oscillation circuit 36, and subtracts (1 1) from the preset value N by one each time the interpolation pulse PI is input. Counter 3 9 When the next pulse is counted after the preset value N of the counter becomes 0 and the number of counted interpolation pulses PI matches the numerical value N set in the storage means 38, the output of the counter 39 becomes L (low level). ) Fall to logic. As a result, the AND gate 34 is closed (off), so that the oscillation of the synchronous oscillation circuit 36 is temporarily stopped.

The loop oscillation signal PLO fed back from the signal path 10 through the connection path 21 is input to the control means 40 through the AND gate 31 and stored in the storage means 38 under the control of the control means 40. The value N is reset to counter 39 again. Since the output of the counter 39 is returned to the H (high level) logic by the presetting of the numerical value N, the AND gate 34 is in an open (on) state (enabled state).

—Pass oscillation signal P L 0 is passed. As a result, the oscillation operation power s of the synchronous oscillation circuit 36 is restarted.

The AND gate 31 cooperates with the counter 41 and the control means 42 to perform an operation of extracting only the loop oscillation signal P L0 from the pulse train fed back through the connection path 21. That is, an operation of extracting the first pulse from a pulse train consisting of one loop oscillation signal P LO and a train of interpolation pulses PI following it is performed. Like the counter 39, the counter 41 presets the numerical value N stored in the storage means 38 under the control of the control means 42 at the timing of the start pulse ST and the loop oscillation signal PLO. You. When a numerical value N is preset in the counter 41 from the storage means 38, the counter 41 becomes H logic, so that one input of the AND gate 31 is supplied with L logic which is an inverted output thereof. . Therefore, the AND gate 31 is closed, and the passage of the pulse train following the loop oscillation signal P 0 is prevented.

The counter 41 decrements (−1) the preset value N by one each time the interpolation pulse PI fed back through the connection path 21 is input. When the next interpolated Hals PI is counted after the preset value N becomes 0, the output of the counter 41 falls to L logic, and the AND gate 31 is opened. Therefore, the loop oscillation signal PLO that has been fed back passes through the AND gate 31 and is input to the control means 40 and 42, so that the counters 39 and 41 are preset. By this preset, the AND gate 31 is returned to the closed state, and eventually the AND gate 31 passes only the loop oscillation signal PLO. Thus, the output cycle of counter 39 or 41 (Fig. 2C) By measuring the delay time, the delay time of the signal path 10 can be measured. Since the loop oscillation signal PLO and the interpolation pulse PI force ^f propagate through this signal path 10, the signal path 10 has substantially the same state as in the actual operation, and therefore, the loop oscillation signal PL shown in FIG. The cycle of 0 is substantially the same as the delay time of the signal path 10 in the actual operation. That is, the correct delay time of the signal path 10 can be measured.

In the pulse generator for measuring delay time described above, the AND gate 34 is controlled by the counter 39 and the control means 40. Separately, a counter 41 and a control means 42 are provided to provide the AND gate 31. However, the counter 39 and the control means 40 may be shared without providing the counter 41 and the control means 42 separately. Further, it goes without saying that a synchronous oscillator of another type or configuration may be used, in which the synchronous oscillation circuit 36 is a loop oscillation circuit.

As described above, according to the present invention, even when the oscillation frequency of the loop oscillation circuit including the signal path is low, the propagation delay time of the signal path is long. Since the delay time of the signal path is measured by inserting an interpolation pulse with a frequency equal to or close to the frequency of the propagating signal into the loop oscillation cycle, the signal path operates with almost the same power consumption as in the actual operation. And the temperature fluctuations are also substantially the same. As a result, even if the signal path is largely affected by temperature fluctuations, as in the case where the signal path is composed of CMOS-structured ICs, the signal path (IC chip) is at almost the same temperature state as in actual operation. Since the delay time is measured, the remarkable advantage that the correct delay time without error can be measured is obtained.

Claims

The scope of the claims

1. A method for measuring a delay time of the signal path by configuring a loop oscillation circuit including a signal path whose delay time is to be measured and measuring a period of an oscillation signal of the loop oscillation circuit. ,

A signal having a frequency equal to or close to the frequency of a signal propagating through the signal path when the signal path is in an actual operating state is inserted into the cycle of the oscillation signal of the loop oscillation circuit. The signal inserted within the cycle of the oscillating signal is propagated through the signal path to make the signal path substantially the same as the actual operation state, and the oscillation signal of the loop oscillation circuit is extracted. A method for measuring a delay time, comprising measuring the period and using the measured period as the delay time of the signal path.

2. The method according to claim 1, wherein said signal path is constituted by an IC having a CMOS structure.

3. The signal to be inserted within the period of the oscillation signal is a pulse signal. The number of pulse signals to be inserted is set in the storage means in advance, and the number of pulse signals one more than this set number of pulse signals is counted. 2. The method according to claim 1, wherein the period of the signal output from the counting means is measured at the time, and the measured period is used as the delay time of the signal path.

4. The signal path according to claim 1, wherein the signal path is one of a plurality of signal paths for supplying a timing signal from a timing signal generation unit to a device under test in various measuring apparatuses. the method of.

5. The signal path according to claim 1, wherein the signal path is one of a plurality of signal paths for supplying a test signal of a predetermined pattern from the pattern generator to the IC under test in the IC test apparatus. The method described in.

6. Perform the delay time measurement method according to any one of claims 1 to 5. Pulse generator for measuring the delay time used for generating a start pulse for loop oscillation of a loop oscillation circuit including a signal path for measuring the delay time When,

A pulse signal oscillating in synchronization with the loop oscillation signal of the loop oscillation circuit and having a frequency equal to or close to the frequency of the pulse signal propagating through the signal path when the signal path is in an actual operation state. A synchronous oscillation circuit that oscillates within the cycle of the loop oscillation signal,

Storage means for storing the number of pulse signals oscillating in the period of the above-mentioned synchronous oscillation circuit power ^s ' the above-mentioned loop-generated Si symbol

A counter for counting the number of pulse signals oscillating within the period of the above-mentioned loop-generated Si signal;

After counting the number of pulse signals oscillated in the cycle of the loop oscillation signal by the number stored in the counter memory storage means and counting one more pulse signal, the oscillation of the synchronous oscillation circuit is stopped. Gate means for causing

Pulse extracting means for extracting only the loop oscillation signal from a pulse train composed of the loop oscillation signal that propagates through the signal path and returns and the pulse signal oscillated within the cycle of the loop oscillation signal;

A pulse generator for delay time measurement, wherein the counter is reset to an initial state by the loop oscillation signal extracted by the pulse extraction means, and control means for restarting oscillation of the synchronous oscillation circuit is provided. .