WO1997027494A1 - Procede de mesure d'un retard et generateur d'impulsions destine a mesurer le retard selon le procede - Google Patents

Procede de mesure d'un retard et generateur d'impulsions destine a mesurer le retard selon le procede Download PDF

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Publication number
WO1997027494A1
WO1997027494A1 PCT/JP1997/000154 JP9700154W WO9727494A1 WO 1997027494 A1 WO1997027494 A1 WO 1997027494A1 JP 9700154 W JP9700154 W JP 9700154W WO 9727494 A1 WO9727494 A1 WO 9727494A1
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WO
WIPO (PCT)
Prior art keywords
signal
delay time
signal path
pulse
loop
Prior art date
Application number
PCT/JP1997/000154
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English (en)
Japanese (ja)
Inventor
Tadahiko Baba
Original Assignee
Advantest Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corporation filed Critical Advantest Corporation
Priority to DE19780113T priority Critical patent/DE19780113T1/de
Priority to GB9720222A priority patent/GB2316493A/en
Publication of WO1997027494A1 publication Critical patent/WO1997027494A1/fr

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3016—Delay or race condition test, e.g. race hazard test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31937—Timing aspects, e.g. measuring propagation delay

Definitions

  • the present invention generally relates to a delay time measuring method suitable for use in measuring a delay time of a signal transmitted through each signal path in an apparatus having a plurality of signal paths.
  • a delay time measuring method for measuring the delay time of each signal path with the signal path being almost the same as or close to the actual operation state and measuring the delay time of this signal path, and the delay time measurement used for implementing this method BACKGROUND OF THE INVENTION 1.
  • an IC test apparatus for testing various semiconductor integrated circuits (hereinafter referred to as Ic) for testing various semiconductor integrated circuits (hereinafter referred to as Ic)
  • Ic semiconductor integrated circuits
  • a test signal of a predetermined pattern is applied to each input terminal of an IC under test (IC under test).
  • the response output signal is compared with the expected value signal, and a failure (FAIL) signal is generated each time the two signals do not match.
  • FAIL failure
  • the I under test is Therefore, the IC test apparatus is provided with at least the number of test signal supply paths, ie, signal paths, equal to the number of input terminals of the IC under test.
  • the signal path of channel 100 it is configured to test a large number of ICs under test, such as 16, 32, and 64, so that a large number of ICs can be tested in a short time. Therefore, in practice, the signal path of channel 100 Incidentally, the phase of the test signal of a predetermined pattern given to each input terminal of the IC under test needs to be adjusted to the intended phase according to the purpose of the test. For this purpose, the delay time in the signal path of each test signal must be given as a known value, and preferably, the signal paths of all test signals have the same delay time ( s ). Therefore, conventionally, in the field of IC test equipment, measuring the delay time of each test signal supply path is regularly performed, and the variation of the delay time is measured based on the measurement result. To get the same delay time Cleaning work is also underway.
  • IC test equipment not only IC test equipment, but also electronic devices and integrated circuit devices that are configured to supply signals (pulses) such as clock signals to subsequent circuits or elements (components) through each of a plurality of signal paths.
  • signals pulses
  • the delay time of a signal propagating through each signal path is measured, and based on the measurement result. Therefore, it is necessary to perform an adjustment operation for eliminating the variation of the delay time to make the same delay time, and an operation for adjusting the delay time so that the signal is supplied to a subsequent circuit or element with a predetermined phase.
  • the work of adjusting the delay time so as to eliminate the variation in the delay time of each signal path and the work of adjusting the delay time so that a signal is supplied at a predetermined phase are generally called skew adjustment.
  • FIG. 3 shows a circuit configuration in which the delay time measuring device 20 used for carrying out this delay time measuring method is connected to one signal path 10.
  • each signal path 10 is composed of a signal path 11 in which a plurality of logic elements are cascade-connected, and a variable delay means 12 inserted in the signal path.
  • the variable delay means 12 is provided for adjusting the delay time of the signal path 10.
  • This signal path 10 can be regarded as one of a plurality of signal paths for supplying a clock signal (timing signal) from the timing signal generator to the device under test, for example, in various measuring apparatuses.
  • the IC test apparatus it can be regarded as one of a plurality of signal paths for supplying a test signal of a predetermined pattern from the pattern generator to the IC under test.
  • a delay time measuring device 20 is connected to the input terminal 14 of the signal path 10.
  • the output terminal 13 of the signal path 10 is connected to the delay time measuring device 20 via the connection line 21, and the signal path 10 ⁇ the output terminal 13 ⁇ the connection line 21 ⁇ the delay time measuring device 20 ⁇
  • a loop of the input end 14 of the signal path 10 is formed.
  • the delay time measuring device 20 includes a start pulse generator 22 that supplies a start pulse ST for loop oscillation to the signal iTO10, and a counter 23 that measures the period of the pulse circulating in the loop. ing. Next, a delay time measuring method will be described.
  • the start pulse ST When one start pulse ST is input to the input terminal 14 of the signal path 10 from the start pulse generator 22, the start pulse ST is output to the output terminal 13 after a delay time ⁇ seconds generated by the signal path 10 has elapsed. Assuming that the delay time of the connection path 21 is sufficiently smaller than the delay time of the signal path S 10 and can be ignored, the pulser s ′ which has propagated through the signal path 10 to the input terminal 14 after ⁇ seconds is fed back. The returned pulse is output again at the output terminal 13 of the signal path 10 a second later, and is returned to the input terminal 14 again.
  • Loop circuit including a signal path 10 by the repetition as shown in FIG. 4, a loop oscillation state having a period of delay time ⁇ with the signal path 10 force 5 '.
  • the counter 23 measures the cycle of the loop oscillation signal P LO and obtains the delay time ⁇ of the signal path 10.
  • the delay time ⁇ of the signal path 10 is short, and the frequency of the loop oscillation signal PLO is close to the frequency of the actual operation of the signal path 10 (hereinafter referred to as actual operation). With frequency, it is possible to measure a delay time that is quite close to the delay time of the signal path during actual operation.
  • various measuring devices, IC (MOS ⁇ IC) of MOS structure in the circuit such as a test device, in particular CMOS ( There is a tendency to make heavy use of complementary MOS (IC) structure ICs.
  • CMOS-structured ICs have the advantage that they consume much less power and can be more compact, so they can be made smaller, which is convenient in this respect.
  • the signal path circuit constituted by 1 C having the 105 ⁇ 105 structure has a relatively long signal propagation delay time. Therefore, when the signal path 10 as described above is constituted by an IC having a CMOS structure, When the above-described conventional delay time measuring method is applied to measure the delay time ⁇ and the loop circuit including the signal path 10 is loop-oscillated, the loop oscillation frequency becomes a relatively low frequency.
  • the frequency of the test signal is as high as about 100 MHz. Is set to For this reason, a large difference force s occurs between the frequency of the loop oscillation and the frequency of the actual operation.
  • Another disadvantage of the IC of the CMOS structure is that power consumption varies depending on the operation speed because it has a characteristic of consuming power only when the state of the active element is inverted. For example, when the signal path 10 operating at 10 ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ at the time of operation is loop-oscillated at 1 ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ which is the 1/10 frequency, and the delay time is measured. In other words, the temperature inside the IC is different from that during actual operation because the power consumption is different between 10 ⁇ ⁇ ⁇ ⁇ and 1 ⁇ ⁇ ⁇ ⁇ . Since the IC delay time ⁇ of the CMOS structure changes depending on the internal temperature of the IC, there is a disadvantage that a correct delay time during actual operation cannot be measured. Disclosure of the invention
  • a first object of the present invention is to provide a delay time measuring method capable of measuring a delay time substantially equal to a delay time of a signal path in an actual operation state.
  • a second object of the present invention is to provide a pulse generator for measuring a delay time used for implementing the above-described method for measuring a delay time according to the present invention.
  • a loop oscillation circuit including a signal path for measuring a delay time is configured, and when the signal path is in an actual operation state within a cycle of a loop oscillation signal of the loop oscillation circuit.
  • a signal having a frequency equal to or close to the frequency of a signal propagating through this signal path is inserted into the signal path, and the above-described loop signal and a signal inserted within the cycle of the loop oscillation signal are propagated through the signal path.
  • the signal path is set to substantially the same state as the actual operation state, the loop oscillation signal of the loop oscillation circuit is taken out, the cycle is measured, and the measured cycle is set as the delay time of the signal path.
  • a method is provided for achieving the first objective.
  • the above-mentioned circuit is constituted by an IC having a CMOS structure. It is, within the period of the loop oscillation signal substantially equal interpolated pulse power to the frequency of the signal which the signal path to propagate the signal path to the actual operating conditions near Rutoki? Is ⁇ input.
  • the counting means when the number of interpolation pulses inserted in the cycle of the loop oscillation signal is set in the storage means in advance and the counting means counts one more interpolation pulse than the set number of interpolation pulses, the counting means generates an output signal, and measures the delay time of the signal path from the period of the output signal of the counting means.
  • a start pulse generator for generating a start pulse for causing a loop oscillation circuit including a signal path whose delay time is to be measured to oscillate in a loop, and in synchronization with the loop oscillation signal of the loop oscillation circuit
  • a synchronous oscillation that oscillates and oscillates a pulse signal having a frequency equal to or close to the frequency of the pulse signal propagating through the signal path when the signal path is in an actual operation state within the cycle of the loop oscillation signal.
  • a circuit a storage means for storing the number of pulses signal oscillating in a cycle of the synchronous oscillator power?
  • the synchronizing oscillation circuit of a pulse signal that oscillates in a circumferential phase of the loop oscillator signal A counter for counting the number of pulses, and counting the number of pulse signals oscillated in the cycle of the loop oscillation signal by the number stored in the storage means by the power counter.
  • the gate means for stopping the oscillation of the synchronous oscillation circuit, the loop oscillation signal propagating along the signal path and fed back, and the period of the loop oscillation signal
  • a pulse extracting means for extracting only the loop oscillation signal from the pulse train composed of the pulse signal oscillated in the step, and returning the counter to an initial state by the loop oscillation signal extracted by the pulse extracting means;
  • a control means for restarting the oscillation of the oscillation circuit.
  • a pulse generation device for delay time measurement used to carry out the delay time measurement method is provided, and the second object is achieved.
  • the signal path whose delay time is to be measured is substantially the same as the actual operation state, and the delay time of the signal path is measured in the same operation state as the actual operation state. . Therefore, a correct delay time substantially equal to the delay time in the actual operation state of the signal path can be obtained.
  • the pulse generator for measuring delay time of the present invention a relatively simple The signal path can be brought into the same state as the actual operation state by the circuit configuration. Therefore, the implementation of the delay time measuring method according to the present invention is facilitated.
  • FIG. 1 is a block diagram showing a circuit configuration of a delay time measuring pulse generator used for carrying out the delay time measuring method according to the present invention. .
  • FIG. 2 is a timing chart for explaining the operation of the delay time measuring pulse generator shown in FIG.
  • FIG. 3 is a block diagram showing a circuit configuration of a delay time measuring device used for implementing the conventional delay time measuring method.
  • Figure 4 is the best mode for carrying out the c invention is a timing Chiya one bets for explaining the operation of the delay time measuring device shown in FIG. 3
  • each signal path 10 has a signal path in which a plurality of logic elements are connected in cascade and a variable delay means inserted in this signal path.
  • each signal i 0 can be regarded as one of a plurality of signal paths for supplying a timing signal from a timing signal generator to a device under test in various measurement circuits, and in an IC test apparatus, It can be regarded as one of a plurality of signal paths for supplying a test signal of a predetermined pattern from the pattern generator to the IC under test.
  • a pulse generator 30 for delay time measurement is connected to the input terminal 14 of the signal path 10 and the signal path 10 has the same frequency as that of the signal propagating during actual operation. Supply a pulse with a frequency close to it.
  • the signal path 10 Since the output terminal 13 of the signal path 10 is connected to the delay time measuring pulse generator 30 by the connection path 21, the signal path 10 ⁇ the output terminal 13 ⁇ the connection path 2 1—delay A loop consisting of a pulse generator for delay time measurement 30 ⁇ an input terminal 14 of the signal path 10 is formed.
  • the pulse generator for delay time measurement 30 includes a start pulse generator 35 for generating a start pulse ST for loop oscillation, and a counter 41 for receiving a loop oscillation signal PLO fed back through the connection path 21. , and that the counter 4 1 and the control hand stage 4 2 for controlling is supplied to the connection path 2 1 loop oscillation signal PLO force s' non-inverting input is fed back through the output of the counter 4 1 is supplied to the inverting input Gate 31; storage means 38 for storing the number of interpolation pulses PI that can be entered within the loop oscillation cycle; output of AND gate 31 and output power s of start pulse generator 35 The value of the interpolation pulse PI stored in the storage means 38 is preset in the synchronous oscillating circuit 36, the counter 39 supplied with the output power of the synchronous oscillating circuit 36, and the power counter 39. And control means 40 for .
  • the synchronous oscillating circuit 36 includes an output of the AND gate 31, an output of the start pulse generator 35, an output of the synchronous oscillating circuit 36, an OR gate 32 supplied with a power of 5 ft, and an OR gate 32.
  • the pulse shaping circuit 33 and AND gate 34) constitute a loop oscillation circuit.
  • the frequency of the interpolation pulse PI is selected to be equal to or close to the frequency of the signal propagating through the signal path 10 in the actual operation state. Therefore, the frequency of the interpolation pulse P i may differ by the apparatus power?, Known Value.
  • the interpolation pulse PI When an interpolation pulse PI having a frequency equal to or close to the frequency of the signal transmitted on the signal path 10 in the actual operation state is inserted within the period of the loop oscillation signal PLO, the interpolation pulse PI becomes the loop oscillation signal PL.
  • the signal propagates along the signal path 10 together with 0. Therefore, the signal path 10 is in the same state as the actual state or a state close thereto.
  • the power consumed in the signal path 10 is substantially the same as the power consumed in the actual operation, so that the temperature fluctuation of the signal 10 is also substantially the same as in the actual operation.
  • the delay time of the signal path 10 can be measured in a temperature fluctuation state substantially the same as the temperature fluctuation of the signal path 10 in the actual operation state.
  • the synchronous oscillation circuit 36 includes a return path 37 for immediately returning the pulse obtained at the output of the AND gate 34 to the OR gate 32, an OR gate 32, a pulse shaping circuit 33, and an AND gate 34.
  • the short loop circuit including the feedback path 37 generates the interpolation pulse PI having a frequency equal to or close to the frequency of the signal propagating through the signal path 10 in the actual operation state.
  • the pulse shaping circuit 33 shapes the waveform of the input pulse into a pulse having a constant pulse width, and performs an operation of amplifying the peak value of the pulse to a predetermined value.
  • the loop oscillation operation power is maintained by this amplification operation.
  • the number of interpolation pulses PI inserted in the oscillation period ⁇ of the loop oscillation circuit including the signal path 10 is stored in the storage means 38 of the pulse generator 30 for measuring delay time.
  • the oscillation cycle of the loop oscillation circuit is a force obtained by measurement.This measured value may be an approximate value.c
  • the numerical value is stored in the storage means 38.
  • Set N This value N is first preset in the counter 39 by the start pulse ST under the control of the control means 40.
  • the counter 39 counts the interpolation pulse PI, which is the oscillation output of the synchronous oscillation circuit 36, and subtracts (1 1) from the preset value N by one each time the interpolation pulse PI is input.
  • the loop oscillation signal PLO fed back from the signal path 10 through the connection path 21 is input to the control means 40 through the AND gate 31 and stored in the storage means 38 under the control of the control means 40.
  • the value N is reset to counter 39 again. Since the output of the counter 39 is returned to the H (high level) logic by the presetting of the numerical value N, the AND gate 34 is in an open (on) state (enabled state).
  • the AND gate 31 cooperates with the counter 41 and the control means 42 to perform an operation of extracting only the loop oscillation signal P L0 from the pulse train fed back through the connection path 21. That is, an operation of extracting the first pulse from a pulse train consisting of one loop oscillation signal P LO and a train of interpolation pulses PI following it is performed.
  • the counter 41 presets the numerical value N stored in the storage means 38 under the control of the control means 42 at the timing of the start pulse ST and the loop oscillation signal PLO. You. When a numerical value N is preset in the counter 41 from the storage means 38, the counter 41 becomes H logic, so that one input of the AND gate 31 is supplied with L logic which is an inverted output thereof. . Therefore, the AND gate 31 is closed, and the passage of the pulse train following the loop oscillation signal P 0 is prevented.
  • the counter 41 decrements ( ⁇ 1) the preset value N by one each time the interpolation pulse PI fed back through the connection path 21 is input.
  • the output of the counter 41 falls to L logic, and the AND gate 31 is opened. Therefore, the loop oscillation signal PLO that has been fed back passes through the AND gate 31 and is input to the control means 40 and 42, so that the counters 39 and 41 are preset.
  • the AND gate 31 is returned to the closed state, and eventually the AND gate 31 passes only the loop oscillation signal PLO.
  • the output cycle of counter 39 or 41 (Fig. 2C) By measuring the delay time, the delay time of the signal path 10 can be measured.
  • the signal path 10 Since the loop oscillation signal PLO and the interpolation pulse PI force f propagate through this signal path 10, the signal path 10 has substantially the same state as in the actual operation, and therefore, the loop oscillation signal PL shown in FIG.
  • the cycle of 0 is substantially the same as the delay time of the signal path 10 in the actual operation. That is, the correct delay time of the signal path 10 can be measured.
  • the AND gate 34 is controlled by the counter 39 and the control means 40.
  • a counter 41 and a control means 42 are provided to provide the AND gate 31.
  • the counter 39 and the control means 40 may be shared without providing the counter 41 and the control means 42 separately.
  • a synchronous oscillator of another type or configuration may be used, in which the synchronous oscillation circuit 36 is a loop oscillation circuit.
  • the propagation delay time of the signal path is long. Since the delay time of the signal path is measured by inserting an interpolation pulse with a frequency equal to or close to the frequency of the propagating signal into the loop oscillation cycle, the signal path operates with almost the same power consumption as in the actual operation. And the temperature fluctuations are also substantially the same. As a result, even if the signal path is largely affected by temperature fluctuations, as in the case where the signal path is composed of CMOS-structured ICs, the signal path (IC chip) is at almost the same temperature state as in actual operation. Since the delay time is measured, the remarkable advantage that the correct delay time without error can be measured is obtained.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Measurement Of Unknown Time Intervals (AREA)

Abstract

La présente invention concerne un procédé de mesure précise du retard d'un parcours (10) de signal constitué par un circuit intégré de structure CMOS dans un état qui est le même que l'état de fonctionnement réel, ou proche de cet état. Un circuit oscillant en boucle comprenant le parcours (10) de signal est constitué et il est amené à un état d'oscillation en boucle par la fourniture d'une impulsion de démarrage (ST) au circuit. Une impulsion d'interpolation P1, dont la fréquence est la même, ou à peu près, que celle du signal par impulsions qui est propagé quand le parcours du signal est en état de fonctionnement effectif, est introduite, cette impulsion d'interpolation P1 et le signal PLO d'oscillation en boucle sont fournis au parcours de signal, et ce parcours est mis sensiblement dans le même état de température que celui de l'état de fonctionnement effectif. Le cycle du signal d'oscillation en boucle PLO est mesuré dans cet état afin de mesurer le retard du parcours de signal.
PCT/JP1997/000154 1996-01-25 1997-01-24 Procede de mesure d'un retard et generateur d'impulsions destine a mesurer le retard selon le procede WO1997027494A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE19780113T DE19780113T1 (de) 1996-01-25 1997-01-24 Verfahren zum Messen einer Verzögerungszeit und Impulserzeugungseinrichtung zum Messen einer Verzögerungszeit für den Einsatz bei der Implementierung dieses Verfahrens
GB9720222A GB2316493A (en) 1996-01-25 1997-01-24 Delay time measuring method and pulse generator for measuring delay time for use in said measuring method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP8010920A JPH09203772A (ja) 1996-01-25 1996-01-25 遅延時間測定方法及び遅延時間測定用パルス発生装置
JP8/10920 1996-01-25

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Publication Number Publication Date
WO1997027494A1 true WO1997027494A1 (fr) 1997-07-31

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PCT/JP1997/000154 WO1997027494A1 (fr) 1996-01-25 1997-01-24 Procede de mesure d'un retard et generateur d'impulsions destine a mesurer le retard selon le procede

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JP (1) JPH09203772A (fr)
KR (1) KR19980703081A (fr)
DE (1) DE19780113T1 (fr)
GB (1) GB2316493A (fr)
TW (1) TW320686B (fr)
WO (1) WO1997027494A1 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5787092A (en) * 1997-05-27 1998-07-28 Hewlett-Packard Co. Test chip circuit for on-chip timing characterization
DE10024476A1 (de) * 2000-05-18 2001-12-20 Infineon Technologies Ag Vorrichtung zum Testen einer elektrischen Schaltung
JP4846215B2 (ja) * 2004-08-27 2011-12-28 株式会社アドバンテスト パルス発生器、タイミング発生器、及びパルス幅調整方法
JP2006189336A (ja) * 2005-01-06 2006-07-20 Advantest Corp 半導体デバイス、試験装置、及び測定方法
KR100921815B1 (ko) * 2007-06-18 2009-10-16 주식회사 애트랩 지연시간 측정회로 및 지연시간 측정 방법
JP2009063567A (ja) * 2008-08-22 2009-03-26 Advantest Corp 半導体試験システム
JP2009031297A (ja) * 2008-08-22 2009-02-12 Advantest Corp 半導体試験システム

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0534412A (ja) * 1991-07-31 1993-02-09 Advantest Corp タイミング発生装置
JPH0534418A (ja) * 1991-07-31 1993-02-09 Oki Electric Ind Co Ltd テスト回路
JPH05281288A (ja) * 1992-03-31 1993-10-29 Oki Electric Ind Co Ltd テスト回路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0534412A (ja) * 1991-07-31 1993-02-09 Advantest Corp タイミング発生装置
JPH0534418A (ja) * 1991-07-31 1993-02-09 Oki Electric Ind Co Ltd テスト回路
JPH05281288A (ja) * 1992-03-31 1993-10-29 Oki Electric Ind Co Ltd テスト回路

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Publication number Publication date
KR19980703081A (ko) 1998-09-05
DE19780113T1 (de) 1998-02-26
GB9720222D0 (en) 1997-11-26
GB2316493A (en) 1998-02-25
TW320686B (fr) 1997-11-21
JPH09203772A (ja) 1997-08-05

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