GB2316493A

GB2316493A - Delay time measuring method and pulse generator for measuring delay time for use in said measuring method

Info

Publication number: GB2316493A
Application number: GB9720222A
Authority: GB
Inventors: Tadahiko Baba
Original assignee: Advantest Corp
Current assignee: Advantest Corp
Priority date: 1996-01-25
Filing date: 1997-01-24
Publication date: 1998-02-25
Also published as: JPH09203772A; DE19780113T1; WO1997027494A1; KR19980703081A; GB9720222D0; TW320686B

Abstract

A method for accurately measuring the delay time of a signal path (10) constituted by an IC of a CMOS structure in a state which is the same as, or approximate to, the actual operation state. A loop oscillation circuit including the signal path (10) is constittuted, and is brought into a loop oscillation state by feeding a start pulse ST to the circuit. An interpolation pulse P 1 having a frequency which is the same as, or approximate to, the frequency of the pulse signal propagated with the signal path is in an actual operation state, is inserted, this interpolation pulse P 1 and the loop oscillation signal P LO are fed to the signal path, and the signal path is brought into the substantially same temperature state as that of the actual operation state. The cycle of the loop oscillation signal P LO is measured under this state so as to measure the delay time of the signal path.

Description

METHOD OF MEASURING A DELAY TIME AND PULSE GENERATING APPARATUS FOR MEASURING A DELAY TIME FOR USE IN IMPLEMENTING THIS METHOD TECHNICAL FIELD The present invention generally relates to a method of measuring a delay time which is suitable for application to an apparatus having a plurality of signal paths (channels) in measuring a delay time of a signal propagating through each of the signal paths. More particularly, the present invention relates to a delay time measuring method which is capable of measuring a delay time of each of signal paths by placing each signal path in substantially the same state as or in the state close to a real state of operation thereof and to a pulse generating apparatus for measurement of delay time which is used in implementing this measuring method.

BACKGROUND ART In a semiconductor integrated circuit testing apparatus (generally called IC tester) for testing various kinds of semiconductor integrated circuits (hereinafter referred to as ICs), for example, a test signal of a predetermined pattern is applied to each of input terminals of an IC to be tested (IC under test), and the output signals of the IC under test responding to the test signals are compared with an expected value signal to generate a failure signal each time each of the output signals does not coincide with the expected value signal, followed by determining whether the IC under test is conforming (defective) or not on the basis of the generated failure signals. Therefore, there are provided in an IC testing apparatus a plurality of test signal supply paths or channels, namely, signal paths the number of which is equal to or greater than the number of input terminals of an IC under test. An IC testing apparatus is arranged such that a plurality of ICs to be tested such as 16, 32 or 64 ICs can be tested at the same time, and hence many ICs can be tested in a short time period. Accordingly, several hundred channels of signal paths are practically provided in an IC testing apparatus.

The phase of a test signal of a predetermined pattern applied to each input terminal of an IC under test must be controlled to an intended phase in accordance with a testing purpose. For this end, each delay time given to each test signal by a corresponding signal path through which the test signal propagates must be given as a known value. Further, it is desirably requested that the delay times of the signal paths for all test signals are uniform (the same) with each other. Therefore, in the art of IC testing apparatus, it has been performed heretofore that the delay time of each test signal supply path is periodically measured, and also an adjusting operation for eliminating unevenness of the measured delay times to make all of uniform delay time based on the measurement results has been effected.

In addition to an IC testing apparatus, in an electronic apparatus or an integrated circuit device having a plurality of signal paths wherein a signal (pulse) such as, for example, a clock signal is supplied to a circuit or an element (part) of the subsequent stage via each of the plurality of signal paths, or in a testing apparatus having a plurality of signal paths for testing an electronic part or element other than IC or in various kinds of measuring apparatus each having a plurality of signal paths, it is also necessary that an adjusting operation for measuring each delay time given to each signal by a corresponding signal path through which the signal propagates and for eliminating unevenness of the measured delay times to make all of uniform delay time based on the measurement results is performed, and an operation for adjusting each delay time so that each signal can be supplied with a predetermined phase to a circuit or an element of the subsequent stage is effected.

Such adjusting operation for eliminating unevenness of the delay times of the signal paths to make all of uniform delay time or the operation for adjusting each delay time so that each signal can be supplied with a predetermined phase is commonly called "skew adjustment".

An example of a prior art delay time measuring method will be explained with reference to Fig. 3. Fig. 3 shows a circuit configuration in which a delay time measuring apparatus 20 used to implement this delay time measuring method is connected to single one signal path 10. In general, one signal path 10 comprises a signal line 11 constituted by a plurality of logical elements connected in cascade, and variable delay means 12 inserted into this signal line 11. Further, the variable delay means 12 is provided to adjust the delay time of the signal path 10.

This signal path 10 can be considered, in various kinds of measuring apparatus, as one of a plurality of signal paths through each of which, for instance, a clock signal (timing signal) is supplied to a device to be measured from a timing signal generating part. Alternatively, this signal path 10 can be considered, in an IC testing apparatus, as one of a plurality of signal paths through each of which a test signal of a predetermined pattern is supplied to an IC under test from a pattern generator.

In order to measure the delay time of the signal path 10, the delay time measuring apparatus 20 is connected to an input end 14 of the signal path 10. An output end 13 of the signal path 10 is connected to the delay time measuring apparatus 20 by a connection line 21 whereby a loop of the signal path 10 - its output end 13 - the connection line 21 - the delay time measuring apparatus 20 - the input end 14 of the signal path 10 is formed. The delay time measuring apparatus 20 comprises a start pulse generator 22 for supplying a start pulse ST for loop oscillation to the signal path 10, and a counter 23 for measuring the period of a pulse circulating or propagating through the loop.

Next, the delay time measuring method will be explained.

When one start pulse ST from the start pulse generator 22 is inputted to the input end 14 of the signal path 10, this start pulse ST is outputted to the output end 13 after t seconds of delay time caused by the signal path 10. If the delay time of the connection line 21 is small enough compared with the delay time of the signal path 10 and can be neglected, the pulse propagated over the signal path 10 is fed back to the input end 14 after T seconds. The fed back pulse is outputted again to the output end 13 of the signal path 10 after t seconds and is fed back again to the input end 14. By repeating this operation, the loop circuit including the signal path 10 gets into, as shown in Fig. 4, a loop oscillation state in which the period is the delay time T of the signal path 10. The counter 23 measures the period of the loop oscillation signal PLO and obtains the delay time T of the signal path 10.

In the above prior art delay time measuring method, if the delay time T of the signal path 10 is short and if the frequency of the loop oscillation signal PLO is close to the frequency in the actual operation time of the signal path 10, the delay time which is considerably close to the delay time of the signal path in the actual operation time can be measured. However, since a small physical size and a low power consumption of an apparatus are required as a recent tendency, there is a tendency that an IC having MOS structure (MOS-IC), particularly an IC having CMOS (complementary MOS) structure is used in many cases in the circuits of various measuring apparatus and testing apparatus etc. Since an IC having CMOS structure consumes considerably low power and can provide a high integration degree, there is an advantage that the circuit can be made physically small. Therefore, a CMOS IC is advantageous in this point.

However, in a signal path and/or a circuit formed in an IC having CMOS structure, the propagation delay time of a signal is relatively long. Therefore, in case that the signal path 10 as mentioned above is formed in an IC having CMOS structure, when the above prior art delay time measuring method is applied to cause a loop oscillation on a loop circuit including this signal path 10 in order to measure the delay time t, the loop oscillation frequency becomes relatively low frequency.

As an example, in an IC testing apparatus, if a circuit which generates a waveform of a test signal having a predetermined pattern through a circuit which supplies the test signal to a terminal of an IC under test are formed in an IC having CMOS structure, the delay time becomes approximately 100 ns. If the delay time is 100 ns, the loop oscillation frequency is 1/(100 ns)=10 MHz.

On the other hand, in an IC testing apparatus, the frequency of a test signal is set to a high frequency of approximately 100 MHz. Therefore, there is a big difference between the loop oscillation frequency and the frequency in the actual operation time.

In each of various measuring apparatus and electronic apparatus, in case that, for example, a high frequency timing (clock) signal is used, if a signal path to which this timing signal is supplied is formed in an IC having CMOS structure, there is, similarly to the above case of an IC testing apparatus, a big difference between the loop oscillation frequency and the frequency in actual operating time.

As another drawback of an IC having CMOS structure, the fact that the power consumption varies in accordance with the operation rate can be cited since an IC having CMOS structure has a characteristic that power is consumed only when the state of an active element is inverted. For example, if, for the signal path 10 which operates at 100 MHz in the actual operating time, a loop oscillation is performed at 1/10 frequency, i.e., 10 MHz and the delay time is measured, the internal temperature of the IC is different from that in the actual operating time since the power consumption of the IC is different between 100 MHz operation time and 10 MHz operation time. In this case, there is a disadvantage that correct delay time in actual operation time cannot be measured since the delay time T of an IC having CMOS structure varies in accordance with the internal temperature of the IC.

DISCLOSURE OF THE INVENTION It is a first object of the present invention to provide a method of measuring a delay time which is capable of measuring substantially the same delay time as that of a signal path in the real state of operation.

It is a second object of the present invention to provide a pulse generating apparatus for measurement of delay time which is used in implementing the above delay time measuring method according to the present invention.

According to the present invention, there is provided a method of measuring the delay time of a signal path which is included in a loop oscillation circuit, the delay time of said signal path being measured by measuring the period of an oscillation signal of said loop oscillation circuit, said method comprising the steps of: inserting a signal having a frequency equal to or close to a frequency of a signal propagating through said signal path when it is energized in the real operating state within the period of an oscillation signal of said loop oscillation circuit; causing said oscillation signal and said signal inserted within the period of said oscillation signal to propagate through said signal path, thereby to energize said signal path in substantially the same state as the real operating state thereof; taking out the oscillation signal of said loop oscillation circuit to measure the period thereof; and regarding the measured period as the delay time of said signal path, and the first object of the invention is attained thereby.

In a preferred embodiment, the signal path is constituted by an IC having CMOS structure, and within the period of the loop oscillation signal is inserted an interpolation pulse having a frequency substantially equal to that of a pulse signal propagating through the signal path when it is energized in the real operating state.

In addition, the number of the interpolation pulse to be inserted within the period of the loop oscillation signal is previously set in storage means, and when counting means counts one more pulse in addition to the set number of the pulse signals, it outputs an output signal, and the delay time of the signal path is measured by means of the period of the output signal from the counting means.

Further, according to the present invention, there is provided a pulse generating apparatus for measurement of delay time which is used in implementing the delay time measuring method, comprising: a start pulse generator for generating a start pulse for starting a loop oscillation of a loop oscillation circuit including a signal path whose delay time is to be measured; a synchronous oscillation circuit oscillating in synchronism with a loop oscillation signal of said loop oscillation circuit and oscillating, within the period of said loop oscillation signal, a pulse signal having a frequency equal to or close to a frequency of a pulse signal propagating through said signal path when it is energized in the real operating state; storage means for storing therein the number of the pulse signals oscillated by said synchronous oscillation circuit within the period of said loop oscillation signal; a counter for counting the number of pulse signals oscillated by said synchronous oscillation circuit within the period of said loop oscillation signal; gate means for stopping the oscillation of said synchronous oscillation circuit when said counter counts one more pulse signal after having counted the number of pulse signals oscillated within the period of said loop oscillation signal until the number stored in said storage means; pulse take-out means for taking out only the loop oscillation signal from a pulse series comprising the loop oscillation signal propagating through said signal path to return back and the pulse signals oscillated within the period of the loop oscillation signal; and control means for resetting said counter to the initial state by means of the loop oscillation signal taken out by said pulse take-out means, thereby to restart the oscillation of said synchronous oscillation circuit, and the second object of the invention is attained thereby.

In accordance with the aforementioned delay time measuring method of the present invention, the signal path whose delay time is to be measured becomes substantially the same state as the real operating state thereof, and the delay time of the signal path is measured in the same state as the real operating state thereof. Therefore, the accurate delay time which is substantially the same as the delay time in the real operating state of the signal path can be obtained.

In addition, in accordance with the pulse generating apparatus for measurement of delay time according to the present invention, it is possible to place the signal path in the same state as the real operating state thereof by a relatively simple circuit configuration. Therefore, the implementation of the delay time measuring method of the present invention can be made easy.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a circuit configuration of the pulse generating apparatus for measurement of delay time used in implementing the delay time measuring method according to the present invention; Fig. 2 is a timing chart for explaining the operation of the pulse generating apparatus for measurement of delay time shown in Fig. 1; Fig. 3 is a block diagram showing a circuit configuration of the delay time measuring apparatus used in implementing a prior art delay time measuring method; and Fig. 4 is a timing chart for explaining the operation of the delay time measuring apparatus shown in Fig. 3.

BEST MODES FOR CARRYING OUT THE INVENTION Now the embodiments of the present invention will be described in detail with reference to Figs. 1 and 2.

Fig. 1 shows a circuit configuration in which a pulse generating apparatus 30 for measurement of delay time used in implementing the delay time measuring method according to the present invention is connected to single one signal path 10.

Like the signal path 10 shown in Fig. 3, in this embodiment one signal path 10 comprises a signal line in which a plurality of logical elements are connected in cascade, and variable delay means inserted into this signal line. In addition, this signal path 10 can be considered, in various kinds of measuring apparatus, as one of a plurality of signal paths through each of which, for instance, a timing signal is supplied to a device to be measured from a timing signal generating part. Alternatively, this signal path 10 can be considered, in an IC testing apparatus, as one of a plurality of signal paths through each of which a test signal of a predetermined pattern is supplied to an IC under test from a pattern generator.

In order to carry out the delay time measuring method according to the present invention, a pulse generating apparatus 30 for measurement of delay time is connected to an input end 14 of the signal path 10 and a pulse having the same frequency as or a frequency close to that of a signal propagating through the signal path 10 in real operating state is supplied to the signal path 10.

Since an output end 13 of the signal path 10 is connected to the pulse generating apparatus 30 for measurement of delay time by a connection line 21, a loop of the signal path 10 its output end 13 - the connection line 21 - the pulse generating apparatus 30 for measurement of delay time - the input end 14 of the signal path 10 is formed.

The pulse generating apparatus 30 for measurement of delay time comprises a start pulse generator 35 for generating a start pulse ST for loop oscillation, a counter 41 to which a loop oscillation signal PLO fed back via the connection line 21 is inputted, control means 42 for controlling the counter 41, an AND gate 31 to the noninverting input of which the loop oscillation signal PLO fed back via the connection line 21 is supplied and to the inverting input of which an output of the counter 41 is supplied, storage means 38 for storing therein the number of interpolation pulses PI which can be inserted within the period of the loop oscillation, a synchronous oscillation circuit 36 to which an output of the AND gate 31 and an output of the start pulse generator 35 are supplied, a counter 39 to which an output of the synchronous oscillation circuit 36 is supplied, and control means 40 for presetting in the counter 39 the number (numerical value) of interpolation pulses PI stored in the storage means 38.

The synchronous oscillation circuit 36 comprises an OR gate 32 to which an output of the AND gate 31, an output of the start pulse generator 35 and an output of the synchronous oscillation circuit 36 are supplied, a pulse shaping circuit 33 for shaping the waveform of the output of this OR gate 32, and an AND gate 34 to which an output of this pulse shaping circuit 33 and an output of the counter 39 are inputted. An output of the AND gate 34 is supplied to the input end 14 of the signal path 10. Therefore, since the AND gate 31 and the synchronous oscillation circuit 36 compose a part of the feedback loop, the signal path 10, the connection line 21, the AND gate 31 and the synchronous oscillation circuit 36 (the OR gate 32, the pulse shaping circuit 33 and the AND gate 34) compose a loop oscillation circuit.

In such a way, when a start pulse ST is supplied to the synchronous oscillation circuit 36 from the start pulse generator 35, a loop oscillation is started. Then, as shown in Fig. 2A, the loop oscillation circuit gets into a loop oscillation state in which the loop oscillation signal PLO runs along the aforementioned loop with a period determined by the delay time n of the signal path 10.

In the delay time measuring method according to the present invention, as shown in Fig. 2B, interpolation pulses PI are inserted into the period X of the loop oscillation signal (therefore, between two adjacent loop oscillation signals PLO)- The frequency of the interpolation pulses PI is selected to be equal to or close to a frequency of a signal propagating over the signal path 10 which is in the actual operating state. Therefore, the frequency of the interpolation pulses PI may be different depending on the apparatus but is a known value.

When the interpolation pulses PI having a frequency equal to or close to a frequency of a signal propagating over the signal path 10 which is in the actual operating state are inserted into the period T of the loop oscillating signal PLOT the interpolation pulses PI propagate over the signal path 10 together with the loop oscillation signal PLO- Therefore, the signal path 10 is placed in the state same as or close to the actual operating state. As a result, since the power consumed in the signal path 10 is substantially same as the power consumed therein during the actual operating time, the temperature variation of the signal path 10 is also substantially same as the temperature variation thereof during the actual operating time. Therefore, according to the delay time measuring method of the present invention, the delay time of the signal path 10 can be measured in the temperature variation state substantially same as the temperature variation state of the signal path 10 which is in the actual operating state. Consequently, even if the signal path 10 is formed in an IC having CMOS structure, the correct delay time which is substantially same as the delay time of the signal path 10 in the actual operating time can be measured.

The aforementioned synchronous oscillation circuit 36 shows a case in which a synchronous oscillation circuit is made up of a loop comprising a feedback path 37 for immediately feeding the pulses obtained at the output of the AND gate 34 back to the OR gate 32, an OR gate 32, a pulse shaping circuit 33 and an AND gate 34. Therefore, the interpolation pulses PI having a frequency equal to or close to a frequency of a signal propagating over the signal path 10 which is in the actual operating state are generated by a short loop circuit including the feedback path 37. Further, the pulse shaping circuit 33 shapes the waveform of an inputted pulse to make a pulse having a constant pulse width and amplifies the pulse so that the peak value of the pulse becomes a predetermined value. The loop oscillation operation is maintained by this amplification operation.

The number of the interpolation pulses PI to be inserted into the oscillation period t of the loop oscillation circuit including the signal path 10 is stored in the storage means 38 of the pulse generating apparatus 30 for measurement of delay time. Although the oscillation period T of the loop oscillation circuit is obtained by a measurement, this measured value may an approximate value. Assuming that the number of the interpolation pulses PI to be inserted into the oscillation period t is N, the value N is set in the storage means 38. This value N is preset first in the counter 39 by the start pulse ST under control of the control means 40.

The counter 39 counts the interpolation pulses PI which are the oscillation output of the synchronous oscillation circuit 36. Every time an interpolation pulse PI is inputted to the counter 39, the counter value is subtracted by one (-1) starting from the preset value N. When, after the value of the counter 39 reaches zero from the preset value N, i.e., the counted number of interpolation pulses PI accords with the value N set in the storage means 38, one more next pulse is counted, the output of the counter 39 falls down to L (low level) logic. As a result, since the AND gate 34 gets into closed (off) state, the oscillation operation of the synchronous oscillation circuit 36 is temporally stopped.

The loop oscillation signal PLO fed back from the signal path 10 via the connection line 21 is inputted to the control means 40 via the AND gate 31 and the value N stored in the storage means 38 is preset again in the counter 39 under the control of the control means 40. Since the output of the counter 39 is restored to H (high level) logic by this presetting operation of the value N, the AND gate 34 gets into open (on) state (enabling state) and passes therethrough the loop oscillation signal PLO. As a result, the oscillation operation of the synchronous oscillation circuit 36 is resumed.

The AND gate 31 cooperates with the counter 41 and the control means 42 to take out only the loop oscillation signal PLO from the pulse series fed back via the connection line 21. That is, the AND gate 31 takes out the first pulse from the pulse series comprising one loop oscillation signal PLO and a subsequent series of interpolation pulses PI. The value N stored in the storage means 38 is preset in the counter 41 similarly to the counter 39 at the timing of the start pulse ST and the loop oscillation signal PLO under the control of the control means 42. When the value N is preset in the counter 41 from the storage means 38, the output of the counter 41 becomes H logic. Consequently, an L logic which is an inverted output of the counter 41 is supplied to one input of the AND gate 31. Hence, the AND gate 31 gets into closed state and inhibits the pulse series following the loop oscillation signal PLO from passing therethrough. Every time an interpolation pulse PI fed back via the connection line 21 is inputted to the counter 41, the counter value is subtracted by one (-1) starting from the preset value N.

When, after the value of the counter 41 reaches zero from the preset value N, one more next interpolation pulse PI is counted, the output of the counter 41 falls down to L logic.

As a result, the AND gate 31 gets into open state.

Therefore, since the fed back loop oscillation signal PLO passes through the AND gate 31 and is inputted to the control means 40 and 42, the counters 39 and 41 are preset. The AND gate 31 is returned to closed state by this preset operation.

As a result, the AND gate 31 passes therethrough only the loop oscillation signal PLO. In such a way, the delay time of the signal path 10 can be measured by measuring the period t (Fig. 2C) of the output of the counter 39 or 41. Since the loop oscillation signal PLO and the interpolation pulses PI propagate over the signal path 10, the signal path 10 is in substantially same state as the actual operating state.

Therefore, the period T of the loop oscillation signal PLO shown in Fig. 2C is substantially same as the delay time of the signal path 10 which is in the actual operation time.

That is, the correct delay time of the signal path 10 can be measured.

Further, in the aforementioned pulse generating apparatus for measurement of delay time, the AND gate 34 is controlled by the counter 39 and the control means 40, and separately from this, the counter 41 and the control means 42 are provided to control the AND gate 31. However, the counter 39 and the control means 40 may be commonly used without separately providing the counter 41 and the control means 42.

In addition, the synchronous oscillation circuit 36 is used as the loop oscillation circuit. However, it is needless to say that other type or other configuration of synchronous oscillator may be used.

As described above, according to the present invention, even if the propagation delay time of a signal path is long, and hence the oscillation frequency of a loop oscillation circuit including this signal path is low, an interpolation pulse having a frequency equal to or close to a frequency of a signal propagating through the signal path which is energized in the real operation state is inserted within the period of the loop oscillation to measure the delay time of the signal path. As a result, the signal path operates with substantially the same power consumption as that in the real operating state thereof, and the temperature variation also becomes substantially the same as that in the real operating state thereof. Consequently, even if a signal path whose delay time is significantly affected by a temperature variation as in a case that the signal path is constituted by an IC having CMOS structure, the delay time of the signal path (IC chip) which is in substantially the same temperature condition as that in the real operating state thereof can be measured. Therefore, there is obtained a remarkable advantage that the accurate delay time can be measured without any error.

Claims

WHAT IS CLAIMED IS:

1. A method of measuring the delay time of a signal path which is included in a loop oscillation circuit, the delay time of said signal path being measured by measuring the period of an oscillation signal of said loop oscillation circuit, said method comprising the steps of: inserting a signal having a frequency equal to or close to a frequency of a signal propagating through said signal path when it is energized in the real operating state within the period of an oscillation signal of said loop oscillation circuit; causing said oscillation signal and said signal inserted within the period of said oscillation signal to propagate through said signal path, thereby to energize said signal path in substantially the same state as the real operating state thereof; taking out the oscillation signal of said loop oscillation circuit to measure the period thereof; and regarding the measured period as the delay time of said signal path.

2. The method according to claim 1, wherein said signal path is constituted by an IC having CMOS structure.

3. The method according to claim 1, wherein said signal inserted within the period of the oscillation signal is a pulse signal, and wherein the number of said pulse signal to be inserted is previously set in storage means, and the period of a signal outputted from counting means when it counts one more pulse in addition to the set number of the pulse signals is measured, thereby regarding the measured period of the signal as the delay time of said signal path.

4. The method according to claim 1, wherein said signal path is one of a plurality of signal paths through each of which a timing signal from a timing generating part is supplied to a device to be measured in various kinds of measuring apparatus.

5. The method according to claim 1, wherein said signal path is one of a plurality of signal paths through each of which a test signal of a predetermined pattern from a pattern generator is supplied to an IC to be tested in an IC testing apparatus.

6. A pulse generating apparatus for measurement of delay time which is used in implementing any one of the delay time measuring methods recited in claims 1 to 5, said pulse generating apparatus comprising: a start pulse generator for generating a start pulse for starting a loop oscillation of a loop oscillation circuit including a signal path whose delay time is to be measured; a synchronous oscillation circuit oscillating in synchronism with a loop oscillation signal of said loop oscillation circuit and oscillating, within the period of said loop oscillation signal, a pulse signal having a frequency equal to or close to a frequency of a pulse signal propagating through said signal path when it is energized in the real operating state; storage means for storing therein the number of the pulse signals oscillated by said synchronous oscillation circuit within the period of said loop oscillation signal; a counter for counting the number of pulse signals oscillated by said synchronous oscillation circuit within the period of said loop oscillation signal; gate means for stopping the oscillation of said synchronous oscillation circuit when said counter counts one more pulse signal after having counted the number of pulse signals oscillated within the period of said loop oscillation signal until the number stored in said storage means; pulse take-out means for taking out only the loop oscillation signal from a pulse series comprising the loop oscillation signal propagating through said signal path to return back and the pulse signals oscillated within the period of the loop oscillation signal; and control means for resetting said counter to the initial state by means of the loop oscillation signal taken out by said pulse take-out means, thereby to restart the oscillation of said synchronous oscillation circuit.