JPH09203772A - Delay time measuring method, and pulse generating device for measuring delay time - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately measure the delay time of a circuit which uses IC of COMS structure under a temp. condition near the actual service condition. SOLUTION: The input terminal 14 and output terminal 13 of a circuit to be measured 10 formed from IC of COMS structure are connected together to constitute a loop oscillation circuit, which is given pulses to generate a loop oscillating condition, and the loop oscillating period is measured to determine the delay time of the circuit to be measured. The circuit to be measured 10 is given interpolating pulses having the same frequency as the frequency to be handled at actual service of the circuit in the loop oscillation period, and the circuit is operated under a temp. condition near the actual service condition, and thereupon the delay time is measured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is suitable for use in measuring the delay time of each signal path of a device having a large number of signal paths such as an IC test apparatus, and a suitable delay time measuring method and delay time. The present invention relates to a measuring pulse generator.

[0002]

2. Description of the Related Art For example, in an IC tester, a test pattern signal is applied to each input terminal of an IC under test, its response output is compared with an expected value pattern, and the occurrence of a mismatch is detected to detect a defect in the IC under test. Then, the quality of the IC under test is judged. Therefore, at least the IC under test must be installed in the IC tester.
There are provided test pattern signal supply paths equal in number to the input terminals. 16 to 32 IC tests at the same time
The number of ICs is about 64, and a large number of ICs can be tested in a short time. Therefore, the IC test apparatus is provided with a signal path of several hundred channels.

By the way, the phase of the test pattern signal applied to each input terminal of the IC under test needs to be aligned with the intended phase according to the purpose of the test. Therefore, the delay time of the signal path of each test pattern signal must be given as a known value. Furthermore, it is desirable that all the test pattern signal paths have the same delay time. For this reason, conventionally, in the field of IC test equipment, the delay time of the test pattern signal supply system path has been regularly measured, and adjustment work for aligning the delay time of each test pattern signal is also performed. ing. This adjustment work is generally called skew adjustment.

A conventional delay time measuring method will be described with reference to FIG. In the figure, reference numeral 10 indicates a circuit under measurement whose delay time is to be measured. Originally, the circuit under test 10 can be regarded as one of the test pattern signal supply paths provided in, for example, an IC test apparatus. The circuit under test 10 has its signal path 11
The variable delay means 12 is provided in the
Is configured so that the delay time of the circuit under test 10 can be adjusted.

Reference numeral 20 denotes a delay time measuring device. The delay time measuring device 20 includes an output terminal 13 of the circuit under test 10,
Loop connecting means 21 for connecting between the input terminal 14 and
A start pulse generator 22 for applying a pulse to this loop connection means 21 to cause the circuit under test 10 to oscillate in a loop,
It is configured by a counter 23 that measures the period of a pulse that circulates in the loop connection means 21.

When one start pulse ST is input from the start pulse generator 22 to the input terminal 14 of the circuit under test 10, the start pulse ST is output to the output terminal 13 after the delay time τ seconds of the circuit under test 10. If the delay time of the loop connection means 21 is sufficiently smaller than the delay time of the circuit under test 10 and is ignored, the output pulse of the circuit under test 10 is fed back to the input terminal 14 after τ seconds. The fed-back pulse is output again to the output terminal 13 after τ seconds and is fed back to the input terminal 14. By repeating this, the circuit under test 10 enters a loop oscillation state having its own delay time τ as a cycle, as shown in FIG. The counter 23 measures the period of the loop oscillation signal P _LO and obtains the delay time τ of the circuit under test 10.

[0007]

There is no problem if the delay time τ of the circuit under test 10 is short and the frequency of the loop oscillation signal P _LO is close to the operating frequency of the circuit under test 10 in actual operation. However, as a recent trend is that downsizing and low power consumption are required, the circuit of the IC test apparatus is commercialized.
There is a tendency to frequently use OS type ICs. The CMOS type IC is convenient in this respect since it consumes less power and can be miniaturized.

However, since the CMOS circuit has a relatively long signal delay time, the circuit under test (the test pattern generation circuit of the IC test apparatus and its transmission path) is a CMOS circuit.
In the case of a type IC, when the circuit under test 10 is oscillated in a loop in order to measure the delay time τ, the loop oscillation frequency becomes a relatively low frequency. By the way,
When the circuit from the generation of the waveform of the test pattern signal of the IC test apparatus to the supply of the test pattern signal to the terminal of the IC under test is composed of an IC of CMOS structure, the delay time is about 100 ns. When delay time is 100ns, loop oscillation frequency is 1 / 100ns = 10MHz
Becomes

On the other hand, in the IC test apparatus, the frequency of the test pattern signal is set to a high frequency of about 100 MHz in order to shorten the test time. For this reason, a large difference occurs between the frequency of loop oscillation and the frequency of actual operation. Another drawback of the CMOS type IC is that it consumes power only when the state of the active element is inverted, so that the power consumption changes according to the operating speed. As a result, the frequency of the measured circuit 10 operating at, for example, 100 MHz in actual operation is reduced to 1/10 of that of 10 MHz.
If the delay time is measured in the state of loop oscillation, the temperature inside the IC will be different from that during actual operation. As a result, the delay time .tau. Of the CMOS type IC changes depending on the temperature inside the IC, which causes a problem that the correct delay time cannot be measured.

An object of the present invention is to increase the delay time of a circuit, such as a CMOS type IC, which causes a loop oscillation at a lower frequency different from the actual operating frequency when the loop oscillation is performed. An object of the present invention is to provide a delay time measuring method and a delay time measuring pulse generator capable of measuring the delay time while being driven at a frequency close to the state.

[0011]

According to the present invention, a loop oscillation circuit is constructed by connecting an output terminal and an input terminal of a circuit to be measured whose delay time is to be measured, and an oscillation cycle of the loop oscillation circuit is set. In the delay time measurement method for measuring and measuring the delay time of the circuit under test, an interpolation pulse insertion that inserts an interpolation pulse of a frequency close to the frequency of the signal passing during actual operation of the circuit under test in the oscillation cycle of the loop oscillation circuit Means and
The interpolating pulse inserted by the interpolating pulse inserting means is distinguished from the loop oscillation signal, and means for measuring the cycle of the loop oscillation signal is provided. We propose a delay time measurement method to measure time.

Further, according to the present invention, the interpolation pulse inserting means may be inserted in the synchronous oscillation circuit that oscillates in synchronization with the loop oscillation of the loop oscillation circuit formed by the circuit to be measured and in the loop oscillation cycle of the synchronous oscillation circuit. A storage unit that stores the number of pulses that can be generated, a counter that counts the number of pulses that are inserted from the oscillation circuit into the loop oscillation circuit, and an interpolation pulse when the count value of this counter reaches the number stored in the storage unit. It is composed of a gate means for temporarily stopping the supply, detects the loop oscillation signal that arrives immediately after the number of pulses stored in the storage means is inserted into the loop oscillation circuit, and measures the loop oscillation cycle, and also performs interpolation. A delay time measuring pulse generator is configured by providing a loop oscillation signal extracting means for canceling the supply stop state of the pulse.

According to the delay time measuring method of the present invention, the frequency of the signal to be measured is close to the frequency of the signal passing through the circuit to be measured during the operation between the oscillation signals of the loop oscillation circuit formed by the circuit to be measured. Since the interpolating pulse of the frequency is inserted to measure the oscillation frequency of the loop, the delay time of the circuit under measurement is measured in a state close to that at the time of actual operation. Therefore, it is possible to obtain the delay time in a state close to the actual operation.

According to the delay time measuring pulse generator of the present invention, the delay time measuring pulse generator can be constructed with a relatively simple structure. Therefore, the delay time can be measured at low cost and with high accuracy.

[0015]

FIG. 1 shows an embodiment of the present invention.
Reference numeral 10 shown in FIG. 1 indicates a circuit to be measured as in FIG.
The delay time measuring pulse generator 30 proposed in the present invention is connected between the output terminal 13 and the input terminal 14 of the circuit under test 10 via the loop connecting means 21. Therefore, the delay time measuring method proposed in claim 1 of the present invention will also be described by explaining the configuration and operation of the delay time measuring pulse generator 30.

The delay time measuring pulse generator 30 has a loop oscillation signal P fed back through the loop connecting means 21.
_The gate means 31 and 32 for passing _LO , the pulse shaping circuit 33, and the gate means 34 for temporarily stopping the operation of giving the interpolation pulse to the circuit under test 10 are provided, and these gate means 31, 32 and the pulse shaping circuit 33 are provided. The gate circuit 34 constitutes a part of the feedback loop, and the start pulse is supplied from the start pulse generator 35, so that the circuit under test 10 has the circuit in the loop connection means 21 and the delay time measuring pulse generator 30. A loop oscillation circuit is formed through the loop oscillation signal P at a cycle determined by the delay time τ of the circuit under test 10 as shown in FIG. 2A.
_LO starts loop oscillation in which the circuit circulates at a cycle of delay time τ of the circuit under test 10.

In the present invention, the interpolation pulse P _I is inserted during the period τ of the loop oscillation signal P _LO . The frequency of the interpolation pulse P _I is matched with the frequency of the signal in the actual operation handled by the circuit under test 10 or is selected as a frequency close to it. Reference numeral 36 denotes a synchronous oscillator that generates this interpolation pulse. In this embodiment, the pulse obtained at the output of the gate means 34 is immediately returned to the gate means 32, the feedback path 37, the gate means 32, and the pulse shaping circuit 3
The case where the synchronous oscillation circuit 36 is configured by a loop configured by 3 and the gate means 34 is shown. Therefore,
The short loop constituted by the feedback path 37 oscillates the interpolation pulse P _I having a frequency close to the frequency handled by the circuit under test 10 in actual operation. The frequency of the interpolation pulse P _I is assumed to be known in advance. The pulse shaping circuit 33 shapes the waveform of the input pulse into a pulse having a constant pulse width and amplifies the peak value of the pulse to a predetermined value. This amplification operation maintains the loop oscillation operation.

In the delay time measuring pulse generator 30 according to the present invention, it is possible to measure an approximate value of the oscillation period τ of the loop oscillation circuit including the circuit to be measured 10 and insert it into the oscillation period τ. Storage means 38 is provided for storing the number of interpolation pulses P _I. By setting a numerical value N in this storage means 38, this numerical value N is initially set to the start pulse S.
The counter 39 is preset by T. Reference numeral 40 denotes a control means for presetting the set value N in the counter 39. The counter 39 counts the number of interpolation pulses P _I which are the oscillation output of the synchronous oscillation circuit 36, subtracts −1 from the preset value N, and the counted value becomes 0, which coincides with the numerical value N set in the storage means 38. , When the next one pulse is counted, the output of the counter 39 falls to L logic, and the gate means 34
Is controlled to a closed state, and the oscillation operation of the synchronous oscillation circuit 36 is temporarily stopped.

The loop oscillation signal P _LO is the loop connection means 21.
Be returned through. This loop oscillation signal P _LO is input to the controller 40 through the gate means 31, and the controller 40 resets the numerical value N stored in the storage means 38 to the counter 39 again. By this preset, the output of the counter 39 is returned to the H logic, the gate means 34 is controlled to the open state, the loop oscillation signal P _LO is passed, and the oscillation operation of the synchronous oscillation circuit 36 is restarted.

The gate means 31 performs an operation of extracting only the first pulse (loop oscillation signal P _LO ) at the head of the pulse train fed back through the loop connection means 21. For this purpose, a counter 41 and a controller 42 are provided. The counter 41 has a start pulse ST, like the counter 39.
The value N stored in the storage unit 38 is preset by being controlled by the control unit 42 at the timing of the loop oscillation signal P _LO . When the numerical value N is preset in the counter 41, the gate means 31 is controlled to the closed state, and the loop oscillation signal P _{LO is} generated.
The passage of the pulse train following is blocked. Along with this, the interpolation pulse P _I returned from the loop connection means 21 is counted,
When the count value is decremented by -1 and the count value returns to 0 and the next interpolation pulse P _I is counted, the output of the counter 41 falls to the L logic, so that the gate means 31 is opened. The loop oscillation signal P _LO arrives under the control of the open state, passes through the gate means 31, and presets the counters 39 and 41. With this preset, the gate means 31
Is returned to the closed state, and the gate means 31 eventually operates to extract only the loop oscillation signal P _LO . Therefore, the delay time of the circuit under test 10 can be measured by measuring the period τ (FIG. 2C) of the output of the counter 39 or 41.

In the above description, the counter 39 and the control means 4
Although the example in which the counter 41 and the control means 42 are provided separately from 0 has been described, the counter 39 and the controller 40 may be used as the counter 41 and the control means 42. Further, although the synchronous oscillation circuit 36 is also composed of a loop oscillation circuit, other types of synchronous oscillators can be used.

[0022]

As described above, according to the present invention, even when the delay time of a circuit having a long delay time and a low loop oscillation frequency is measured, the signal to be handled during the actual operation of the circuit under test 10 is measured. The delay time is measured by inserting the interpolating pulse P _I having a frequency close to that in the loop oscillation cycle, so that the circuit under test 10 operates with substantially the same power consumption as in the actual operation, which is the case in the CMOS type IC. However, the delay time can be measured under the temperature condition in which the temperature inside the IC chip is almost equal to that in actual operation. Therefore, there is an advantage that the correct delay time can be measured.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a pulse generator for measuring delay time according to the present invention.

FIG. 2 is a timing chart for explaining the operation of FIG.

FIG. 3 is a block diagram for explaining a conventional technique.

FIG. 4 is a timing chart for explaining the operation of FIG.

[Explanation of symbols]

 10 circuit under measurement 13 output terminal 14 input terminal 21 loop connection means 30 pulse generator for delay time measurement 31, 32, 34 gate means 33 pulse shaping circuit 35 start pulse generator 36 synchronous oscillation circuit 38 storage means 39, 41 counter 40 42 Control means

Claims (2)

[Claims] 1. A loop oscillation circuit is constructed by connecting an output terminal and an input terminal of a circuit to be measured whose delay time is to be measured, and an oscillation cycle of the loop oscillation circuit is measured to measure the circuit to be measured. In the delay time measuring method for measuring the delay time of, the signal under test is inserted into the oscillation cycle of the loop oscillation circuit, and a signal having a frequency close to the frequency of the signal passing during actual operation of the circuit under test is inserted. A delay time measuring method characterized in that the delay time is measured by operating in a state close to the above. 2. A. A synchronous oscillating circuit that synchronizes with the oscillation of a loop oscillating circuit composed of the circuit under test and that oscillates in a cycle close to the cycle of the circuit under test in operation; Storage means for storing the number of oscillation cycles of the synchronous oscillation circuit that can exist within the oscillation cycle of the loop oscillation circuit composed of the circuit under test; A counter for counting the number of oscillation cycles of the synchronous oscillation circuit stored in the storage means; Gate means for stopping the oscillation of the synchronous oscillation circuit immediately after counting the number of oscillation cycles of the synchronous oscillation circuit stored in the storage means by the counter; Pulse extraction means for extracting the first pulse of the pulse train output from the circuit under measurement, and F. A pulse generator for delay time measurement constituted by control means for returning the counter to the initial state by the pulse taken out by the pulse taking means and restarting the oscillation of the synchronous oscillation circuit.