KR20080048487A - Strobe technique for time stamping a digital signal - Google Patents

Abstract

A system and apparatus generates a time-stamp to identify and record the time of an event such as an edge received in a data signal or clock signal. A set of strobe pulses can be generated by routing an external clock signal to delay elements with incrementally increasing delay values. A data signal or device under test clock signal can be applied to the input to each of a set of latches which are clocked by the strobe pulses. The set of latches can thereby capture a series of samples of the data signal or clock signal. The series of samples can be encoded as an edge time within a clock cycle. A clock cycle counter can be added to the edge time to generate the time stamp.

Description

STROBE TECHNIQUE FOR TIME STAMPING A DIGITAL SIGNAL

TECHNICAL FIELD The present invention generally relates to automated testing of semiconductor chips, and more particularly to clocking of automated test equipment.

Automatic test equipment (ATE) is commonly used to test semiconductor chips and integrated circuits during their manufacture. Functional testing is usually performed by configuring the ATE to apply electrical signals to multiple connection points on the device under test (DUT) while measuring the output response of the DUT at a particular connection point.

ATE usually measures the relative timing between the applied input signal and the measured output signal when measuring the performance of the DUT. Highly accurate timing of the test system clock is necessary to ensure that the proper data has been collected, especially when evaluating the DUT's response to the speed signal.

It is required to test the performance of the DUT against its own system clock. Accordingly, the ATE can be configured to measure the output at a time relative to the internal clock of the DUT. However, measurements of the DUT's system clock may be inaccurate at high data rates and clock rates because signal slewing and jitter can significantly affect the measurement results.

Many integrated circuits (ICs) include a bus with a synchronous clock accompanied by data. Accessing the DUT's synchronous internal clock without the help of expensive test system hardware channels is impractical. Using test systems to test data on the bus with a synchronous clock has been a problem because data on the bus can have very high jitter to the test system clock.

A method of using a test system to emulate a DUT clock for comparison with a DUT data signal without undue slew and jitter that is primarily associated with the use of the clock system is incorporated herein by reference, and is incorporated herein by reference in Event No. 81) 077331-0104, described in Applicant's co-pending US application Ser. No. 11 / 234,542, filed September 23, 2005, entitled "Strobe Technology for Timing of Digital Signals."

It is often required to obtain and correlate precise edge times of clock and data signals with time stamps. In the field of ATE, it is often required to record the time at which a particular data signal edge or clock signal edge is received from the DUT, for example by a time stamp.

Embodiments of the present invention generate a time stamp to identify and record the time of an event, such as an edge received from a data signal or clock signal. In one embodiment, a set of strobe pulses is generated by routing an external clock signal, such as a MOSC / 8 clock, in a series of delays with incremental delays. Digital signals, such as data signals or synchronous clock signals, are applied to the inputs to each of the sets of parallel latches clocked by strobe pulses. This set of parallel latches captures a sample of a single short series of data or clock signals.

An encoder converts the samples of the single short series into words representing the edge time and polarity of the sampled signal. If this signal is a data signal, the word may be stored in RAM. If this signal is a clock signal, the word is routed to the clock bus and can be used to address the RAM. The difference between clock edge time and data edge time can be measured and compared against the predicted value.

A counter that receives an external clock signal can also be used to identify which clock cycle is currently input to the sampler. The encoded edge time of the data signal or clock signal output from the encoder can be input to the time stamp circuit along with the output from the counter. This time stamp circuit combines the counter output with the encoded edge time to output the precise time of the current clock edge. Time stamp logic can be added to latch precise time information or to route it to memory.

In one embodiment, the invention provides a method of providing a strobe triggered by a time stamp clock and comprising a plurality of strobe pulses; Applying the strobe to the digital signal of a device; Storing the state of the digital signal at the time of the strobe pulses of the strobe; And combining a time stamp clock count with at least one time of the strobe pulses. In one embodiment, the strobe includes a plurality of uniformly spaced strobe pulses having a frequency above the frequency of the digital signal. This digital signal can be, for example, a data signal or a clock signal.

Certain embodiments of the present invention read the stored state of the data signal at a time corresponding to a strobe pulse in which the state change of the clock signal occurs. The delay between the state change of the data signal and the state of the clock signal can be measured by counting strobe pulses therebetween.

The strobe is generated by applying the time stamp clock to a delay circuit comprising a plurality of delay elements and providing a connection between each of the delay elements to receive a plurality of sequential delayed copies of the pulses in the time stamp clock signal. . In one embodiment, the plurality of delay elements are arranged in series. This delay circuit can be controlled by a delay lock loop, the delay element comprising a controllable summing element that is tunable to compensate for delay line error.

In one embodiment, the strobe applies each of the strobe pulses to a corresponding latch of a plurality of latches as a latch clock signal, applying a digital signal of the device under test to each input of the latch and the test under test. The state of the digital signal of the device can be applied to the digital signal of the device under test by receiving as a respective output of the latch.

Storage of the data signal comprises receiving in parallel a strobed sample of the digital signal of the device under test as a series of samples and encoding the strobed sample as a digital word to identify a time of state change in the digital signal. Can be executed by a step. In a particular embodiment, the digital word can be added to the clock count to generate a time stamp. The digital word thus generated can be demultiplexed to reduce the data rate of the digital word. The time stamp can then be output in association with a transition event in the data or clock signal of the device under test.

In another embodiment, the present invention provides an apparatus for generating a time stamp for a digital signal. This device example includes a time stamp clock that provides an input to the sampling circuit. This sampling circuit includes a plurality of increasing strobe delays of a time stamp clock that each trigger a latch that samples the digital signal of the device under test. The encoder is arranged to be in communication with the sampling circuit. The encoder converts the sampled digital signal into edge time data of a binary word. The counter is arranged to be in communication with the time stamp clock and outputs a count of the time stamp clock to the time stamp circuit. A time stamp circuit combines the count with the binary word to produce a time stamp of an edge / event of a digital word. In a particular embodiment, the time stamp logic circuit is arranged to be in communication with the time stamp circuit. This time stamp logic circuit is designed to output the time stamp of the edge / event.

The above and other features and advantages of the present invention will be better understood with reference to the following figures and description thereof.

1 is a functional block diagram of a method for testing a data signal or a clock signal of a device under test using certain elements of an embodiment of the invention;

2 is a schematic timing diagram illustrating the application of a strobe to a data signal and a synchronous clock signal in accordance with an embodiment of the present invention;

3 is a schematic diagram of a multistrobe sampler used in a plurality of embodiments of the invention, and

4 is a schematic diagram of an apparatus for testing a data signal or clock signal of a device under test using certain elements of an embodiment of the invention.

5 is a functional block diagram of a method for providing a time stamp for an edge / event in a data or clock signal in accordance with an embodiment of the invention;

6 is a schematic diagram of an apparatus for providing a time stamp to an edge / event in a data or clock signal in accordance with an embodiment of the present invention.

An example of a method for testing and evaluating synchronous clocked data without directly comparing a synchronous signal to a data signal under test is described with reference to FIG. 1.

In the sampling step 10, the data signal and clock signal under test (DUT) are sampled to obtain a binary value of the state of the signal at high speed using a strobe. Thus, sampled data is obtained in a latched state as a single short series of dense samples of the data signal or clock signal under test. Although the term “single shot” is used herein, sampling of multiple or multiple channels, for example, with multiple iterations of a time stamping method, can be achieved in various embodiments of the invention. It should be understood that multiple iterations of step 10 may be performed.

In a single short series, the edge time and edge polarity of the data signal and / or clock signal of the device under test are detected. In encoding step 12, the detected edge time and polarity are encoded in a binary word. In an embodiment, the encoded edge time is represented as the five least significant bits of the six bit word and the polarity is represented as the most significant bit.

In one example of high speed test equipment using the present invention, an encoded 6 bit word is generated at approximately 2 gigabytes per second. Storage and Comparison Steps To provide a more suitable data rate for downstream, the encoded words can be multiplexed to provide 489 bit words at only 250 megabits per second. The 48-bit word indicates eight 5-bit edge times and the corresponding eight one-bit edge polarities.

In the selector step 14, it is determined whether the encoded data indicates the edge time and polarity of the sampled data or the edge time and polarity of the sampled clock signal. If the encoded data indicates the edge time and polarity of the sampled data signal, then a storage step 16 is executed in which the encoded data is stored in the RAM. In this embodiment, 96x40 RAM is used to store the encoded data.

If the encoded data represents the edge time and polarity of the sampled synchronous clock signal, only encoded data with one polarity is selected and used as the clock edge time. In clock selection step 18, the encoded clock edge time is routed to the clock bus. Thus, clock edge data can be routed to multiple channels and used on one or more chips.

In memory access step 20, the clock data is used as a pointer to the RAM address of the corresponding encoded data signal edge time. In comparison step 22, the data edge time found in the memory at the clock address is compared to the predicted value to determine whether the indicated data signal edge time is within a prespecified limit of the indicated clock edge time. This can cause a pass / fail indication to be generated automatically.

Sampling step 10 is performed to obtain a dense read of the state of the data signal and / or clock signal of the DUT. 2 is a schematic timing diagram showing an example of relative timings of the data signal 24 and the clock signal 26 of the device under test. The data signal 24 in the device under test is shown as a voltage / logic level that changes state at the edge 28. Clock signal 26 is changing state at edge 30. Strobes 32 and 34 provide dense pulses that respectively trigger sampling of the state of the data signal under test.

This results in a series of bits 36, 38 indicating the state of the data under test or the clock signal at dense time intervals by sampling. The change in state 40 in the series of bits 38 representing the clock signal can be used as reference timing to compare against the state 42 of the data signal in the series of bits 36 representing the data signal. In this embodiment, the series of bits 36, 38 are further encoded before being compared as described herein with respect to FIGS. 1 and 4.

As used throughout this specification to describe a series of strobe pulses or signals, the term “dense” should be interpreted broadly and it should be understood that such spacing may vary depending on the needs of a particular test application. It should be understood that such pulses or signals that are "dense" with respect to the timing of the device under test may have or be more likely to have a higher frequency than the signal under test or the clock signal.

A sampling circuit for obtaining a strobed sample of the data under test or a clock signal is shown in FIG. 3. An initiator signal, such as a single strobe pulse, is generated by a conventional edge generator and applied to delay line input 44. The series of delay elements output a progressively delayed copy 48 of the initiator signal. In this embodiment, the progressively delayed copy 48 of the initiator signal is sent to a summation circuit (SUM) 50 as known in the art to interpolate between delay elements to produce a denser copy 52 of the initiator signal. to provide.

In this embodiment, the summation circuit 50 includes a summation element 54 each comprising a Gilbert cell based on fine verniers with eight settings (i.e. 3 bit control). This setting can be tuned to correct for delay line errors. Speed control current for the delay line element 46 is provided by a delay lock loop (DDL) 56. Each of the delay copies of the input strobe pulses is provided to the clock input of the corresponding D latch 58. The data signal under test or the synchronous clock signal is transmitted to its input at each of the D latches. As a result, the data stored in the D latch indicates a binary snapshot of the state of the data signal under test or the clock signal. In this embodiment, a set of 31 D latches are used to obtain a 31 bit wide, strobed representation of the signal under test.

An apparatus for using a strobe representation of a synchronous clock to test a data signal in a DUT in accordance with an embodiment of the present invention is described in FIG. The signal under test 59 and the strobe 61 are applied to the sampling circuit 62. In this embodiment, the sampling circuit 62 is the sampling device described in detail in FIG. Encoder circuit 64, in communication with sampling circuit 62, accepts a tightly strobed representation of the signal under test from sampling circuit 62, which is then edge edge and edge polarity (i.e. high to low or low to high). Switch to a data word that is displayed. In this embodiment, the encoder converts a 31 bit binary snapshot of the edge transition into a 6 bit word. The most significant bit is used to indicate edge polarity and the remaining five bits are used to indicate edge time. Although the encoding described herein uses a 6 bit word and a 1 bit polarity indication for illustration, those skilled in the art should understand that numerous other word lengths may be used and that data may be encoded under other designs within the scope of the present invention.

In an embodiment of the invention, a 6 bit word is output from the encoder at approximately 2 gigabytes per second. Demultiplexer 66 in communication with encoder 64 is used to convert the data into a 48-bit word at a data rate of 250 gigabytes per second. The 48-bit word includes eight 5-bit words representing edge time and their corresponding eight single polarity bits. Those skilled in the art should understand that demultiplexing is not necessary in all cases and that various other bit rate and / or demultiplexing details may be optional within the scope of the present invention.

The router circuit 70 is used to transmit a signal indicating the synchronous clock of the DUT to the tester clock bus 72. This routing circuit 70 also selects only one clock edge time with one polarity to represent the system clock. That is, select the edge time that represents the clock set (up polarity) and ignore the clock reset (down polarity). This allows the clock edge time sent to the tester bus 72 to be used for multiple channels.

The word output from the demultiplexer 66 representing the data signal of the DUT is stored directly in the RAM 68 without being selected as a clock signal. In this embodiment, the data is stored in 96 × 40 RAM. Those skilled in the art should understand that numerous other ram configurations may be used within the scope of the present invention.

The clock edge time on tester bus 72 is used as a pointer to address the data stored in RAM 68. Routing circuit 74 selects which clock on the bus to use as the pointer and sends the clock edge time to comparison circuit 76. The comparison circuit 76 provides the clock edge time as an address to the RAM 68 and reads the data edge time stored at this address. As a result, the data edge time addressed to RAM is compared with the clock edge time to measure the difference.

The comparison circuit 78 compares the predicted value 77 of the difference between the data edge and the synchronous clock edge with the difference found by the comparison circuit 76. The comparison circuit 78 outputs a pass or fail signal 80 for each comparison depending on whether the predicted difference is within certain limits.

Accordingly, various embodiments of the present invention provide a means for indicating a signal under test in precise edge time and the polarity of the transition at the corresponding edge time. The edge time and polarity so marked are stored for comparison with a timing signal such as the synchronous clock of the device under test. This timing signal is also displayed for its precise edge time. This indication of timing signal edge time may be provided to the clock bus for use through the test system, for example, to compare with the corresponding data signal edge time in RAM. The result of this comparison is checked against the predicted value to determine whether the device under test matches the test specification.

An example of a method of executing a time stamp operation can be achieved by adding a small number of steps to the method for testing and evaluating synchronous clocked data without directly comparing the synchronous signal to the data signal under test described with reference to FIG. 1. . An example method for performing a time stamp operation is described with reference to FIG. 5.

In the selection time stamp initiation step 9, it is determined whether to implement a time stamp or bypass this time stamp and not execute the multi strobe method of signal analysis as described in FIG. It should be understood that an alternative method according to the present invention may permanently call the time stamp system without the option to bypass the time stamp.

If the time stamp has been called, then a sampling step 11 is executed in which a clock, called the time stamp clock, starts the input strobe. As an example, the time stamp clock may be a system master oscillator clock divided by eight (MOSC / 8 clocks). If the time stamp is not called, a sampling step 10 is executed in which the edge generator initiates an input strobe. In either case, the data signal and clock signal of the device under test (DUT) are sampled to obtain a binary value of the states of the signals at high speed using a storobe. This sampled data is thus obtained as a single short series of samples of this sampled data. In the encoding step 12, the selector step 14, the storage step 16 and the clock selection step 18 can be executed as described above with reference to FIG. 1.

If the time stamp was selected or permanently configured in step 9, a time stamp calculation step 19 is executed in which edge time is added to the clock cycle to obtain the time stamp. This clock cycle counter counts the cycles of the clock that started the input strobe in the sampling step 11.

An example of an apparatus for generating a time stamp is described by adding an element to the apparatus of FIG. 4 for using a strobed representation of a synchronous clock to test a data signal in a DUT. An example apparatus for generating a time stamp is described with reference to FIG.

The digital signal 59 from the DUT is applied to the sampling circuit 62. Router 84 is used to select a second input to sampling circuit 62. If a time stamp is to be implemented, a clock signal, such as the signal generated by the MOSC / 8 clock 82, is input by the router 84 as the second input of the sampling circuit 62. If no time stamp implementation is selected, the signal from the edge generator 61 is applied by the router 84 as a second input to the sampling circuit 62. In this device example, the sampling circuit 62 is the sampling device described in detail in FIG. Encoder circuit 64, demultiplexer 66, router circuit 70, tester clock bus 72, RAM 68, router circuit 74, comparison circuit 76, and pass / fail signal 80 A comparison circuit 78 that acts on the predicted value 77 to output is configured and operates as described above with reference to FIG. 3.

If a time stamp implementation was chosen in step 9 of FIG. 5, router circuit 86 directs a word representing data edge time or clock edge time from demultiplexer 66 to time stamp circuit 90. The counter 88 in communication with the sampler start clock 82 counts the cycles of the time stamped clock. The counter 88 provides information to the time stamp circuit 90, which may be combined with a word representing edge time to form a time stamp. In an embodiment, time stamp circuit 90 adds the counter output to the encoded edge time to form a time stamp. This time stamp may be sent to the time stamp logic circuit 92 for output or storage, for example.

Accordingly, various embodiments of the present invention provide a means for generating a precise time stamp of the signal under test by adding a small number of elements to the multistrobe apparatus described above. The time stamp may be used to complement the multistrobe test method or may be standalone to perform only time stamp operations.

Although embodiments of the present invention have been described herein with respect to a multistrobe test apparatus that can be converted to a time stamp scheme by the way of a normal router, those skilled in the art should understand that the present invention can be configured as a dedicated time stamp. In a dedicated time stamp embodiment, for example, an input to the sampling circuit 62 of FIG. 6 is always provided by the clock 82. In this embodiment, the edge generator 61 and the router circuit 84 may be omitted. The router circuit 86 may also be omitted in the dedicated time stamp embodiment, because the connection between the demultiplexer 66 and the time stamp circuit 90 may be wired in this embodiment.

Although embodiments of the present invention have been described herein generally with respect to strobe pulses, those skilled in the art will appreciate that the strobe pulses may be configured to apply threshold voltages in cycles of various waveforms such as square waves, sinusoids, triangle waves, impulses, etc. to trigger corresponding latches. It should be understood that it may include. For example, it can be considered that the leading edge of the square wave pulse can be used as a strobe pulse in an embodiment of the present invention.

Although embodiments of the present invention have been described herein generally with respect to strobes generated by a series of sequential delay elements, those skilled in the art should understand that the delay elements may be configured in a number of alternative configurations within the scope of the present invention. For example, it is contemplated that the strobe initiator pulses may be applied to a plurality of delay elements arranged in parallel rather than in series within the scope of the present invention. It is also contemplated that a combination of series and parallel delay elements may be provided within the scope of the present invention to provide a plurality of dense copies of the strobe initiation signal.

While embodiments of the present invention have been described herein generally for automated test equipment, those skilled in the art should understand that the present invention may be useful in many other signal comparison operations. For example, the present invention is expected to be used as a timing element in an unlimited number of high speed processing applications.

It should be understood that various modifications may be made to the embodiments disclosed herein. Thus, the foregoing description has been presented as an example of various embodiments of the terminals, rather than to limit the invention. Those skilled in the art will appreciate that other modifications are within the scope of the claims appended hereto.

Claims (21)

In the time stamp generation method for a digital signal, Providing a strobe triggered by a time stamp clock and comprising a plurality of strobe pulses; Applying the strobe to the digital signal of a device; Storing the state of the digital signal at the time of the strobe pulses of the strobe; And Combining a time stamp clock count with a time of at least one of the strobe pulses, And said strobe has a frequency greater than or equal to the frequency of said digital signal. 2. The method of claim 1 wherein the strobe comprises a plurality of uniformly spaced strobe pulses. The method of claim 1, wherein the digital signal comprises a data signal. The method of claim 1, wherein the digital signal comprises a clock signal. The method of claim 1, wherein the strobe is Applying the time stamp clock to a delay circuit comprising a delay element; And Providing a connection between each of the delay elements to receive a plurality of sequential delayed copies of the pulses in the time stamp clock signal. 6. The method of claim 5, wherein the delay elements are configured in series. 7. The time stamp generation of claim 6, wherein said delay element is controlled by a delay lock loop, said delay element comprises a controllable summation element, said summation element being tunable to correct for delay line error. Way. The method of claim 1, wherein the strobe is Applying each pulse of the strobe to a corresponding latch of a plurality of latches as a latch clock signal; Applying the digital signal to each input of the latch; And Receiving the state of the digital signal of the device under test as the output of each of the latches, wherein the time stamp generation method is applied to the digital signal. The method of claim 1, wherein the storing step, Receiving the state of the digital signal as a series of samples; And Encoding the series of samples as a digital word to identify a time of state change in the digital signal. 10. The method of claim 9, wherein the digital word is added to the clock count to generate the time stamp. 11. The method of claim 10, further comprising outputting the time stamp in association with a transition event in the digital signal. 10. The multi-bit word of claim 9, wherein the encoding yields a multi-bit word having a first range of bits identifying the time of the state change and a second range of bits identifying the polarity of the state change. How to create a time stamp. 13. The method of claim 12, further comprising demultiplexing the transmission of the multibit word to reduce the transmission rate of the multibit. 15. The method of claim 13, further comprising storing the demultiplexed word in RAM at the reduced rate. A method of generating a time stamp for a data signal or a clock signal of a device under test, Initiating a strobe having a frequency above at least one of a data signal or a clock signal of the device under test using a time stamp clock signal; Applying a time stamp clock to a delay circuit comprising a series of delay elements; And Providing a connection between each of the delay elements to receive a plurality of sequential delayed copies of a pulse in the time stamp clock signal to produce the strobe; Applying each pulse of the strobe to a corresponding latch of a plurality of latches as a latch clock signal; Applying a data signal or clock signal of the device under test to each input of the latch; Receiving a state of a data signal or a clock signal of the device under test as each output of the latch; And Combining a time stamp clock with at least one time of the strobe pulses by adding a digital word representing the time of the at least one strobe pulse to the clock count. An apparatus for generating time stamps for digital signals, A time stamp clock providing an input to a sampling circuit comprising a plurality of increasing strobe delay elements in communication with the time stamp clock; An encoder in communication with the sampling circuit for converting the sampled digital signal into edge time data of a binary word; And A counter in communication with the time stamp clock for outputting a count of the time stamp clock to a time stamp circuit; The time stamp circuit combines the count with the binary word to generate a time stamp of an edge in the digital signal, Each of said plurality of increasing strobe delay elements triggering a corresponding latch for sampling a data signal or clock signal of a device under test. 17. The apparatus of claim 16, further comprising a time stamp logic circuit in communication with the time stamp circuit and for outputting a time stamp of the edge. The method of claim 16, A memory in communication with the encoder and storing the binary word if the digital signal is a data signal; A routing circuit in communication with the encoder, selecting a binary word having a set polarity if the digital signal is a clock signal and routing the binary word to a clock bus for use in a plurality of channels; A memory address line in communication with the clock bus and configured to select clock time data and to use the clock time data to address data stored in the memory; A first comparing circuit in communication with the memory and for comparing the clock time data to data stored in the memory; And And a second comparing circuit in communication with the first comparing circuit, the second comparing circuit comparing a predicted value of data corresponding to a particular clock time with a value indicated by a binary word in the memory. Generating device. The method of claim 16, An input routing circuit in communication with the sampling circuit; And And an edge generator in communication with the input routing circuitry. And the routing circuit selects between the input generator and the time stamp clock for input to the sampling circuit. 17. The apparatus of claim 16, wherein the digital signal comprises a data signal. 17. The apparatus of claim 16, wherein the digital signal comprises a clock signal.

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