JP4495308B2 - Semiconductor device testing method and semiconductor device testing equipment - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device test method suitable for use in testing a semiconductor device equipped with a memory capable of writing and reading at high speed, and a semiconductor device test apparatus that operates using this test method.
[0002]
[Prior art]
Before explaining the prior art relating to the present invention, an outline of an IC test apparatus for testing a general semiconductor device will be described.
In FIG. 9, TES indicates the entire semiconductor device test apparatus. The semiconductor device test apparatus TES includes a main controller 13, a pattern generator 14, a timing generator 15, a waveform formatter 16, a logic comparator 12, a driver 17, a signal reading circuit 11, a failure analysis memory 18, and a logic amplitude reference voltage source 19. , A comparison reference voltage source 21, a device power source 22, and the like.
[0003]
The main controller 13 is generally constituted by a computer system, and mainly controls the pattern generator 14 and the timing generator 15 in accordance with a test program created by the user, and generates test pattern data from the pattern generator 14, and this test pattern. The data is converted into a test pattern signal having an actual waveform by the waveform formatter 16, and the test pattern signal is voltage-amplified into a waveform having an amplitude value set by the logic amplitude reference voltage source 19 to the semiconductor device DUT to be tested. Apply and store.
[0004]
The response signal read from the semiconductor device under test DUT is read by the signal reading circuit 11 with its logical value. The logical comparator 12 compares the logical value read by the signal reading circuit 11 with the expected value output from the pattern generator 14, and if a mismatch with the expected value occurs, the memory cell at the read address is defective. Each time a failure occurs, a failure address is stored in the failure analysis memory 18 and, for example, it is determined whether or not a defective cell can be repaired at the end of the test.
[0005]
Although FIG. 9 shows the configuration of the test apparatus for one pin, in reality, this configuration is provided for the number of pins of the semiconductor device DUT to be tested. The input of the test pattern for each pin and the configuration of the semiconductor device DUT to be tested The response signal is captured.
The above is a configuration of a test apparatus for testing a general semiconductor device.
By the way, some types of memory composed of semiconductors input data together with a clock, write data to the semiconductor device in synchronization with the clock, and output data synchronized with the clock together with the clock from the semiconductor device. There is a memory that uses it to exchange data.
[0006]
FIG. 10 shows a state at the time of reading from this type of memory. DA, DB, DC... Shown in FIG. 10A indicate data output from the semiconductor device (data output from a certain pin). TD1, TD2,... Indicate each test cycle. DQS shown in FIG. 10B indicates a clock output from the memory. Data DA, DB, DC,... Are output from the semiconductor device in synchronization with the clock DQS. This clock is used as a synchronizing signal (data strobe) when transferring data DA, DB, DC,.
[0007]
One of the test items when testing this type of semiconductor device is the time difference (phase difference) from the rise and fall timing of each clock DQS (hereinafter referred to as the reference clock) to the data change point. There are items for measuring dI1, dI2, dI3. These time differences dI1, dI2, dI3,... Are evaluated as devices having excellent characteristics with quick response as the time is as short as possible. The grade of the semiconductor device under test is determined by the length of this time difference.
[0008]
When the reference clock DQS output from the semiconductor device under test is in practical use, the clock generated by the clock source is applied to the semiconductor device, and this clock is distributed to the internal circuit of the semiconductor device and synchronized with this clock. Data is output. Therefore, even when a test is performed by a test apparatus, a clock is applied from the test apparatus side to the semiconductor device under test, and the clock passes through the semiconductor device under test and is output as a reference clock for data delivery along with the data. . Therefore, the rising and falling timings of the reference clock are measured, and the times dI1, dI2, dI3,... From the measured rising and falling timings to the changing points of the data DA, DB, DC,. Become.
[0009]
As described above, since the reference clock output from the semiconductor device is output through the inside of the semiconductor device, the rising timing and falling timing are determined depending on the internal environment of the semiconductor device and the external environment such as temperature. As shown in FIG. 11, there is a phenomenon that a difference occurs in the phases of the reference clocks DQS1, DQS2, DQS3,... Furthermore, in addition to the difference in phase due to the difference in each semiconductor device, there is also a phenomenon in which a so-called jitter J that fluctuates with the passage of time (thermal change) occurs in the address of the memory accessed inside the semiconductor device. It is done.
[0010]
Therefore, in order to accurately measure the times dI1, dI2, dI3... From the rising timing and falling timing of the reference clock DQS to the change points of the data DA, DB, DC. The rising timing and falling timing of the reference clock DQS must be accurately measured.
For this reason, the strobe pulse application timing of the signal reading circuit conventionally provided in the semiconductor device test apparatus is gradually moved, the rising and falling timings of the reference clock DQS are measured, and the time dI1 is measured using the measurement result. , DI2, dI3,...
[0011]
FIG. 12 shows a portion for measuring the rising and falling timings of the reference clock DQS conventionally used. The level comparator 10 is composed of a pair of voltage comparators CP1 and CP2, and whether the logical value of the reference clock DQS output from the semiconductor device under test DUT by the pair of voltage comparators CP1 and CP2 satisfies a normal voltage condition. Determine whether or not. The voltage comparator CP1 determines whether or not the H logic voltage value of the reference clock DQS is equal to or higher than the normal voltage value VOH. The voltage comparator CP2 determines whether or not the voltage value on the L logic side of the reference clock DQS is equal to or lower than the normal voltage VOL.
[0012]
These determination results are input to the signal reading circuit 11, and the signal reading circuit 11 measures the rising timing and falling timing of the reference clock DQS. The signal reading circuit 11 executes an operation of reading the logical value input at that time every time the strobe pulse STB is applied.
As shown in FIG. 13, the strobe pulse STB is applied with a slight phase difference (τT) for each test cycle. That is, for each test cycle, one straw portion pulse STB is given to the signal reading circuit 11 to execute an operation of reading the output states of the voltage comparators CP1 and CP2.
[0013]
The logical comparator 12 compares the logical value output from the signal reading circuit 11 with a predetermined expected value (H logic in the example of FIG. 12), and when the logical value output from the signal reading circuit 11 matches the expected value. To output a path signal PA representing a path (good). Knowing the time T1 (FIG. 13C) from the generation timing of the strobe pulse STB1 (FIG. 13B) (the generation timing of the strobe pulse STB is known) that has read that the output of the level comparator 10 is inverted to H logic, the rising edge of the reference clock DQS Determine the timing.
[0014]
When detecting the falling timing of the reference clock DQS, the generation of the strobe pulse STB starts at a timing later than the timing when the reference clock DQS rises to the H logic, and in the same way as the rising detection, the voltage comparator The falling timing is verified by a strobe pulse obtained by reading the state in which the output of CP2 is inverted to H logic.
As described above, conventionally, the generation timing of the reference clock DQS is measured using the signal reading circuit 11 provided in the semiconductor test apparatus and the timing measuring means using the strobe pulse STB applied to the signal reading circuit 11. Therefore, there is a drawback that it takes time because the test cycle TD must be repeatedly executed even if only the rising and falling timings of the reference clock DQS are measured.
[0015]
Moreover, the rising and falling timings of the reference clock DQS are measured over all addresses from the start to the end of the test pattern in order to avoid the effects of jitter caused by all the addresses of the memory under test to be tested or heat generation. Therefore, it takes a long time to measure the rising and falling timings of the reference clock.
As a method of shortening the time for measuring the rising and falling timings of the reference clock DQS, the phase difference τT given to the strobe pulse STB can be roughly taken to reduce the number of executions of the test cycle, but it is given to the strobe pulse STB. When the phase difference τT is roughly changed, the accuracy of the timing measurement of the rising and falling edges of the reference clock DQS is reduced, and as a result, the times dI1, dI2, and the time from the reference clock DQS to the change points of the data DA, DB, DC. There is a drawback that the reliability of the measurement results of dI3.
[0016]
In order to eliminate these inconveniences, the present applicant proposed “Japanese Patent Application No. 2000-009113: name semiconductor device test method / semiconductor device test apparatus” on January 18, 2000.
In order to facilitate understanding of the present invention, an outline of the semiconductor device test method and semiconductor device test apparatus previously proposed will be briefly described.
FIG. 14 shows the configuration of the main part of a semiconductor device test apparatus that operates using the previously proposed semiconductor device test method. As shown in FIG. 14, the previously proposed semiconductor device test apparatus has a level comparator 10, a multi-phase pulse generator 30, and a plurality of signal reading circuits TC1, TC2, TC3 for pins that output the reference clock DQS. , TC4, TC5..., A plurality of comparison / determination means PF1, PF2, PF3, PF4, PF5... And the comparison results of these comparison / determination means PF1, PF2, PF3, PF4, PF5. Conversion means 31 for converting, a memory 32 for storing the phase number, a timing selection circuit 33 for selecting and outputting the generation timing of the strobe pulse STB from the phase number read from the memory 32 during the test, and the timing selection circuit And a strobe generation circuit 34 for generating a strobe pulse STB at the timing selected in 33. Those proposed conductor device tester.
[0017]
In this example, the multi-phase pulse generator 30 is constituted by a plurality of delay elements DY1, DY2, DY3, DY4, DY5,... Having delay times slightly different from each other. By giving the delay time of each delay element DY1, DY2, DY3, DY4, DY5,..., For example, 100 PS (picosecond), a multiphase pulse having a time difference of 100 PS can be generated.
FIG. 15 shows an example of a multiphase pulse. Multi-phase pulses P1, P2, P3, P4,..., Each having a phase difference of, for example, 100 PS from a predetermined phase position of the test cycle TD, are input to each strobe pulse of the signal reading circuit TC1, TC2, TC3, TC4, TC5 Given to the terminal.
[0018]
A level comparison result is input from the level comparator 10 to each input terminal of the signal reading circuits TC1, TC2, TC3, TC4, TC5. FIG. 14 shows a configuration for measuring the rising timing of the reference clock DQS. Therefore, the output of the voltage comparator CP1 that performs level comparison on the H logic side is input to each input terminal of the signal reading circuits TC1, TC2, TC3, TC4, TC5.
Although the configuration for measuring the timing on the falling side of the reference clock DQS is omitted in FIG. 14, the configuration is the same as the configuration shown in FIG. 12, and in this case, a voltage comparator that performs level comparison on the L logic side The output of CP2 is read with multiphase pulses.
[0019]
FIG. 15 shows how to measure the rising timing of the reference clock DQS, and FIG. 16 shows how to measure the falling timing of the reference clock DQS. 15A and 16B show waveforms of the reference clock DQS output from the pin that outputs the reference clock of the semiconductor device under test DUT. The voltage comparator CP1 constituting the level comparator 10 is supplied with the comparison voltage VOH. When the level of the reference clock DQS becomes higher than the comparison voltage VOH, the voltage comparator CP1 outputs an H logic.
[0020]
Therefore, when a strobe pulse composed of multi-phase pulses is applied after the voltage comparator CP1 outputs H logic, the signal reading circuit outputs H logic. The comparison determination means PF1, PF2, PF3, PF4, PF5... Compare the expected value (H logic in this example) with the reading results of the signal reading circuits TC1, TC2, TC3, TC4, TC5. When the outputs of TC1, TC2, TC3, TC4, TC5... Match the expected value of the H logic, the H logic indicating the match is output.
[0021]
Each of the comparison / determination means PF1, PF2, PF3, PF4, PF5,. The comparison is made, and it is determined that it is valid when a mismatch occurs between the comparison determination result in the previous stage and its own signal reading result, and a determination result representing the validity is output. 15 and 16 show a case where the comparison determination means PF4 outputs an H logic determination result indicating validity.
[0022]
FIG. 17 shows an example of a specific configuration of the PF 4 as an example of the comparison determination unit. FIG. 17 shows a case in which the circuit can also be used as a circuit for measuring the falling timing of the reference clock DQS. Therefore, the signal reading circuit TC4 ′ is connected to the output side of the voltage comparator CP2, and the multiphase pulses P4 and TC4 ′ shown in FIGS. 15 and 16 are strobe pulses at the strobe input terminals of the signal reading circuits TC4 and TC4 ′. As given.
[0023]
The comparison / determination means PF4 compares the expected value EXP with the outputs of the signal reading circuits TC4 and TC4 ′, the OR gate G3 for ORing the outputs of these gates G1 and G2, and the output of the OR gate G3. A mismatch detection gate G4 that detects a mismatch with the comparison determination result in the previous stage can be used.
The rising timing of the reference clock DQS can be detected by a system path including the voltage comparator CP1, the signal reading circuit TC4, the gate G1, the OR gate G3, and the mismatch detection gate G4. An H logic is given as an expected value when the rising timing of the reference clock DQS is measured, and an L logic is set as an expected value when the falling timing is detected. By setting the expected value of H logic, the gate G1 becomes effective, and this gate G1 monitors whether the output of the signal reading circuit TC4 is inverted to H logic.
[0024]
When the output of the signal reading circuit TC4 is inverted to H logic, the output of the gate G1 is also inverted to H logic, and the H logic is input to the mismatch detection gate G4 through the OR gate G3. The mismatch detection gate G4 can be constituted by, for example, an exclusive OR circuit, and the comparison determination result P / F of the previous stage is given to one input terminal thereof.
The mismatch detection gate G4 outputs H logic only when the comparison determination result P / F in the previous stage is not H logic and the reading result of its own signal reading circuit TC4 is inverted to H logic. The output of this H logic is input to the conversion means 31 shown in FIG. 14, and is also supplied to the comparison / determination means of the next stage, here PF5. In the next stage comparison judgment means PF5, its own signal reading circuit PC5 outputs the H logic, but since the H logic is inputted from the previous stage comparison judgment means PF4, the mismatch detection result is not outputted and the L logic is outputted. The
[0025]
As a result, only the comparison / determination means to which the multiphase pulse is first applied from the time when the level of the reference clock DQS exceeds the comparison voltage VOH provided for level comparison outputs the H logic. Note that L logic is given to the mismatch detection gate G4 of the first-stage comparison / determination means PF1 as the comparison / determination result of the previous stage. Thus, when its own signal reading circuit TC1 outputs H logic, it outputs an H logic mismatch detection signal, and detects that the reference clock DQS rises at the beginning of the test cycle TD.
[0026]
The conversion means 31 takes in the comparison determination results of the respective comparison determination means PF1, PF2, PF3, PF4, PF5..., And converts them into data with as small a bit number as possible. In other words, in the previously proposed invention, the comparison determination means PF1, PF2, PF3, PF4, PF5... Are converted into the phase numbers of the multiphase pulses that give the reading results of the signal reading circuit in which the respective determination results are valid. It is characterized by a point.
FIG. 18 shows a conversion algorithm of the conversion means 31. The signal reading circuits TC1, TC2,... And the comparison / determination means PF1, PF2,... Are desirably provided in a number that can be set at a strobe interval that can sufficiently satisfy the measurement accuracy with respect to the device specifications. The comparison determination means PF1 to PF8 are shown as being present. When any one of the eight comparison determination means PF1 to PF8 outputs H logic (indicated by 1 in the figure), the bit position is converted to a numerical value 1 to 8, and “1” is subtracted from the numerical value. In this example, the subtraction result is converted to 4-bit numerical data D0 to D7. The 4-bit numerical data F0 to F7 can be handled as numbers representing the phase order of the multiphase pulses P1 to P8. It can be converted into numbers for 16 phases of 0 to 15 by 4 bits, and this phase number is stored in the memory 32.
[0027]
In this way, for example, by converting the 8-bit comparison / determination result into 4-bit phase number data, there is an advantage that the storage space of the memory 32 can be reduced.
[0028]
FIG. 19 shows an outline of the timing selection circuit 33. The timing selection circuit 33 includes a timing memory 33A that stores the generation timing of the strobe pulse STB, and a selector 33B that selects one of the generation timings stored in the timing memory 33A according to the measurement result read from the memory 32. .
For example, 16 types of time values of 200 PS, 300 PS, 400 PS, 500 PS,... Are stored in the timing memory 33A. This time value corresponds to the time value from the initial phase position of each test cycle TD, and indicates the rising or falling timing of the measured reference clock DQS. The timing given by this time value becomes the reference phase position for measuring the times dI1, dI2, dI3... Until the data change point to be measured. This time value is selected according to the measurement result stored in the memory 32, and the selected time value is input to the strobe generation circuit 34.
[0029]
The strobe generation circuit 34 adds or subtracts the time (scheduled value) until the data change point read from the semiconductor device DUT to be read from the time value input from the timing selection circuit 33, and the strobe pulse STB at the timing of the calculation result. And applying the strobe pulse STB to the signal reading circuit 11 to read the data read from the semiconductor device under test DUT, and test whether there is a data change point at the strobe pulse timing. To do.
[0030]
That is, the designer of the semiconductor device grasps the time from the rising or falling timing of the reference clock DQS to the change point of the data read from the semiconductor device as a design value in advance. Therefore, by measuring the rising and falling timings of the reference clock DQS in advance and setting the timings to known values, the data changes within the predetermined time range from the rising and falling timings of the reference clock DQS. By testing whether or not a dot exists, an accurate inspection can be performed.
FIG. 20 shows a modified embodiment of the multiphase pulse generator 30. In this embodiment, delay elements DY1, DY2, DY3,... Having a slight delay time equal to each other are continuously connected, and each of the continuously connected delay elements DY1, DY2, DY3,. An example is shown as a configuration for generating a multiphase pulse to which a phase difference is given.
[0031]
[Problems to be solved by the invention]
In the previously proposed invention, the timing of the reference clock DQS is measured over the entire test pattern generation length (all test cycles) for testing the semiconductor device under test, the measurement result is stored in the memory 32, and this measurement result is stored. Since a test method for executing an actual test using the method has been adopted, there is a drawback that the time required for the test is doubled.
The present invention intends to propose a semiconductor device test method and a semiconductor device test apparatus that can complete a test only by executing the entire test pattern generation length once.
[0032]
[Means for Solving the Problems]
According to the first aspect of the present invention, the rising or falling timing of each data read from the semiconductor device under test and the rising or falling timing of the reference clock output in synchronization with these data are slightly set. Sampling is performed with a strobe pulse composed of multi-phase pulses given a phase difference, and the phase difference between the timing of each data and the timing of the reference clock is measured, and is this phase difference within a predetermined range? A semiconductor device test method for determining the quality of a semiconductor device under test based on whether or not the device is good is proposed.
[0033]
According to claim 2, in the semiconductor device test method according to claim 1, a multiphase pulse is generated for each test cycle in which a phase difference is given little by little from a predetermined phase position of each test cycle. The pulse is used as a strobe pulse of the signal reading circuit for detecting the generation timing of the reference clock and the signal reading circuit for detecting the generation timing of each data, and the phase of the strobe pulse in which the change point of the reference clock is detected The phase number of the strobe pulse in which the number and the change point of each data are detected is defined as the reference clock and the phase of each data, and the semiconductor device under test depends on whether or not the difference value of this phase number is within a predetermined value range We propose a semiconductor device test method for determining the quality of a semiconductor device.
[0034]
According to a third aspect of the present invention, in the semiconductor device testing method according to the first aspect, for each test cycle, a multiphase pulse is generated in which a phase difference is given little by little from a predetermined phase position of each test cycle. A multi-phase pulse is used as a strobe pulse for a signal reading circuit for detecting the generation timing of a reference clock and a signal reading circuit for detecting the generation timing of each data, and a strobe pulse for detecting a change point of the reference clock A semiconductor device test method is proposed in which a reference table is accessed by each of the phase number of the data and the phase number of the strobe pulse in which the change point of each data is detected, and the pass / fail judgment result is directly read from the reference table.
[0035]
In claim 4 of the present invention,
A, a plurality of sets of signal reading circuits provided for measuring the generation timing of data output from the semiconductor device under test;
B, a set of signal reading circuits provided for measuring the generation timing of the reference clock output from the semiconductor device under test;
C, multiphase pulse generating means for applying a strobe pulse composed of multiphase pulses in which a phase difference is slightly given to each set of signal reading circuits;
D, a plurality of sets of comparison determination means for comparing the result read by each of the plurality of signal reading circuits with an expected value;
E, reference phase number conversion means for giving a reference phase number to the strobe pulse that has detected the change point of the reference clock in the determination results of the plurality of sets of comparison determination means;
F, a plurality of data phase number conversion means for giving a data phase number to each of the strobe pulses that have detected a change point of each data in the determination results of the plurality of sets of comparison determination means;
G, a plurality of phase difference detection units that convert the reference phase number conversion means and the data phase number conversion means to obtain a difference between the reference phase number and each data phase number;
H, a quality determination unit that determines whether or not the phase difference output by the plurality of phase difference detection units is within a predetermined range;
A semiconductor device test apparatus constituted by the following is proposed.
[0036]
In claim 5 of the present invention,
A, a plurality of sets of signal reading circuits provided for measuring the generation timing of data output from the semiconductor device under test;
B, a set of signal reading circuits provided for measuring the generation timing of the reference clock output from the semiconductor device under test;
C, multiphase pulse generating means for applying a strobe pulse composed of multiphase pulses in which a phase difference is slightly given to each set of signal reading circuits;
D, a plurality of sets of comparison determination means for comparing the result read by each of the plurality of sets of signal reading circuits with an expected value;
E, reference phase number conversion means for giving a reference phase number to the strobe pulse that has detected the change point of the reference clock in the determination results of the plurality of sets of comparison determination means;
F, a plurality of data phase number conversion means for giving a data phase number to each of the strobe pulses that have detected a change point of each data in the determination results of the plurality of sets of comparison determination means;
G, the reference phase number is input to one address, each data phase number is input to the other address, and it is referred to whether the generation timing of each data is within a predetermined range, and the reference result is used as a pass / fail judgment result Multiple lookup tables to output,
A semiconductor device test apparatus constituted by the following is proposed.
[0037]
According to claim 6 of the present invention, in any one of the semiconductor device test apparatuses according to claim 4 or 5,
The multi-phase pulse generating means is composed of a plurality of delay elements having slightly different delay times, and a semiconductor device configured to generate a multi-phase pulse having a slight phase difference by applying pulses to the plurality of delay elements. Propose test equipment.
According to claim 7 of the present invention, in any one of the semiconductor device test apparatuses according to claim 4 or 5,
A multi-phase pulse generating means proposes a semiconductor device testing apparatus configured to continuously connect a plurality of delay elements having the same delay time and obtain a multi-phase pulse from each connection point of the plurality of cascade-connected delay elements.
[0038]
According to claim 8 of the present invention, in any one of the semiconductor device test apparatuses according to claim 4 or 5,
The plurality of comparison / determination means output the comparison / determination results to the comparison / determination means having the next longest delay time in order from the side having the shortest delay time of the strobe pulse composed of multiphase pulses. A configuration in which a valid determination result is output only from the comparison determination means that has detected a mismatch with the determination result, and an output bit position of the valid determination result is converted into a phase number of a strobe pulse in which a conversion store of the reference clock is detected A semiconductor device test apparatus is proposed.
[0039]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows an embodiment of the present invention. In FIG. 1, parts corresponding to those in FIG. In the present invention, the data D0, D1,... Output from the semiconductor device under test are respectively compared with the reference clock DQS by the level comparator 10, and the level comparison result is supplied to the signal reading circuit 40. The reference clock DQS is The rising or falling timing of all the data D0, D1,... Is measured with a strobe pulse STRB composed of multiphase pulses generated by the multiphase pulse generator 30. Here, description will be made assuming that the rising timing described with reference to FIG. 15 is detected.
[0040]
The output of the signal reading circuit 40 is input to the comparison / determination means 50, and the comparison / determination means 50 determines which phase strobe pulse in the multi-phase strobe pulse changes at the rising edge of the data D0, D1,... And the reference clock DQS. It is determined whether or not
The determination operation of the comparison / determination means 50 is configured so that only the phase comparison unit that captures the change point preferentially outputs “1” as in the description of FIG. 17.
[0041]
When the comparison determination means 50 determines which phase strobe pulse has detected the data D0, D1,... And the change point of the reference clock DQS, the determination result is input to the data phase number change means 31D and the reference phase number conversion means 31R. The data phase number DN0 and the reference phase number RN0 are converted.
FIG. 2 shows the conversion algorithm of these phase number conversion means 31D and 31R. In the example shown in FIG. 2, the bit position of the phase for which “1” logic is output by the determination means 50 is converted as it is into numerical data F1, F2, F3, F4, F5, F6, F7, and F8, and the numerical data F1 to F8. Is output as the data phase number DN0 and the reference phase number RN0.
[0042]
The data phase number DN0 converted by the data phase number conversion means 31D and the reference phase number RN0 converted by the reference phase number conversion means 31R are respectively the rising timing of each data D0, D1, D2, D3. Phases that define the timing are determined, and these are compared by the phase comparison unit 60.
FIG. 3 shows an example of the phase comparison unit 60. In this example, the phase comparison unit 60 is configured using a digital subtractor. The data phase number DN0 is input to the positive input terminal side, and the reference phase number RN0 is input to the negative input terminal side.
[0043]
Therefore, when the data phase number DN0 is “6” as shown in FIG. 4 and the reference phase number RN0 is “3”, X = 6−3 = 3 is output as the output X of the phase comparison unit 60. .
Further, when the data phase number DN0 is “3” and the reference phase number RN0 is “7” as shown in FIG. 5, the output X of the phase comparison unit 60 is X = 3-7 = −4.
FIG. 6 shows an example of the configuration of the pass / fail judgment means 70 and the spec setting unit 71. The spec setting unit 71 can be composed of registers G1 and G2, and the user sets set values of specifications corresponding to the semiconductor device under test in the registers G1 and G2. Here, “5” is set in the register G1, and “0” is set in the register G2.
[0044]
The pass / fail judgment means 70 can be composed of two subtracters U1 and U2, two encoders E1 and E2, and an OR gate OR. The phase comparison result X of the phase comparator 60 is input to the minus input terminal of the subtractor U1 and the plus input terminal of the subtractor U2, and the setting set in the register G1 constituting the spec setting unit 71 is set to the plus input terminal of the subtractor U1. The value “5” is input, and “0” set in the register G2 is input to the minus input terminal of the subtractor U2.
[0045]
The encoders E1 and E2 output 0 logic if the outputs of the subtracters U1 and U2 are positive, and output 1 logic if they are negative.
The OR gate OR outputs the outputs of the encoders E1 and E2 and outputs a pass / fail judgment result PASS / FAIL. When the output of the OR gate OR is 0, it is judged as pass (good), and when it is 1, it is judged as fail (bad).
Therefore, in the example shown in FIG. 4, since X = 3, the output of the subtractor U1 is 5-3 = 2 and the output of the subtractor U2 is 3-0 = 3, so the outputs of the encoders E1 and E2 Both become 0 and are determined to be paths.
[0046]
On the other hand, since X = −4 in the example shown in FIG. 5, the output of the subtractor U1 is 5-(− 4) = 9, and the output of the subtractor U2 is −4−0 = −4. Is 0, but the output of the encoder E2 is 1, so that the determination output of the OR gate OR is 1 and it is determined as fail.
In other words, as a setting example in this case, a case is set in which it is determined to be defective when the phase of the reference clock DQS is delayed from the phase of the data.
[0047]
The determination result of the pass / fail determination means 70 varies depending on the set value set in the spec setting unit 71, but the determination result is variously changed according to the convenience of the user.
FIG. 7 shows a modified embodiment of the present invention. In this embodiment, a reference table 80 constituted by a memory is prepared at each subsequent stage of the data phase conversion means 31D and the reference phase conversion means 31R, and the pass / fail judgment result PASS / FAIL is directly output from the reference table 80. Show the case.
[0048]
In this example, the reference phase number RN0 is input to the memory constituting the reference table 80 at the X address, and each data phase number DN0 is input to the Y address of the memory.
FIG. 8A is a table showing the difference between the data phase number DN0 and the reference phase number RN0. In the table shown in FIG. 8A, when the user wants to determine, for example, −2 to +2 as good, the reference table 80 indicates a path to storage cells in the range of −2 to +2 as shown in FIG. 6B. P is stored, and F representing failure is stored in the other memory cells.
[0049]
By storing in this way, the X address reference phase number RNO is applied, and by applying the data phase number DNO to the Y address, the path P is read for the phase difference falling within the range of -2 to +2. For other phase differences, the failure F is read out, and the quality is determined.
[0050]
【The invention's effect】
As described above, according to the present invention, the phase difference between the generation timing of the reference clock and each data is measured in real time to determine whether the phase difference is within a predetermined range or faster or slower than the reference clock. Since the quality can be determined, the test can be completed by generating only one round of the test pattern from the start to the end. As a result, there is an advantage that the test can be completed in a shorter time than before.
Further, by storing each output value of the phase comparison unit 60 in a memory or the like from the start to the end of the test, there is an advantage that the fluctuation of the phase difference between the data and the reference clock, jitter, or the like can be analyzed.
[Brief description of the drawings]
FIG. 1 is a block diagram for explaining one embodiment of the present invention.
FIG. 2 is a diagram for explaining the operation of FIG. 1;
3 is a block diagram showing an example of a specific circuit structure of a phase comparison unit shown in FIG.
4 is a timing chart for explaining the operation of the phase comparison unit shown in FIG. 3;
FIG. 5 is a view similar to FIG.
6 is a block diagram for explaining a circuit structure of the pass / fail determination means shown in FIG. 1. FIG.
FIG. 7 is a block diagram for explaining a modified embodiment of the present invention.
8 is a diagram showing an example of an internal configuration of a reference table shown in FIG.
FIG. 9 is a block diagram for explaining an outline of a conventional semiconductor device test apparatus.
FIG. 10 is a timing chart illustrating an operation of a semiconductor device that generates a reference clock in synchronization with a data read output.
11 is a timing chart for explaining how jitter occurs in a reference clock output from the semiconductor device described in FIG. 10;
FIG. 12 is a block diagram for explaining a level comparator and a signal reading circuit for determining whether a read signal is good or bad in the semiconductor device test apparatus.
13 is a timing chart for explaining a method of measuring the generation timing of a read signal in the conventional semiconductor device test apparatus shown in FIG.
FIG. 14 is a block diagram for explaining the technical content of a prior application.
15 is a timing chart for explaining the operation of the prior application shown in FIG. 14;
16 is a timing chart for explaining the operation of the prior application shown in FIG. 14;
FIG. 17 is a block diagram for explaining the operation of the comparison determination means used in the embodiment of the prior application shown in FIG. 14;
18 is a diagram for explaining the operation of the conversion means used in the embodiment of the prior application shown in FIG. 14;
19 is a block diagram for explaining the structure of the timing selection circuit shown in FIG. 14;
FIG. 20 is a block diagram showing a modification of the multiphase pulse generator in the prior art.
[Explanation of symbols]
10 level comparator
30 Multi-phase pulse generator
31D data phase number conversion means
31R Reference phase number conversion means
40 Signal reading circuit
50 comparison judgment means
60 Phase comparator
70 Pass / fail judgment means
71 Spec setting device
80 reference table

Claims (8)

A test method for a semiconductor device that outputs a reference clock and a plurality of data synchronized with the reference clock according to a test pattern,
Over the entire test cycle of the test pattern, within each test cycle, a multiphase pulse with a slight phase difference from a predetermined phase position is generated,
Within each test cycle, a plurality of data and a reference clock each sampled with strobe pulse comprised by the multi-phase pulse of each said plurality of data multiphase sample output and the reference clock that is read from the semiconductor device under test Multiphase sample output of
In the multiphase sample output of each of the above data, the sample output that has changed between the sample outputs of adjacent phases is detected, and the generation phase of the strobe pulse that samples the sample output that has changed is determined. A sample that is obtained as a timing phase of the rising or falling edge of data and detects the sample output that has changed between the sample outputs of adjacent phases within the multi-phase sample output of the reference pulse, and has caused the change Obtain the generation phase of the strobe pulse that sampled the output as the rising or falling timing phase of the reference clock,
Obtain the phase difference between the rising or falling timing phase of each obtained data and the rising or falling timing phase of the reference clock,
A method for testing a semiconductor device, comprising: determining whether the semiconductor device under test is good or not based on whether or not the phase difference is within a predetermined range. Semiconductor device testing method smell of claim 1 wherein Te,
Defined phase number of strobe pulses detecting a change point of the sample output reference clock, and a phase number of the detected strobe pulse the changing point of the sample outputs of the respective data and reference clock phase and the respective data phase, the A semiconductor device testing method comprising: determining whether a semiconductor device under test is good or not based on whether or not a phase number difference value is within a predetermined range. Semiconductor device testing method smell of claim 1 wherein Te,
Access the phase number of the strobe pulse detects a change point of the sample output of the reference clock, the reference table by each of the respective data sample output detected strobe pulse phase number of the change point of the reference table of acceptability A semiconductor device testing method, wherein the determination result is directly read out. A test apparatus for a semiconductor device that outputs a reference clock and a plurality of data synchronized with the reference clock in each test cycle over the entire test cycle of the test pattern,
A, within each test cycle, a multi-phase pulse generator that generates a multi-phase pulse sequentially given a minute time difference from a predetermined phase position in a phase order corresponding to the time difference;
B, and a plurality of signal reading means provided corresponding to said plurality of data to the semiconductor device under test outputs in each test cycle, the signal reading means each to each phase of the multiphase pulse provided corresponding comprise a signal reading circuit for multiple applied to a corresponding strobe pulse to pulse phase, a plurality of signal read circuit for each signal reading means receives the corresponding data in parallel, it is applied A plurality of signal reading means for sampling at the generation timing in the phase sequence by the strobe pulse of each phase and outputting a sample output of the data, thereby outputting each sample output of the plurality of data in parallel ;
C , reference clock signal reading means provided corresponding to the reference clock output in each test cycle by the semiconductor device under test, provided corresponding to each phase of the multiphase pulse, And a plurality of reference clock signal reading circuits applied as strobe pulses, the plurality of reference clock signal reading circuits receiving the reference clocks in parallel, and applying the applied strobe of each phase. A reference clock signal reading means for sampling at a generation timing in the above-mentioned phase order by a pulse and outputting a sample output of the reference clock ; and
D, a plurality of comparison and determination means provided corresponding to the multiple signal reading means, the comparison determination means provided corresponding to a plurality of signal read circuit of the corresponding signal reading means A plurality of comparison / determination circuits including a plurality of comparison / determination circuits compare and determine whether the level of the sample output of the data received from the corresponding signal reading circuit matches the expected value. The comparison / determination result is output to the comparison / determination circuit at the subsequent stage of the phase number of the next phase of the multi-phase pulse. It is determined that only the comparison determination circuit that has detected the effective determination result is output, and the strobe pulse of the phase that has issued the effective determination result captures the rising or falling change point of the data, This A plurality of comparison determination means for detecting the rising or falling change points of the plurality of data thereby,
E, reference clock comparison / determination means provided corresponding to the reference clock signal reading means, and a plurality of reference clocks provided corresponding to the plurality of reference clock signal reading circuits, respectively. A plurality of reference clock comparison / determination circuits, wherein the reference clock multi-phase sample output level received from the corresponding reference clock signal reading circuit matches the expected value. The comparison determination result is output to the comparison determination circuit for the reference clock at the subsequent stage of the number after the phase order of the multi-phase pulse, and the comparison determination circuit for each reference clock determines its own comparison determination. The result is compared with the comparison determination result of each preceding stage, and the determination result that is valid is output only from the comparison determination circuit for the reference clock that has detected the mismatch, and the determination result that is valid is issued Strobe pulse of the comparison and determination means for determining the reference clock and that captures the change point of the rising or falling edge of the reference clock,
F, the output bit position determination result that the effective comparison judgment unit for the reference clock is output, the change point of the reference clock is converted into phase number of the detected strobe pulse, a reference phase as a reference phase number which Number conversion means;
G, provided corresponding to the comparison and determination means of the multiple, the output bit position determination result that the effective of comparison decision means corresponding is output, the phase number of the strobe pulse detects a change point of the data a plurality of data phase number conversion means converts each of them with data phase number,
H, means for determining the acceptability of a semiconductor device under test and a respective data phase number which the reference phase number conversion means is converted reference phase number and the plurality of data phase number conversion unit is converted,
A semiconductor device testing apparatus characterized by comprising: The semiconductor device test apparatus according to claim 4,
The quality determining means includes one address of the reference phase number input has the other address for input each data phase number, the memory cells determined by these two addresses, input reference phase number and the data phase number And P representing the path is stored only in the memory cells having the desired range of the phase number difference values, and F representing the failure in the other memory cells. Including a reference table configured by a memory that stores the reference phase number, the reference phase number is input to one address from the reference phase number conversion means, and the data phase number is input to the other address from a plurality of data phase number conversion means is, the semiconductor device is referred to the storage cell that is determined by these two addresses, which reference table by the output as quality determination result of each data from the referenced memory cells, characterized in that Test equipment. The semiconductor device test apparatus according to claim 4,
  A plurality of phase comparison units provided corresponding to the plurality of data phase number conversion means, respectively;
  Each of the plurality of phase comparison units includes a digital subtractor that subtracts the data phase number output from the corresponding data phase number conversion means and the reference phase number output from the reference phase number conversion means,
  The means for determining pass / fail of the semiconductor device under test includes a plurality of pass / fail determination means provided corresponding to the plurality of phase comparison sections, respectively. The pass / fail determination means are first and second subtractors, first In each pass / fail judgment means, the first subtracter subtracts the subtraction result output from the corresponding phase comparison unit and the upper limit specification value, and the second subtracter corresponds. Subtraction is performed between the subtraction result output from the phase comparison unit and the lower limit specification value, and the first encoder outputs an encoding output of 0 or 1 depending on whether the subtraction output of the first subtractor is positive or negative, and the second encoder Outputs an encoded output of 0 or 1 depending on whether the subtracted output of the second subtractor is positive or negative, and an OR gate ORs the outputs of the first and second encoders, and determines whether it is good or not based on 0 or 1 Give the result The semiconductor device testing apparatus, characterized by. In the semiconductor device testing apparatus according to claim 4 -6,
The multi-phase pulse generating means is composed of a plurality of delay elements having slightly different delay times, and is configured to generate a multi-phase pulse having a slight phase difference by applying a pulse to the plurality of delay elements. A semiconductor device testing apparatus. In the semiconductor device testing apparatus according to claim 4 -6,
A semiconductor device testing apparatus characterized in that a multiphase pulse generating means continuously connects a plurality of delay elements having the same delay time and obtains a multiphase pulse from each connection point of the plurality of cascaded delay elements. .

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