WO2007038233A3 - Strobe technique for test of digital signal timing - Google Patents

Strobe technique for test of digital signal timing Download PDF

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Publication number
WO2007038233A3
WO2007038233A3 PCT/US2006/036912 US2006036912W WO2007038233A3 WO 2007038233 A3 WO2007038233 A3 WO 2007038233A3 US 2006036912 W US2006036912 W US 2006036912W WO 2007038233 A3 WO2007038233 A3 WO 2007038233A3
Authority
WO
WIPO (PCT)
Prior art keywords
signal
clock
word
test
edge time
Prior art date
Application number
PCT/US2006/036912
Other languages
French (fr)
Other versions
WO2007038233A2 (en
Inventor
Ronald A Sartschev
Ernest P Walker
Original Assignee
Teradyne Inc
Ronald A Sartschev
Ernest P Walker
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/234,599 external-priority patent/US7573957B2/en
Priority claimed from US11/234,814 external-priority patent/US7574632B2/en
Priority claimed from US11/234,542 external-priority patent/US7856578B2/en
Application filed by Teradyne Inc, Ronald A Sartschev, Ernest P Walker filed Critical Teradyne Inc
Priority to EP06804013A priority Critical patent/EP1927203A2/en
Priority to KR1020087006518A priority patent/KR101236769B1/en
Priority to JP2008532401A priority patent/JP5254794B2/en
Publication of WO2007038233A2 publication Critical patent/WO2007038233A2/en
Publication of WO2007038233A3 publication Critical patent/WO2007038233A3/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31937—Timing aspects, e.g. measuring propagation delay
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
    • G01R31/31726—Synchronization, e.g. of test, clock or strobe signals; Signals in different clock domains; Generation of Vernier signals; Comparison and adjustment of the signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56004—Pattern generation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56012—Timing aspects, clock generation, synchronisation

Abstract

A test system timing method simulates the timing of a synchronous clock on the device under test. Strobe pulses can be generated by routing an edge generator to delay elements with incrementally increasing delay values. A data signal or synchronous clock signal can be applied to the input of each of a set of latches which are clocked by the strobe pulses. An encoder can convert the series of samples which are thereby latched to a word representing edge time and polarity of the sampled signal. If the sampled signal is a data signal, the word can be stored in memory. If the sampled signal is a clock signal, the word is routed to a clock bus and used to address the memory. The difference between clock edge time and data edge time is provided and can be compared against expected values.
PCT/US2006/036912 2005-09-23 2006-09-22 Strobe technique for test of digital signal timing WO2007038233A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP06804013A EP1927203A2 (en) 2005-09-23 2006-09-22 Strobe technique for test of digital signal timing
KR1020087006518A KR101236769B1 (en) 2005-09-23 2006-09-22 Strobe technique for test of digital signal timing
JP2008532401A JP5254794B2 (en) 2005-09-23 2006-09-22 Strobe technique for testing the timing of digital signals

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US11/234,814 2005-09-23
US11/234,599 US7573957B2 (en) 2005-09-23 2005-09-23 Strobe technique for recovering a clock in a digital signal
US11/234,814 US7574632B2 (en) 2005-09-23 2005-09-23 Strobe technique for time stamping a digital signal
US11/234,542 2005-09-23
US11/234,542 US7856578B2 (en) 2005-09-23 2005-09-23 Strobe technique for test of digital signal timing
US11/234,599 2005-09-23

Publications (2)

Publication Number Publication Date
WO2007038233A2 WO2007038233A2 (en) 2007-04-05
WO2007038233A3 true WO2007038233A3 (en) 2008-10-30

Family

ID=37900290

Family Applications (3)

Application Number Title Priority Date Filing Date
PCT/US2006/037099 WO2007038339A2 (en) 2005-09-23 2006-09-22 Strobe technique for recovering a clock in a digital signal
PCT/US2006/037100 WO2007038340A2 (en) 2005-09-23 2006-09-22 Strobe technique for time stamping a digital signal
PCT/US2006/036912 WO2007038233A2 (en) 2005-09-23 2006-09-22 Strobe technique for test of digital signal timing

Family Applications Before (2)

Application Number Title Priority Date Filing Date
PCT/US2006/037099 WO2007038339A2 (en) 2005-09-23 2006-09-22 Strobe technique for recovering a clock in a digital signal
PCT/US2006/037100 WO2007038340A2 (en) 2005-09-23 2006-09-22 Strobe technique for time stamping a digital signal

Country Status (4)

Country Link
EP (3) EP1927204A2 (en)
JP (3) JP5254794B2 (en)
KR (3) KR101236769B1 (en)
WO (3) WO2007038339A2 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7573957B2 (en) 2005-09-23 2009-08-11 Teradyne, Inc. Strobe technique for recovering a clock in a digital signal
US7574632B2 (en) 2005-09-23 2009-08-11 Teradyne, Inc. Strobe technique for time stamping a digital signal
US7856578B2 (en) 2005-09-23 2010-12-21 Teradyne, Inc. Strobe technique for test of digital signal timing
CN102356594B (en) * 2009-04-30 2015-03-25 爱德万测试株式会社 Clock generating apparatus, testing apparatus and clock generating method
WO2010131286A1 (en) * 2009-05-11 2010-11-18 株式会社アドバンテスト Reception device, test device, reception method, and test method
JPWO2011033589A1 (en) * 2009-09-18 2013-02-07 株式会社アドバンテスト Test apparatus and test method
US8554514B2 (en) 2009-09-18 2013-10-08 Advantest Corporation Test apparatus and test method
WO2014108742A1 (en) * 2013-01-09 2014-07-17 Freescale Semiconductor, Inc. Method and apparatus for sampling a signal
US9279857B2 (en) 2013-11-19 2016-03-08 Teradyne, Inc. Automated test system with edge steering
KR101738005B1 (en) 2016-06-10 2017-05-19 (주)제이케이아이 Logic analyzer
US10733345B1 (en) * 2018-08-23 2020-08-04 Cadence Design Systems, Inc. Method and system for generating a validation test

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3997740A (en) * 1975-05-30 1976-12-14 Bell Telephone Laboratories, Incorporated Pulse train analyzer
US4989202A (en) * 1988-10-14 1991-01-29 Harris Corporation ISDN testing device and method
US5084669A (en) * 1990-03-08 1992-01-28 Telefonaktiebolaget L M Ericsson Direct phase digitization
US5483534A (en) * 1992-05-29 1996-01-09 Nec Corporation Transmitting system having transmitting paths with low transmitting rates
US5499190A (en) * 1992-01-16 1996-03-12 Hamamatsu Photonics K.K. System for measuring timing relationship between two signals
US6173207B1 (en) * 1997-09-22 2001-01-09 Agilent Technologies, Inc. Real-time control system with non-deterministic communication
US6198700B1 (en) * 1999-06-04 2001-03-06 Level One Communications, Inc. Method and apparatus for retiming test signals
US6204710B1 (en) * 1998-06-22 2001-03-20 Xilinx, Inc. Precision trim circuit for delay lines
US6285722B1 (en) * 1997-12-05 2001-09-04 Telcordia Technologies, Inc. Method and apparatus for variable bit rate clock recovery

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5446650A (en) * 1993-10-12 1995-08-29 Tektronix, Inc. Logic signal extraction
US5526286A (en) * 1994-02-16 1996-06-11 Tektronix, Inc. Oversampled logic analyzer
JP4495308B2 (en) * 2000-06-14 2010-07-07 株式会社アドバンテスト Semiconductor device testing method and semiconductor device testing equipment
JP2002196053A (en) * 2000-12-25 2002-07-10 Ando Electric Co Ltd Ic measurement device
US7233164B2 (en) * 2003-12-17 2007-06-19 Rambus Inc. Offset cancellation in a multi-level signaling system

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3997740A (en) * 1975-05-30 1976-12-14 Bell Telephone Laboratories, Incorporated Pulse train analyzer
US4989202A (en) * 1988-10-14 1991-01-29 Harris Corporation ISDN testing device and method
US5084669A (en) * 1990-03-08 1992-01-28 Telefonaktiebolaget L M Ericsson Direct phase digitization
US5499190A (en) * 1992-01-16 1996-03-12 Hamamatsu Photonics K.K. System for measuring timing relationship between two signals
US5483534A (en) * 1992-05-29 1996-01-09 Nec Corporation Transmitting system having transmitting paths with low transmitting rates
US6173207B1 (en) * 1997-09-22 2001-01-09 Agilent Technologies, Inc. Real-time control system with non-deterministic communication
US6285722B1 (en) * 1997-12-05 2001-09-04 Telcordia Technologies, Inc. Method and apparatus for variable bit rate clock recovery
US6204710B1 (en) * 1998-06-22 2001-03-20 Xilinx, Inc. Precision trim circuit for delay lines
US6198700B1 (en) * 1999-06-04 2001-03-06 Level One Communications, Inc. Method and apparatus for retiming test signals

Also Published As

Publication number Publication date
WO2007038340A2 (en) 2007-04-05
JP4907663B2 (en) 2012-04-04
JP2009510403A (en) 2009-03-12
WO2007038339A3 (en) 2007-12-06
WO2007038340A3 (en) 2007-11-22
EP1927203A2 (en) 2008-06-04
KR101237878B1 (en) 2013-02-27
KR20080047403A (en) 2008-05-28
JP2009510842A (en) 2009-03-12
KR20080048487A (en) 2008-06-02
WO2007038339A2 (en) 2007-04-05
KR101239743B1 (en) 2013-03-06
KR20080045714A (en) 2008-05-23
JP2009509174A (en) 2009-03-05
KR101236769B1 (en) 2013-02-25
EP1927204A2 (en) 2008-06-04
EP1927210A2 (en) 2008-06-04
JP5254794B2 (en) 2013-08-07
JP5254795B2 (en) 2013-08-07
WO2007038233A2 (en) 2007-04-05

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