CN1767390A - Multipath clock detecting device - Google Patents
Multipath clock detecting device Download PDFInfo
- Publication number
- CN1767390A CN1767390A CN 200410086136 CN200410086136A CN1767390A CN 1767390 A CN1767390 A CN 1767390A CN 200410086136 CN200410086136 CN 200410086136 CN 200410086136 A CN200410086136 A CN 200410086136A CN 1767390 A CN1767390 A CN 1767390A
- Authority
- CN
- China
- Prior art keywords
- clock
- unit
- signal
- latch
- door
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention discloses a multi-path clock detester which comprises: a clock receiving unit, a multi-path multi-speed clock detecting unit, a detecting result processing unit, a reference clock unit and a control interface unit, wherein the reference clock unit is used to receive the detected clock signal and change the level interface and the voltage breadth of the detected signal; the detecting result processing unit is used to finish the lock, output and indicate of the detecting result; the reference clock unit is used to provide a reference clock signal to the multi-path multi-speed clock detecting unit; the control interface unit is used to generate the corresponding break signal to the upper position controller and receive the control of the upper position controller to finish the reset and disinfect of the multi-path multi-speed clock detecting unit; the multi-path multi-speed clock detecting unit is formed by a plurality of clock detecting circuits to finish the detect of the multi-path detecting clock with different speed.
Description
Technical field
The present invention relates to the clock test of the communications field, specifically, relate to a kind of device of realizing many speed of multichannel clock detection.
Background technology
In telecommunication system, the clock that the clock unit of many systems or clock board all can externally be exported the multichannel different rates uses for other system and veneer, when these systems were tested, the exist situation and the performance index of its output clock all were the projects that must test usually.On the other hand, clock in the communication system also produces temporary transient losing (clock temporarily lose show as clock signal present single high level or low level) sometimes, in many application scenarios, in case clock generating is lost, will bring for whole system and seriously influence, so must carry out real-time monitoring clock.
On routine techniques is realized, can use monostable flipflop (as 74HC123 etc.) that continuous clock signal is carried out pulse missing detects, the clock signal consecutive hours, monostable flipflop is triggered always, remain on high level, in case the continuous several pulse missings of clock signal, monostable flipflop just produces alarm signal.If a system need carry out pulse missing to a plurality of clocks and detect, just need a plurality of monostable flipflops, this will consume many circuit resources, simultaneously because the number of the continuous pulse-losing that it can detect is the parameter setting by outward element, and this parameter adjustment inconvenience of getting up.
Chinese patent 99127039.8 (" a kind of clock signal pulse missing detecting circuit ", Bei'er Co., Ltd., Shanghai) realized a kind of clock signal pulse missing detecting circuit by logical circuits such as trigger, comparator, counters, but this circuit adopts the circuit of method of counting detection loss of clock the same with other, requires the frequency of counting clock signal must be higher than the measured clock signal.When the measured clock frequency is higher, detect the bottleneck that circuit is realized that is selected to of frequency like this, the cost of realization is also very high.
Summary of the invention
Purpose of the present invention is exactly the device that proposes that a kind of reference clock frequency requirement is lower, cost is lower and can detect many speed of multichannel clock simultaneously.
A kind of multipath clock detecting device comprises clock receiving element 101, many speed of multichannel clock detection unit 102, testing result processing unit 103, reference clock unit 104 and control interface unit 105; Described clock receiving element 101 is used to receive the measured clock signal and the measured clock signal is carried out electric level interface and voltage amplitude conversion; Described testing result processing unit 103 is used to finish latching, export and indicating of testing result; Described reference clock unit 104 provides a reference clock signal to output to many speed of multichannel clock detection unit 102; Described control interface unit 105 is used to finish to upper control machine and produces corresponding interrupt signal, receives the control of upper control machine simultaneously, finishes resetting and remove many speed of multichannel clock detection unit 102; Described many speed of multichannel clock detection unit 102 is made of the several clock detection circuit, finishes the detection to the multichannel measured clock of different rates.
Each road clock detection circuit in above-mentioned many speed of multichannel clock detection unit 102 comprises or door A301, or door B304, counter 302, comparator 303, edge triggered flip flop 305 and latch 306; Pulse reference clock behind 302 pairs of processes of described counter or the door A301 is counted; Described measured clock through or door B304 and enter edge triggered flip flop 305 and handle the back and remove end generation erase pulse continuously at counter 302; The count value of described counter 302 outputs to comparator 303 and compares with the value of presetting, and the output result of comparator 303 send latch 306 to latch, and described or door A301 carries out with the output result reference clock signal or operates; Described or door B304 carries out the signal in measured clock signal and the latch 306 or operates; Described latch 306 is accepted the control of the control clear signal of control interface unit 105 outputs.
The device that uses the present invention to propose, can the multipath clock of different rates be detected simultaneously, and because the reference clock frequency that each road clock detection circuit needs is less than or equal to the frequency of tested clock, avoid high-frequency to detect the problem that clock is difficult to obtain, reduced the circuit cost of whole detection device.
Description of drawings
Fig. 1 is the principle assumption diagram of the checkout gear that proposes of the present invention;
Fig. 2 is the modular structure figure that the present invention proposes the embodiment of device;
Fig. 3 is the principle assumption diagram of single channel clock detection circuit among the present invention;
Fig. 4 is the circuit diagram of the single channel clock detection that realizes in programmable logic device;
Fig. 5 is the clock detection logical simulation schematic diagram of the circuit among Fig. 4.
Embodiment
The present invention is described in further detail below in conjunction with drawings and Examples.
Fig. 1 is the principle assumption diagram of the checkout gear that proposes of the present invention, as shown in Figure 1, and the multipath clock detecting device that the present invention proposes, comprise clock receiving element 101, many speed of multichannel clock detection unit 102, testing result processing unit 103, reference clock unit 104 and control interface unit 105; Described clock receiving element 101 is used to receive the measured clock signal and the measured clock signal is carried out electric level interface and voltage amplitude conversion; Described testing result processing unit 103 is used to finish latching, export and indicating of testing result; Described reference clock unit 104 provides a reference clock signal to output to many speed of multichannel clock detection unit 102; Described control interface unit 105 is used to finish to upper control machine and produces corresponding interrupt signal, receives the control of upper control machine simultaneously, finishes resetting and remove many speed of multichannel clock detection unit 102; Make the work of testing apparatus continuity ground.Described many speed of multichannel clock detection unit 102 is made of the several clock detection circuit, and it is the core of checkout gear, finishes the detection to the multichannel measured clock of different rates.
Fig. 2 is the modular structure figure that the present invention proposes the embodiment of device, as shown in Figure 2, on the basis of Fig. 1, clock detection unit 102 further comprises single-ended clock receiving element 201, be used to receive the clock level of TTL or CMOS form, and differential clocks receiving element 202, be used for receiving the clock level of the common LVDS of communication system (low-voltage differential signal) form, after handling, the differential received chip synthesizes single-ended clock level.Unit 201 and Unit 202 constitute the clock receiving unit of checkout gear jointly, receive the measured clock that external clock unit or clock board are sent here, and the clock signal of each form can receive 4 the tunnel, can also increase as required again.Testing result processing unit 103 specifically comprises testing result latch units 205, is used for the testing result of each road clock is kept at latch; Indicating member 203, the form of its employing LED light is indicated the test result of each road clock intuitively.With output unit 204 as a result, be used for test result is outputed to upper control machine.Reference clock unit 104 is produced behind the EPLD frequency division by crystal oscillator on this device, is set to 8K or 2M clock, can also revise divide ratio as required, provides other suitable reference clocks to use for the clock detection unit.
Fig. 3 is the principle assumption diagram of single channel clock detection circuit among the present invention, and as shown in Figure 3, each road clock detection circuit comprises or door A301, or door B304, counter 302, comparator 303, edge triggered flip flop 305 and latch 306; Pulse reference clock behind 302 pairs of processes of described counter or the door A301 is counted; Described measured clock through or door B304 and enter edge triggered flip flop 305 and handle the back and remove end generation erase pulse continuously at counter 302; The count value of described counter 302 outputs to comparator 303 and compares with the value of presetting, and the output result of comparator 303 send latch 306 to latch, and described or door A301 carries out with the output result reference clock signal or operates; Described or door B304 carries out the signal in measured clock signal and the latch 306 or operates; Described latch 306 is accepted the control of the control clear signal of control interface unit 105 outputs.Its operation principle is as follows: the pulse reference clock behind 302 pairs of processes of counter or the door A302 is counted, if measured clock exists, measured clock is removed end at counter 302 and is produced erase pulse continuously after edge triggered flip flop 305 is handled, the count value of counter 302 does not reach the set point of comparator 303 forever like this, thereby testing result output perseverance is a low level.If measured clock does not exist or recurs pulse missing, then counter 302 is removed end and can not be produced clear signal, thereby the step-by-step counting of 302 pairs of reference clocks of counter reaches the set point of comparator 303, and testing result is output as high level, and the expression measured clock does not exist or pulsing is lost.Testing result is delivered to latch 306 simultaneously and is latched, and just can detect after must being removed by the control clear signal of control interface unit 105 outputs next time.
Circuit among Fig. 3 can be used as a circuit module and is embedded in the veneer circuit, carries out clock supervision real-time on the veneer.This circuit is realized in programmable logic device, can realize the detection of multipath clock in a slice programmable logic device, and Fig. 4 is the circuit diagram of the single channel clock detection that realizes in programmable logic device.As shown in Figure 4, reference clock signal REFCLK through or deliver to the CLK end of counter acount2 behind the door.TESTCLK is a measured clock, and its passes through or deliver to behind the door the input of an edge triggered flip flop edge, and the output of edge triggered flip flop edge is delivered to the CLR end of counter acount2 again.In this circuit diagram, comparator circuit is realized with door AND2 by two inputs, when the count value of counter reaches 3, with gate output terminal (testing result CLKLOS) be 1, the expression measured clock does not exist or clock pulse is temporarily lost, when the count value of counter is 0,1 or 2, with gate output terminal be 0.Because the frequency of the reference clock REFCLK that we select is less than or equal to the frequency of measured clock (if the frequency of measured clock signal is very low, for fear of adopting low reference clock frequency, can in circuit, exchange processing to measured clock and reference clock), what measured clock did not stop after edge triggered flip flop is handled produces clear signal at counter CLR end, thereby the count value of counter does not reach 3.If measured clock does not exist or produces temporary transient pulse missing, when totally having produced rising edge pulse more than 3, reference clock also do not have clear signal to arrive, comparator this moment (with door) action, output high level.
Fig. 5 is the clock detection logical simulation schematic diagram of the circuit among Fig. 4.As shown in Figure 5, the meaning of each waveform is among the figure: waveform 1 is reference clock REFCLK, and waveform 2 is measured clock TESTCLK, and waveform 3 is the testing result CLKLOS of measured clock, and waveform 4 is testing result clear signal CPURST.From logical simulation figure, can be clearly seen that, do not change and (permanently be high level or low level when measured clock at 3 rising edges of reference clock level took place in the pulse period, among Fig. 5 low level), then testing result CLKLOS becomes high level at once, and have only after the CPURST signal carries out zero clearing to testing result, CLKLOS just becomes low level, can begin to detect next time.It can also be seen that from analogous diagram, if measured clock is detected more accurately, checkout gear can detect immediately when promptly losing a spot of several pulse signal, will select the reference clock source approaching with the measured clock frequency so for use, the counting figure place of unison counter and the activation threshold value of comparator also influence the precision of detection.
In the clock test of telecommunication system, consider testing efficiency, for several clock from same clock buffer chip or the output of EPLD logical circuit, usually only need test more accurately road clock wherein, to the clock on other roads, only need test whether clock signal to be arranged, the clock detecting device that adopts this patent to propose, as long as select a suitable reference clock, just can have or not detection simultaneously to the clock of other many roads different rates.
Claims (7)
1, a kind of multipath clock detecting device is characterized in that comprising clock receiving element (101), many speed of multichannel clock detection unit (102), testing result processing unit (103), reference clock unit (104) and control interface unit (105); Described clock receiving element (101) is used to receive the measured clock signal and the measured clock signal is carried out electric level interface and voltage amplitude conversion; Described testing result processing unit (103) is used to finish latching, export and indicating of testing result; Described reference clock unit (104) provides a reference clock signal to output to many speed of multichannel clock detection unit (102); Described control interface unit (105) is used to finish to upper control machine and produces corresponding interrupt signal, receives the control of upper control machine simultaneously, finishes resetting and remove many speed of multichannel clock detection unit (102); Described many speed of multichannel clock detection unit (102) is made of the several clock detection circuit, finishes the detection to the multichannel measured clock of different rates.
2, device according to claim 1, it is characterized in that: each the road clock detection circuit in described many speed of multichannel clock detection unit (102) comprises or door A (301), or door B (304), counter (302), comparator (303), edge triggered flip flop (305) and latch (306); Described counter (302) to through or door A (301) after pulse reference clock count; Described measured clock through or door B (304) and enter edge triggered flip flop (305) and handle the back and remove end generation erase pulse continuously at counter (302); The count value of described counter (302) outputs to comparator (303) and compares with the value of presetting, and the output result of comparator (303) send latch (306) to latch, and described or door A (301) carries out with the output result reference clock signal or operates; Described or door B (304) carries out the signal in measured clock signal and the latch (306) or operates; Described latch (306) is accepted the control of the control clear signal of control interface unit (105) output.
3, device according to claim 1 and 2, it is characterized in that described clock detection unit (102) comprises single-ended clock receiving element (201), be used to receive the clock level of TTL or CMOS form, and differential clocks receiving element (202), be used to receive the clock level of low-voltage differential signal form.
4, device according to claim 1 and 2 is characterized in that described testing result processing unit (103) specifically comprises testing result latch units (205), is used for the testing result of each road clock is kept at latch; Indicating member (203) is used for indicating intuitively the test result of each road clock; With output unit (204) as a result, be used for test result is outputed to upper control machine.
5, device according to claim 1 and 2 is characterized in that described reference clock unit (104) produces reference clock signal by crystal oscillator behind the EPLD frequency division.
6, device according to claim 4 is characterized in that described indicating member (203) adopts LED light to realize.
7, device according to claim 2 is characterized in that described circuit can realize in programmable logic device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100861365A CN1309169C (en) | 2004-10-27 | 2004-10-27 | Multipath clock detecting device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100861365A CN1309169C (en) | 2004-10-27 | 2004-10-27 | Multipath clock detecting device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1767390A true CN1767390A (en) | 2006-05-03 |
| CN1309169C CN1309169C (en) | 2007-04-04 |
Family
ID=36743035
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100861365A Active CN1309169C (en) | 2004-10-27 | 2004-10-27 | Multipath clock detecting device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1309169C (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103197139A (en) * | 2012-01-06 | 2013-07-10 | 上海华虹集成电路有限责任公司 | Clock frequency test method and clock frequency test circuit |
| CN101826871B (en) * | 2009-03-03 | 2015-12-09 | 瑞昱半导体股份有限公司 | Frequency detecting device and method |
| CN105391448A (en) * | 2015-12-07 | 2016-03-09 | 中国航空工业集团公司西安航空计算技术研究所 | Method for detecting correctness of differential clock frequency in real time |
| CN105807134A (en) * | 2014-12-31 | 2016-07-27 | 无锡华润矽科微电子有限公司 | Frequency tester and frequency test system |
| CN105892560A (en) * | 2016-03-29 | 2016-08-24 | 杭州和利时自动化有限公司 | Clock detection method and system used for embedded system |
| CN104076263B (en) * | 2013-03-28 | 2017-03-15 | 致茂电子(苏州)有限公司 | The measuring time value module of semiconductor ATE and method |
| CN109004920A (en) * | 2018-05-29 | 2018-12-14 | 苏州大学 | A kind of novel signal failing edge edge sense circuit |
| CN109412581A (en) * | 2017-08-18 | 2019-03-01 | 杭州晶华微电子有限公司 | A kind of clock failure of oscillation detection circuit |
| CN109543811A (en) * | 2018-10-31 | 2019-03-29 | 上海希路智能科技有限公司 | A kind of counting circuit, method of counting and chip |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5903748A (en) * | 1997-08-18 | 1999-05-11 | Motorola Inc. | Method and apparatus for managing failure of a system clock in a data processing system |
| TW538597B (en) * | 1998-03-31 | 2003-06-21 | Fujitsu General Co Ltd | Phase lock loop circuit |
| CN1108024C (en) * | 1999-12-29 | 2003-05-07 | 上海贝尔有限公司 | Clock signal switching and selecting method in synchronous clock supply system and its device |
-
2004
- 2004-10-27 CN CNB2004100861365A patent/CN1309169C/en active Active
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101826871B (en) * | 2009-03-03 | 2015-12-09 | 瑞昱半导体股份有限公司 | Frequency detecting device and method |
| CN103197139B (en) * | 2012-01-06 | 2017-03-15 | 上海华虹集成电路有限责任公司 | Clock rate testing circuit |
| CN103197139A (en) * | 2012-01-06 | 2013-07-10 | 上海华虹集成电路有限责任公司 | Clock frequency test method and clock frequency test circuit |
| CN104076263B (en) * | 2013-03-28 | 2017-03-15 | 致茂电子(苏州)有限公司 | The measuring time value module of semiconductor ATE and method |
| CN105807134A (en) * | 2014-12-31 | 2016-07-27 | 无锡华润矽科微电子有限公司 | Frequency tester and frequency test system |
| CN105391448A (en) * | 2015-12-07 | 2016-03-09 | 中国航空工业集团公司西安航空计算技术研究所 | Method for detecting correctness of differential clock frequency in real time |
| CN105391448B (en) * | 2015-12-07 | 2018-04-20 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of method of the differential clocks frequency correctness of detection in real time |
| CN105892560A (en) * | 2016-03-29 | 2016-08-24 | 杭州和利时自动化有限公司 | Clock detection method and system used for embedded system |
| CN109412581A (en) * | 2017-08-18 | 2019-03-01 | 杭州晶华微电子有限公司 | A kind of clock failure of oscillation detection circuit |
| CN109004920A (en) * | 2018-05-29 | 2018-12-14 | 苏州大学 | A kind of novel signal failing edge edge sense circuit |
| CN109004920B (en) * | 2018-05-29 | 2023-08-15 | 苏州大学 | Novel signal falling edge detection circuit |
| CN109543811A (en) * | 2018-10-31 | 2019-03-29 | 上海希路智能科技有限公司 | A kind of counting circuit, method of counting and chip |
| CN109543811B (en) * | 2018-10-31 | 2023-06-16 | 上海希路智能科技有限公司 | Counting circuit, counting method and chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1309169C (en) | 2007-04-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101685135B (en) | Test device and test method for testing circuit board | |
| CN103036670B (en) | A kind of clock recovery circuitry and parallel output circuit | |
| CN1309169C (en) | Multipath clock detecting device | |
| CN108401445A (en) | For the circuit of time of measuring, method and related chip, system and equipment | |
| CN105450215B (en) | A kind of coincidence measurement system and method | |
| CN1948973A (en) | Method and circuit of obtaining wave shape trigger signal of oscilloscope | |
| CN103760759A (en) | Automatic forward/reverse direction IRIG-B code decoding method | |
| CN107112985A (en) | A kind of system and method for detecting dropout | |
| CN102147426A (en) | Broadband triggering circuit of digital oscilloscope | |
| CN108761557A (en) | A kind of chiasma type light curtain detection device based on FPGA | |
| CN103645379A (en) | TTL signal frequency hopping monitoring system and method | |
| CN207440315U (en) | A kind of photoelectric detection system | |
| CN1333529C (en) | Clock signal detection method and apparatus in electronic devices | |
| CN106026982B (en) | A kind of monostable flipflop | |
| CN1395350A (en) | Method for quickly-blanking flutter-identifying dislocation of switch quantity | |
| CN1202616C (en) | High frequency clock pulse loss monitoring detection circuit with low frequency clock | |
| CN105425926B (en) | The controllable reset circuit of asynchronous reset synchronous release bandwidth | |
| CN209559337U (en) | A kind of single photon detection dead time control device | |
| CN104518755A (en) | Digital circuit noise filter and digital filtering method | |
| CN102508140B (en) | Method for realizing pulse check through digital circuit | |
| CN2713741Y (en) | Clock detecting circuit | |
| CN112345820B (en) | High-speed serial signal loss detection circuit | |
| CN108984451A (en) | Signal driving method and communication equipment | |
| CN114064332A (en) | Clock detection method and device and clock safety system | |
| CN106301298A (en) | A kind of telecommunication transmission system and method for communication transmission |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |