CN1108024C - Clock signal switching and selecting method in synchronous clock supply system and its device - Google Patents
Clock signal switching and selecting method in synchronous clock supply system and its device Download PDFInfo
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- CN1108024C CN1108024C CN 99127043 CN99127043A CN1108024C CN 1108024 C CN1108024 C CN 1108024C CN 99127043 CN99127043 CN 99127043 CN 99127043 A CN99127043 A CN 99127043A CN 1108024 C CN1108024 C CN 1108024C
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Abstract
The present invention relates to a clock signal switching and selecting method and a device thereof in a synchronous clock supply system. The device of the method comprises two identical modules which are interconnected to simultaneously operate, and each module comprises a frequency doubling circuit, a phase adjusting circuit and a clock switching and selecting circuit; each frequency doubling circuit receives a signal from the outside and doubles a frequency, and each phase adjusting circuit receives the signal transmitted from each frequency doubling circuit so as to detect the signal and adjust the phase difference between the signals to a very small range and output two adjusted signals and a detection result signal; each clock switching and selecting circuit selects one signal from the two adjusted signals output by the phase adjusting circuit so as to output the signal according to an outside control signal and the detection result signal.
Description
The present invention relates to clock signal switching and selecting method and device thereof in a kind of synchronous clock supply system.
Synchronous clock supply system plays a part very important in communication system, reliable in order to ensure clock signal, and synchronous clock supply system always comprises two primary, spare modules, whole device is operated under the state of Hot Spare.Under the normal condition, have only a module clock signal, be referred to as the master and use module, and another module is called spare module.When the master was taken place with module generation problem or other special circumstances, system need become original master standby with module, and original spare module becomes main using simultaneously.Tend to cause two clock signals to occur in following period of time when occurring in such selection switching and export simultaneously or export without any a signal, these situations all can have a strong impact on the operate as normal of whole communication system.
The object of the present invention is to provide clock signal switching and selecting method and device thereof in a kind of synchronous clock supply system, make and between primary, spare clock signal, to switch rapidly when fortuitous event occurring, have only unique signal output to guarantee device.
In order to realize above-mentioned goal of the invention, the clock signal switching and selecting method in a kind of synchronous clock supply system that is provided, it comprises the following steps: an external reference signal of input is carried out frequency multiplication respectively, produces first frequency-doubled signal and second frequency-doubled signal; First frequency-doubled signal and second frequency-doubled signal are carried out the first phase place adjustment and the second phase place adjustment simultaneously, in a very little scope, and the phase difference of adjusted two output signals of second phase place is also in a very little scope until the phase difference of adjusted two output signals of first phase place; Control signal according to the outside input is respectively selected a signal that derives from first frequency-doubled signal or second frequency-doubled signal as output signal respectively from the first phase place adjustment and adjusted two output signals of second phase place.
In order to realize above-mentioned goal of the invention, clock signal switching selector in a kind of synchronous clock supply system that is provided, it comprises two identical modules of working simultaneously, each module comprises a frequency multiplier circuit, one with the unidirectional phase-adjusting circuit that connects of this frequency multiplier circuit, one with the unidirectional clock switching selecting circuit that connects of this phase-adjusting circuit, two modules link by following mode: each clock switching selecting circuit is interconnected, each phase-adjusting circuit is interconnected, the phase-adjusting circuit of this module also connects with the frequency multiplier circuit of another module is unidirectional, wherein: each frequency multiplier circuit carries out frequency multiplication respectively from outside receiving inputted signal; Each phase-adjusting circuit receives the signal that each frequency multiplier circuit transmits respectively, carries out input and adopts their phase difference of delay line technological adjustment to very little scope, exports adjusted two signals and testing result signal, and they also carry out information interaction simultaneously; Each clock switching selecting circuit is selected an output according to external control signal with from the testing result signal of phase-adjusting circuit from adjusted two signals of this phase-adjusting circuit output, they go back interactive information simultaneously.
Clock signal switching selector in the above-mentioned synchronous clock supply system, wherein, the clock switching selecting circuit comprises: the pulse detection switch unit receives outside pulse detection alarm signal, the output switching command; The module status switch unit receives outside module status index signal, the output switching command; Function control switch unit receives outside function control signal, the output switching command; Clock switches selects control unit, except receiving outside default setting signal, also receive the switching command of above-mentioned three unit output, and the output switching command that receives is carried out priority select, the switching command of first-selected pulse detection switch unit output, next selects the switching command of module status switch unit output, moreover the switching command of selection function control switch unit output, select outside default setting signal at last, export selected signal then; The clock output select unit switches the selection control unit from clock and obtains selected signal, and selects an output from two input clock signals of outside.
Owing to adopted above-mentioned technical solution, make and between primary, spare clock signal, to switch rapidly when fortuitous event occurring to have only unique signal output to guarantee device.
The present invention is further illustrated below in conjunction with drawings and Examples.
Fig. 1 is the circuit structure functional block diagram of clock signal switching selector of the present invention;
Fig. 2 is the circuit structure functional block diagram of the clock switching selecting circuit shown in Fig. 1.
Clock signal switching and selecting method in a kind of synchronous clock supply system of the present invention carries out frequency multiplication respectively to an external reference signal of importing, and produces first frequency-doubled signal and second frequency-doubled signal of 8.192Mhz; First frequency-doubled signal and second frequency-doubled signal to 8.192MHz carry out the first phase place adjustment and the second phase place adjustment simultaneously, in a very little scope, and the phase difference of adjusted two output signals of second phase place is also in a very little scope until the phase difference of adjusted two output signals of first phase place; Control signal according to the outside input is respectively selected a signal that derives from first frequency-doubled signal or second frequency-doubled signal respectively as output signal from the output signal of the first phase place adjustment and adjusted two 8.192MHz of second phase place.
As shown in Figure 1, clock signal switching selector of the present invention comprises two identical modules of working simultaneously 11,22, and each module comprises the clock switching selecting circuit 3 that phase-adjusting circuit 2 that frequency multiplier circuit 1 and this frequency multiplier circuit link and this phase-adjusting circuit link.The connecting mode of two modules is: each phase-adjusting circuit 2 of two modules is interconnected, and each clock switching selecting circuit 3 of two modules is interconnected, and each phase-adjusting circuit 2 links with the frequency multiplier circuit 1 of another module respectively.
The frequency multiplier circuit 1 of above-mentioned two modules is 8.192MHz signal f, f ' with the reference signal Ref frequency multiplication of input, and delivers to the phase-adjusting circuit 2 of two modules respectively; Behind f and the f ' process phase-adjusting circuit 2, the phase difference of output signal F1 and F2 (F1 ' and F2 ') just can (be noted between 0～10ns, F1 and F1 ', F2 and F2 ' are much at one), when switching, output signal just can reduce the phase jitter of clock signal so greatly.Phase-adjusting circuit 2 also carries out the pulse detection warning to signal f, f ' simultaneously, output pulse detection alarm signal P1, P2 (P1 ', P2 '), and deliver to clock and export switching selecting circuit 3, clock output switching selecting circuit 3 produces selected signal C0 and C1 in real time according to a plurality of input control signals, according to selected signal C0, a C1 selection final clock signal Fo of conduct (Fo ') from F1 and F2 (F1 ' and F2 ').From Fig. 1, it can also be seen that between the phase-adjusting circuit 2 of two modules also exchange selected signal C0 and C1 separately mutually, thereby output clock selecting state notifying the other side of this module.Close between selected signal and the selected clock and be: during C0=1, select this module output clock for use; During C1=1, select the output clock of another module for use.Also exchange the input control signal and the pulse detection alarm signal of module separately between the clock switching selecting circuit of two modules mutually, when guaranteeing operate as normal, the C0 of two modules, C1 are opposite each other, thereby guarantee the signal of two modules selection homologies.
As shown in Figure 2, described clock output select circuit module 3 comprises pulse detection switch unit 31, module status switch unit 32, function control switch unit 33, switches selection control unit 34, switches with clock and select the control unit 34 unidirectional output select units that connect 35 with pulse detection switch unit 31, module status switch unit 32 and the function control switch unit 33 unidirectional clocks that connect.Clock output select circuit module 3 receives a plurality of input control signal P1, P2 (P1 ', P2 '), M1, M2 (M1 ', M2 '), S (S '), DS (DS ').P1, P2 (P1 ', P2 ') are the pulse detection alarm signals from phase-adjusting circuit 2, M1, M2 (M1 ', M2 ') are two module operating state index signals, S (S ') is outside function control signal, and DS (DS ') is the default index signal of two modules when default of powering on.Pulse detection switch unit 31 receives pulse detection alarm signal P1, P2 (P1 ', P2 ') after, the output switching command switches to clock selects control unit 34, module status switch unit 32 receives operating state index signal M1, M2 (M1 ', M2 ') after, the output switching command switches to clock selects control unit 34, after function control switch unit 33 receives outside function control signal S (S '), the output switching command switches to clock selects control unit 34, clock switches selects control unit 34 to change selected signal C0 according to following priority orders according to this output switching command, C1, thus make output signal also immediately F1 and F2 (F1 ', F2 ') switch between:
TP top priority be from phase-adjusting circuit module 2 pulse detection alarm signal P1, P2 (P1 ', P2 '), under the normal condition, do not produce pulse detection alarm signal P1, P2 (P1 ', P2 '), thereby allow other input control signal to have an effect.And in case a 8.192MHz signal after the frequency multiplication is arranged, for example signal f breaks down, then this module produces pulse detection alarm signal P1, pulse detection switch unit 31 receives P1, send switching command, clock switches selects control unit 34 to change selected signal C0, C1 at once, and the control output signal is switched between F1 and F2; Another module produces pulse detection alarm signal P2 ', its pulse detection switch unit 31 receives P2 ', send switching command, clock switches selects control unit 34 to change its selected signal at once, the control output signal is switched between F1 ' and F2 ', in this process, it is corresponding that the switching that these two modules take place is selected, and guarantees to select same output signal.When pulse detection switch unit 31 output switching commands, clock switches selects control unit 34 to shield other output switching command automatically;
Inferior priority is module operating state index signal M1, M2 (M1 ', M2 '), when pulse detection switch unit 31 is not exported switching command, if module operating state index signal M1, M2 (M1 ', M2 '), module status switch unit 32 sends switching command, be similar to foregoing description, the output signal change that switches;
When pulse detection alarm signal P1, P2 (P1 ', P2 ') and module operating state index signal M1, M2 (M1 ', M2 ') are default, can also change output signal by outside function control signal S (S ');
When system just powers on, pulse detection alarm signal P1, P2 (P1 ', P2 '), module operating state index signal M1, M2 (M1 ', M2 '), outside function control signal S (S ') signal all are in default setting, and this moment, the default index signal DS (DS ') of two modules when default of powering on was depended in the output of two modules.
The clock signal of the present invention's design is switched the selection implementation and is mainly realized by hardware, has guaranteed speed and the reliability switched.
Claims (3)
1. the clock signal switching and selecting method in the synchronous clock supply system is characterized in that it comprises the following steps:
External reference signal to input carries out frequency multiplication respectively, produces first frequency-doubled signal and second frequency-doubled signal;
First frequency-doubled signal and second frequency-doubled signal are carried out the first phase place adjustment and the second phase place adjustment simultaneously, in a very little scope, and the phase difference of adjusted two output signals of second phase place is also in a very little scope until the phase difference of adjusted two output signals of first phase place;
Control signal according to the outside input is respectively selected a signal that derives from first frequency-doubled signal or second frequency-doubled signal as output signal respectively from the first phase place adjustment and adjusted two output signals of second phase place.
2. the clock signal switching selector in the synchronous clock supply system, it is characterized in that, it comprises two identical modules of working simultaneously, each module comprises a frequency multiplier circuit, one with the unidirectional phase-adjusting circuit that connects of this frequency multiplier circuit, one with the unidirectional clock switching selecting circuit that connects of this phase-adjusting circuit, two modules link by following mode: each clock switching selecting circuit is interconnected, each phase-adjusting circuit is interconnected, the phase-adjusting circuit of this module also connects with the frequency multiplier circuit of another module is unidirectional, wherein: each frequency multiplier circuit carries out frequency multiplication respectively from outside receiving inputted signal; Each phase-adjusting circuit receives the signal that each frequency multiplier circuit transmits respectively, carries out input and adopts their phase difference of delay line technological adjustment to very little scope, exports adjusted two signals and testing result signal, and they also carry out information interaction simultaneously; Each clock switching selecting circuit is selected an output according to external control signal with from the testing result signal of phase-adjusting circuit from adjusted two signals of this phase-adjusting circuit output, they go back interactive information simultaneously.
3, the clock signal switching selector in a kind of synchronous clock supply system according to claim 2 is characterized in that, described clock switching selecting circuit comprises:
The pulse detection switch unit receives outside pulse detection alarm signal, the output switching command;
The module status switch unit receives outside module status index signal, the output switching command;
Function control switch unit receives outside function control signal, the output switching command;
Clock switches selects control unit, except receiving outside default setting signal, also receive the switching command of above-mentioned three unit output, and the output switching command that receives is carried out priority select, the switching command of first-selected pulse detection switch unit output, next selects the switching command of module status switch unit output, moreover the switching command of selection function control switch unit output, select outside default setting signal at last, export selected signal then;
The clock output select unit switches the selection control unit from clock and obtains selected signal, and selects an output from two input clock signals of outside.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 99127043 CN1108024C (en) | 1999-12-29 | 1999-12-29 | Clock signal switching and selecting method in synchronous clock supply system and its device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 99127043 CN1108024C (en) | 1999-12-29 | 1999-12-29 | Clock signal switching and selecting method in synchronous clock supply system and its device |
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| Publication Number | Publication Date |
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| CN1302121A CN1302121A (en) | 2001-07-04 |
| CN1108024C true CN1108024C (en) | 2003-05-07 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 99127043 Expired - Lifetime CN1108024C (en) | 1999-12-29 | 1999-12-29 | Clock signal switching and selecting method in synchronous clock supply system and its device |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100438361C (en) * | 2003-08-01 | 2008-11-26 | 华为技术有限公司 | Method for controlling master spare clock phase for synchronous digital system equipment |
| CN1309169C (en) * | 2004-10-27 | 2007-04-04 | 中兴通讯股份有限公司 | Multipath clock detecting device |
| CN100338967C (en) * | 2005-05-19 | 2007-09-19 | 北京北方烽火科技有限公司 | Method and apparatus for realizing clock redundancy back-up in WCDMA system base station |
| CN101078944B (en) * | 2007-05-11 | 2010-05-26 | 东南大学 | Clock switching circuit |
| CN101252405B (en) * | 2008-03-27 | 2012-09-05 | 华为技术有限公司 | Clock detection and auto switching method and system |
| CN101693921B (en) * | 2009-10-10 | 2013-02-06 | 上海中优医药高科技有限公司 | Detection primer of gene mutation of phenylalanine hydroxylase |
| CN104717090B (en) * | 2013-12-17 | 2019-07-02 | 中兴通讯股份有限公司 | Interface signal is active and standby mutually to send processing method and system |
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1999
- 1999-12-29 CN CN 99127043 patent/CN1108024C/en not_active Expired - Lifetime
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| CN1302121A (en) | 2001-07-04 |
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Address after: 201206 No. 388-389 Nanjing Road, Jinqiao, Shanghai, Pudong Patentee after: ALCATEL-LUCENT SHANGHAI BELL Co.,Ltd. Address before: 201206 No. 388-389 Nanjing Road, Jinqiao, Shanghai, Pudong Patentee before: Shanghai Bell Alcatel Co.,Ltd. Address after: 201206 No. 388-389 Nanjing Road, Jinqiao, Shanghai, Pudong Patentee after: Shanghai Bell Alcatel Co.,Ltd. Address before: 201206 No. 388-389 Nanjing Road, Jinqiao, Shanghai, Pudong Patentee before: Shanghai Bell Co.,Ltd. |
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