CN109543811A - A kind of counting circuit, method of counting and chip - Google Patents
A kind of counting circuit, method of counting and chip Download PDFInfo
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- CN109543811A CN109543811A CN201811291858.2A CN201811291858A CN109543811A CN 109543811 A CN109543811 A CN 109543811A CN 201811291858 A CN201811291858 A CN 201811291858A CN 109543811 A CN109543811 A CN 109543811A
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- pulse signal
- counter
- multichannel
- latch
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06M—COUNTING MECHANISMS; COUNTING OF OBJECTS NOT OTHERWISE PROVIDED FOR
- G06M1/00—Design features of general application
- G06M1/27—Design features of general application for representing the result of count in the form of electric signals, e.g. by sensing markings on the counter drum
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Engineering & Computer Science (AREA)
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- Manipulation Of Pulses (AREA)
Abstract
The invention discloses a kind of counting circuit, method of counting and chip, counting circuit includes: multichannel latch pulse input unit, multichannel latch control logic unit, latch units and counter；The output end of multichannel latch pulse input unit is connect with the input terminal that multichannel latches control logic unit, and the output end that multichannel latches control logic unit is connect with counter, and counter is connect with latch units；After multichannel latch pulse input unit receives multiplex pulse signal, multichannel latches control logic unit and carries out logic judgment to multiplex pulse signal according to setting logic circuit and collect multiplex pulse signal, multichannel latches control logic unit and sends trigger signal to counter according to the multiplex pulse signal collected, triggering latch units latch the current count value of counter after counter receives trigger signal, and the present invention needs to be arranged the technical issues of multiple counters solve synchronous error measurement or the adjustment of multiplex pulse width synchronization to solve in existing system.
Description
Technical field
The present invention relates to electric circuit construction technical fields, and in particular to a kind of counting circuit, method of counting and chip.
Background technique
Counting circuit is to be carried out periodically in computer or the common function of signal processing system using system work clock
It counts, completes hardware or software timing function, while also having and counting latch function, but do not support multichannel external trigger function
Can, it is not able to satisfy the system that multiple external triggers latch demand, for example go to adjust using the pulse signal all the way of accurate metering
Another way or the not high pulse of multichannel accuracy, or using the pulse signal all the way for having accurate metering desynchronize in addition all the way or
The pulse signal of multichannel, traditional realization need to be arranged multiple counters and solve synchronous error measurement or multiplex pulse width synchronization
Adjustment, the higher cost that simultaneity factor is realized.
Summary of the invention
The embodiment of the present invention is designed to provide a kind of counting circuit, method of counting and chip, existing to solve
Need to be arranged the technical issues of multiple counters solve synchronous error measurement or the adjustment of multiplex pulse width synchronization in system.
To achieve the above object, the embodiment of the invention provides a kind of counting circuits, comprising: the input of multichannel latch pulse is single
Member, multichannel latch control logic unit, latch units and counter；The output end of the multichannel latch pulse input unit and institute
State the input terminal connection that multichannel latches control logic unit, the output end of the multichannel latch control logic unit and the counting
Device connection, the counter are connect with the latch units；The multichannel latch pulse input unit receives multiplex pulse signal
Afterwards, the multichannel latches control logic unit and carries out logic judgment to the multiplex pulse signal according to setting logic circuit and converge
Collect the multiplex pulse signal, the multichannel latches control logic unit according to the multiplex pulse signal collected to the meter
Number device sends trigger signal, and the counter triggers the latch units to the counter after receiving the trigger signal
Current count value is latched.
Preferably, the setting logic circuit is designed according to the input state of the multiplex pulse signal, institute
It states the combinational logic that input state includes: the multiplex pulse signal and meets the triggering latch units and the counter is worked as
The condition that preceding count value is latched, wherein any pulse signal all the way in the multiplex pulse signal or at least arteries and veins all the way
It rushes signal and meets the condition that the latch units latch the current count value of the counter that triggers.
Preferably, value register is counted, the counting value register is connect with the latch units, the count value deposit
Device is used to store the mapping relations of the count value and the corresponding every road pulse signal mark of the count value.
Preferably, the cycle counter that the counter is 32 or more.
Preferably, the first host data Fabric Interface is provided on the counter, the first host data exchange connects
Mouth is the interface that the counter is communicated with CPU.
Preferably, tally control logic unit, the counter are connect with the tally control logic unit, the counting
Control logic unit is for controlling the counter setting initial count value, starting counting and terminate counting.
It preferably, further include pulse signal input status register, the pulse signal input status register passes through the
Two host data Fabric Interfaces can be accessed by CPU, and the pulse signal input status register obtains and stores the multichannel arteries and veins
Rush the input state and the corresponding mark of every road pulse signal of signal.
Preferably, further includes: digital PLL circuit, the digital PLL circuit are connect with clock unit, the number
For adjusting, the clock unit inputs the multichannel latch pulse input unit to word phase-locked loop circuit, the multichannel latches control
Logic unit, the counter, counts value register, CPU, tally control logic unit and pulse signal at the latch units
The frequency of the signal of input status register.
Still further aspect, the embodiment of the invention provides a kind of method of counting, which comprises
Receive multiplex pulse signal；Logic judgment is carried out to the multiplex pulse signal according to setting logic circuit and is collected
The multiplex pulse signal；Trigger signal is sent to counter according to the multiplex pulse signal collected, the counter connects
Triggering latch units latch the current count value of the counter after receiving the trigger signal.
Still further aspect, the embodiment of the invention provides a kind of chips, including, counting circuit as described above.
The embodiment of the present invention has the advantages that
A kind of counting circuit, method of counting and the chip that the embodiment of the present invention proposes, technology disclosed by the embodiments of the present invention
Scheme can be reduced goes adjustment another way or multichannel accuracy not high using the pulse signal all the way of accurate metering in the prior art
Pulse, or using accurate metering pulse signal all the way desynchronize one or more other pulse signal counting circuit in meter
Number device quantity, the prior art need multiple counters to realize that above-mentioned function, the present invention only need a counter, reduce counting
The quantity of device, while also avoiding being arranged in the prior art that multiple counters solve synchronous errors measurement or multiplex pulse width is same
The technical issues of successive step, is provided with multichannel in the counting circuit of the embodiment of the present invention and latches control logic unit to multiplex pulse
The logic judgment of signal can carry out logic judgment to multiplex pulse signal and then collect multiplex pulse signal, and triggering is latched single
Member latches the current count value of counter.
Detailed description of the invention
Fig. 1 is that the embodiment of the present invention discloses counting circuit structural schematic diagram.
Fig. 2 is a kind of method of counting flow diagram disclosed by the embodiments of the present invention.
Specific embodiment
In order that those skilled in the art will better understand the technical solution of the present invention, implement below in conjunction with the present invention
Attached drawing in example, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment
Only a part of the embodiments of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is common
Technical staff's every other embodiment obtained without making creative work, all should belong to protection of the present invention
Range.
It should be noted that description and claims of this specification and term " first " in above-mentioned attached drawing, "
Two " etc. be to be used to distinguish similar objects, without being used to describe a particular order or precedence order.It should be understood that using in this way
Data be interchangeable under appropriate circumstances, so as to the embodiment of the present invention described herein can in addition to illustrating herein or
Sequence other than those of description is implemented.In addition, term " includes " and " having " and their any deformation, it is intended that cover
Cover it is non-exclusive include, for example, the process, method, system, product or equipment for containing a series of steps or units are not necessarily limited to
Step or unit those of is clearly listed, but may include be not clearly listed or for these process, methods, product
Or other step or units that equipment is intrinsic.
As shown in Figure 1, the embodiment of the invention provides a kind of counting circuit structural schematic diagrams.
Counting circuit disclosed by the embodiments of the present invention include: multichannel latch pulse input unit 01, multichannel latch control patrol
Unit 02, latch units 06 and counter 04 are collected, the output end and multichannel of multichannel latch pulse input unit 01 latch control and patrol
The input terminal connection of volume unit 02, the output end that multichannel latches control logic unit 02 are connect with counter 04, counter 04 and
Latch units 06 connect.
Further include counting value register 07, count value register 07 and connect with latch units 06, counts value register 07 and use
In the mapping relations that stored count value and count value corresponding multiplex pulse signal Zhong Mei road pulse signal identify, every road pulse
Signal identification can be customized according to system progress, is then assigned to corresponding every road pulse signal.
It further include that digital PLL circuit 09, digital PLL circuit 09 is connect with clock unit 08, digital phase-locked loop electricity
Road 09 inputs multichannel latch pulse input unit 01 for adjusting clock unit 08, multichannel latches control logic unit 02, latches
Unit 06, counter 04, counting value register 07, CPU 10, tally control logic unit 05 and pulse signal input state are posted
The frequency of 03 signal of storage, clock unit 08 are the working foundations of all functional units of the present invention.
The cycle counter that counter 04 is 32 or more, counter 04 can adjust the length of counter 04 as needed.
Further include: tally control logic unit 05, counter 04 are connect with tally control logic unit 05, and tally control is patrolled
Unit 05 is collected to be used for the setting of control counter 04 initial count value, start counting and terminate to count.
It is provided with central processor CPU 10 in counting circuit, the exchange of the first host data is provided on counter 04 and is connect
Mouthful, the first host data Fabric Interface is the interface that counter 04 is communicated with CPU 10.
It further include that pulse signal input status register 03, pulse signal input status register 03 is connect with CPU10,
Latch pulse input status register 03 is obtained and is stored every in the input state and multiplex pulse signal of multiplex pulse signal
The corresponding mark of road pulse signal, CPU 10 can obtain pulse signal input state by the second host data Fabric Interface and post
The corresponding mark of the road multiplex pulse signal Zhong Mei pulse signal stored on storage 03, CPU 10 are deposited by access count value
Mapping relations between the available count value of device 07 and the corresponding mark of every road pulse signal.
Setting pulse signal input status register 03 of the embodiment of the present invention can increase to be realized using the embodiment of the present invention
The flexibility of system function to be achieved, when starting to carry out circuit design, if there is multiplex pulse signal, if merely from hard
It is extremely complex for carrying out logic judging circuit in part design, so increasing pulse signal input status register 03 can mitigate
The complexity of hardware design can carry out the sharing a part of the task, CPU 10 by pulse signal input status register 03
The data on pulse signal input status register 03 are accessed by the second host data Fabric Interface, can be matched by software and hardware
It closes to complete logic judgment and the arbitration of multiplex pulse signal, increases and realize system function to be achieved using the embodiment of the present invention
The flexibility of energy.
In embodiment disclosed by the invention, multichannel latch pulse input unit 01 is for receiving the defeated of multiplex pulse signal
Enter；Multichannel latches the multiplex pulse signal that control logic unit 02 is used to that multichannel latch pulse input unit 01 to be cooperated to complete input
Arbitration judge and prevent lose multiplex pulse signal；The counter 04 that latch units 06 are used to trigger multiplex pulse signal
Current count value is latched；
Counter 04 is for counting system clock unit 08, in embodiment disclosed by the invention, only setting one
The systematic demand of institute can be completed in a counter 04, simplifies the complexity of circuit design, also solve need to be arranged it is multiple
The technical issues of synchronous error measurement or multiplex pulse width synchronization that counter solves adjust.
In embodiment disclosed by the invention, after multichannel latch pulse input unit 01 receives multiplex pulse signal, multichannel lock
Control logic unit 02 is deposited to carry out logic judgment to multiplex pulse signal according to setting logic circuit and collect multiplex pulse signal,
Multichannel latches control logic unit 02 and sends trigger signal to counter 04 according to the multiplex pulse signal collected, and counter 04 connects
Triggering latch units 06 latch the current count value of counter 04 after receiving trigger signal.
Setting logic circuit is designed according to the input state of multiplex pulse signal, and input state includes:
The combinational logic of multiplex pulse signal meets triggering latch units and latches to the current count value of counter 04
Condition, wherein any pulse signal all the way in multiplex pulse signal or at least pulse signal meets the triggering lock all the way
The condition that memory cell 06 latches the current count value of counter 04.
Setting logic circuit is combined logic judgment according to the default function of realizing and determines the type that count value latches.
Counting circuit disclosed by the invention specifically includes that clock unit 08, multichannel latch pulse input unit 01, multichannel lock
Deposit the counter 04 and tally control logic unit 05 of 02,32 bit length of control logic unit or more, host data Fabric Interface；
Clock unit 08 receives crystal oscillator or system clock input, as the working foundation of counter 04, can increase number if necessary
Clock is inputted frequency multiplication by phase-locked loop circuit 09 (DPLL), improves counting accuracy.Multichannel latch pulse input unit 01 is to connect
By the circuit of multiple external multiplex pulse signal triggering inputs, cooperation multichannel latches control logic unit 02 and completes input signal
Arbitration judges and prevents from losing multiplex pulse signal, and the count value of latch is stored in and is counted in value register 07, centre
Reason device CPU10 can obtain these values by the data channel of counter 04, and accessed according to design requirement and these is utilized to count
According to.More than 32 bit lengths counter 04 and tally control logic are general cycle counters, can adjust counting as needed
The length of device, and Counter Design scheme is adjusted therewith, it is locked according to the trigger signal that multichannel latch pulse input unit 01 provides
Deposit current count value.Host data Fabric Interface is the interface communicated with CPU 10, according to this counting circuit in whole system
In integrated form use access bus appropriate, but must assure that data obtaining time within the acceptable range, on piece
It can be data access bus in system (SOC), can be concurrently or sequentially bus in discrete part.
A kind of counting circuit disclosed by the embodiments of the present invention, wherein increase multichannel and latch control logic unit 02, multichannel
Latching control logic unit 02 can receive qualified to multiplex pulse signal progress logic judgment and arbitration, counter 04
Pulse signal triggering, and trigger latch units 06 and the current count value of counter 04 is latched, The present invention reduces countings
The quantity of device, reduces cost, reduces the complexity of circuit design.
Still further aspect, as shown in Fig. 2, the embodiment of the invention discloses a kind of method of counting:
It should be noted that step shown in the flowchart of the accompanying drawings can be in such as a group of computer-executable instructions
It is executed in computer system, although also, logical order is shown in flow charts, and it in some cases, can be with not
The sequence being same as herein executes shown or described step.
A kind of method of counting disclosed by the invention the following steps are included:
Step S1 receives multiplex pulse signal；
It should be noted that can be received by multichannel latch pulse input unit 01 more in embodiment disclosed by the invention
A external pulse signal input.
Step S2 carries out logic judgment to the multiplex pulse signal according to setting logic circuit and collects the multichannel arteries and veins
Rush signal；
Multiplex pulse signal is carried out according to setting logic circuit it should be noted that multichannel latches control logic unit 02
Logic judgment simultaneously collects multiplex pulse signal, is combined logic judgment especially by the function of default realization and determines count value
It latches.
Step S3 sends trigger signal to counter according to the multiplex pulse signal collected, and the counter receives
Latch units are triggered after to the trigger signal to latch the current count value of the counter.
Still further aspect, the embodiment of the invention also discloses a kind of chip, chip includes above-mentioned counting circuit；
The structure of specific counting circuit is same as the previously described embodiments, is not just repeating at this.
A kind of counting circuit, method of counting and the chip that the embodiment of the present invention proposes, technology disclosed by the embodiments of the present invention
Scheme can be reduced goes adjustment another way or multichannel accuracy not high using the pulse signal all the way of accurate metering in the prior art
Pulse, or using accurate metering pulse signal all the way desynchronize one or more other pulse signal counting circuit in meter
Number device quantity, the prior art need multiple counters to realize that above-mentioned function, the present invention only need a counter, reduce counting
The quantity of device, while also avoiding being arranged in the prior art that multiple counters solve synchronous errors measurement or multiplex pulse width is same
The technical issues of successive step, is provided with multichannel in the counting circuit of the embodiment of the present invention and latches control logic unit to multiplex pulse
The logic judgment of signal can targetedly trigger latch units and latch to the current count value of counter.
Although having used general explanation and specific embodiment herein, the present invention is described in detail, at this
On the basis of invention, it can be made some modifications or improvements, this will be apparent to those skilled in the art.Therefore,
These modifications or improvements without departing from theon the basis of the spirit of the present invention are fallen within the scope of the claimed invention.
Claims (10)
1. a kind of counting circuit characterized by comprising multichannel latch pulse input unit, multichannel latch control logic unit,
Latch units and counter；
The output end of the multichannel latch pulse input unit is connect with the input terminal that the multichannel latches control logic unit, institute
The output end for stating multichannel latch control logic unit is connect with the counter, and the counter is connect with the latch units；
After the multichannel latch pulse input unit receives multiplex pulse signal, the multichannel latches control logic unit according to setting
Determine logic circuit to carry out logic judgment to the multiplex pulse signal and collect the multiplex pulse signal, the multichannel latches control
Logic unit processed sends trigger signal to the counter according to the multiplex pulse signal collected, and the counter receives
The latch units are triggered after the trigger signal to latch the current count value of the counter.
2. a kind of counting circuit as described in claim 1, which is characterized in that the setting logic circuit is according to the multichannel
What the input state of pulse signal was designed, the input state includes:
The combinational logic of the multiplex pulse signal meet the current count value that triggers the latch units to the counter into
The condition that row latches, wherein any pulse signal all the way in the multiplex pulse signal or at least pulse signal meets all the way
Trigger the condition that the latch units latch the current count value of the counter.
3. a kind of counting circuit as described in claim 1, which is characterized in that further include: count value register, the count value
Register is connect with the latch units, and the counting value register is used to store the count value and the count value is corresponding
The mapping relations of every road pulse signal mark.
4. a kind of counting circuit as described in claim 1, which is characterized in that the cycle count that the counter is 32 or more
Device.
5. a kind of counting circuit as described in claim 1, which is characterized in that be provided with the first host data on the counter
Fabric Interface, the first host data Fabric Interface are the interface that the counter is communicated with CPU.
6. a kind of counting circuit as described in claim 1, which is characterized in that further include: tally control logic unit, the meter
Number device is connect with the tally control logic unit, and the tally control logic unit is initial for controlling the counter setting
Count value starts counting and terminates to count.
7. a kind of counting circuit as described in claim 1, which is characterized in that it further include pulse signal input status register,
The pulse signal input status register can be accessed by the second host data Fabric Interface by CPU, and the pulse signal is defeated
Enter input state and the corresponding mark of every road pulse signal that status register obtains and stores the multiplex pulse signal.
8. a kind of counting circuit as described in claim 1, which is characterized in that further include: digital PLL circuit, the number
Phase-locked loop circuit is connect with clock unit, and the digital PLL circuit inputs the multichannel lock for adjusting the clock unit
Deposit pulse input unit, the multichannel latch control logic unit, the latch units, the counter, count value register,
The frequency of the signal of CPU, tally control logic unit and pulse signal input status register.
9. a kind of method of counting, which is characterized in that the described method includes:
Receive multiplex pulse signal；
Logic judgment is carried out to the multiplex pulse signal according to setting logic circuit and collects the multiplex pulse signal；
Trigger signal is sent to counter according to the multiplex pulse signal collected, the counter receives the triggering letter
Latch units are triggered after number to latch the current count value of the counter.
10. a kind of chip, which is characterized in that including counting circuit as described in claim 1 to 8 any one.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811291858.2A CN109543811B (en) | 2018-10-31 | 2018-10-31 | Counting circuit, counting method and chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811291858.2A CN109543811B (en) | 2018-10-31 | 2018-10-31 | Counting circuit, counting method and chip |
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| CN109543811B CN109543811B (en) | 2023-06-16 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113377045A (en) * | 2021-06-08 | 2021-09-10 | 广东三姆森科技股份有限公司 | Multi-path position comparison output device based on FPGA |
| CN114118337A (en) * | 2021-11-19 | 2022-03-01 | 深圳诺博医疗科技有限公司 | Batch medicine bottle classification counting method and device |
| CN114951046A (en) * | 2022-05-10 | 2022-08-30 | 苏州天准科技股份有限公司 | Latch counting trigger equipment and system |
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| CN109543811B (en) | 2023-06-16 |
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