CN103901942B - For the calibration method and device of the clock accuracy of terminal - Google Patents
For the calibration method and device of the clock accuracy of terminal Download PDFInfo
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Abstract
The present invention relates to terminal, a kind of calibration method and device of the clock accuracy for terminal are disclosed.In the present invention, closed by obtaining fast clock, the time span that slow clock works, and the timing offset in the time span；And timing offset ratio is calculated accordingly；The conversion of timing offset ratio is modified to the proportionality coefficient of slow clock and fast clock, the calibration to slow clock accuracy is completed.Due to by measuring timing offset of the slow clock in onset time section, and according to the slow clock of timing offset amendment and the proportionality coefficient of fast clock, reach the purpose for calibrating slow clock, therefore so that the calibration to slow clock accuracy, the dependence to hardware is reduced, improve the degree of accuracy, power consumption is reduced, timing offset is corrected in time, such that it is able to further lifting terminal receptivity.
Description
Technical field
The present invention relates to terminal, more particularly to for terminal clock accuracy calibration method and device.
Background technology
During existing terminal is realized, it will usually use a brilliant shake of 26M as system clock, producing ratio is more fixed
When, but because terminal is not constantly working condition, therefore would generally be carried out under IDLE using a slow clock of 32K
Timing controlled when sleep, it is insensitive to temperature change because 26M clocks are brilliant shakes producing, it is relatively more accurate, and 32K
Clock is then more sensitive to temperature change, therefore 32K clocks will often be calibrated to prevent its accuracy from deviation occurring.
Way as at present, although say and largely save power consumption, but in the process of 32K clock alignments
In, because the method for using hardware calibration, it is still required for being counted using 26M clocks, and under usual condition, because
To do hardware calibration before, follow-up flow can be further to optimize, by small using software calibration
The method of deviation, further to reduce dependence of the calibration to hardware, so as to realize that power consumption is more saved.
The content of the invention
It is an object of the invention to provide a kind of calibration method and device of the clock accuracy for terminal so as to clock
The calibration of precision, reduces the dependence to hardware, improves the degree of accuracy, reduces power consumption, timing offset is corrected in time, such that it is able to enter one
Step lifting terminal receptivity.
In order to solve the above technical problems, embodiments of the present invention provide a kind of calibration of clock accuracy for terminal
Method, the terminal has fast clock and a slow clock, and the fast clock clock frequency more than the slow clock clock frequently
Rate, the fast clock is accurately；Comprise the steps of：
A. obtain the fast clock to close, the time span T that the slow clock works, and in the T time length
Timing offset Δ T；
B. according to the Δ T and T, it is calculated timing offset ratio Δ R；
C. the proportionality coefficient of the slow clock and the fast clock is read；Wherein, the initial value of the proportionality coefficient passes through
Hardware calibration is obtained；
D. the proportionality coefficient of the reading is subtracted into the timing offset ratio, obtains new proportionality coefficient, completed to slow
The calibration of clock accuracy.
Embodiments of the present invention additionally provide a kind of calibrating installation of the clock accuracy for terminal, and the terminal has
Fast clock and slow clock, and the fast clock clock frequency of the clock frequency more than the slow clock, the fast clock is essence
Accurate, comprising：Duration acquisition module, timing offset acquisition module, timing offset ratio computing module, proportionality coefficient obtain mould
Block, clock alignment module；
The duration acquisition module is used to obtain the fast clock closing, the time span T that the slow clock works；
The timing offset acquisition module is used to obtain the timing offset Δ T in the T time length；
The timing offset ratio computing module is used for according to the Δ T and T, is calculated timing offset ratio Δ
R；
The proportionality coefficient acquisition module is used to read the proportionality coefficient of the slow clock and the fast clock；Wherein, institute
The initial value for stating proportionality coefficient is obtained by hardware calibration；
The clock alignment module is used to for the proportionality coefficient of the reading to subtract the timing offset ratio, obtains new
Proportionality coefficient, completes the calibration to slow clock accuracy.
Embodiment of the present invention in terms of existing technologies, is closed, the time that slow clock works by obtaining fast clock
Length, and the timing offset in the time span；And timing offset ratio is calculated accordingly；By the conversion of timing offset ratio
Proportionality coefficient to slow clock and fast clock is modified, and completes the calibration to slow clock accuracy.Due to by measuring in action
Timing offset in time period, and according to the slow clock of timing offset amendment and the proportionality coefficient of fast clock, reach calibration it is slow when
The purpose of clock, therefore so that the calibration to slow clock accuracy, the dependence to hardware is reduced, the degree of accuracy is improved, power consumption is reduced, and
Shi Xiuzheng timing offset, such that it is able to further lifting terminal receptivity.
In addition, in the step A, comprising following sub-step：
After each terminal is waken up from sleep state, the terminal receives paging, and obtains length of one's sleep length, as
The T；Wherein, the terminal is in the fast clock in the sleep state time period and closes, and the slow clock works；
Reception data to receiving paging carry out channel estimation, the timing offset amount in length of one's sleep length are obtained, as institute
State Δ T.
Because terminal was in the sleep state time period, fast clock is closed, and slow clock works, and length of one's sleep length is held very much
Easily obtain, and can all go to receive paging after each terminal is waken up, can be calculated in length of one's sleep length according to data are received
Interior timing offset, therefore, obtain the timing offset produced in length of one's sleep length and time period, can further make to it is slow when
The calibration of clock precision, reduces the dependence to hardware.
Furthermore it is possible to pass through directly to calculate the ratio of the Δ T and the T, and using the ratio as the Δ R, from
And timing offset ratio is obtained, computational methods are simple, reduce clock accuracy calibration duration, so as to further reduce work(
Consumption.
Furthermore it is also possible to calculate timing offset ratio by following three kinds of modes：
The first：Compare the size of the Δ T and default threshold value；If the Δ T is less than or equal to default
Threshold value, then calculate the ratio of the Δ T and the T, and using the ratio as the Δ R；If the Δ T is more than default
Threshold value, then calculate the ratio of the default threshold value and the T, and using the ratio as the Δ R.
Second：Calculate the average of predetermined number Δ T；Calculate the average of the corresponding T of the predetermined number Δ T；Calculate institute
The ratio of the average of Δ T and the average of the T is stated, using the ratio as the Δ R.
The third：According to the variation tendency of predetermined number Δ T, adjusted value is determined；Calculate the ratio of the adjusted value and the T
Value, using the ratio as the Δ R.
By above-mentioned three kinds of computational methods, accurate timing offset ratio can be obtained, so as to ensure clock accuracy
The robustness of calibration.
Brief description of the drawings
Fig. 1 is the flow chart of the calibration method of the clock accuracy for terminal according to first embodiment of the invention；
Fig. 2 is the calibration structure schematic diagram of the clock accuracy for terminal according to third embodiment of the invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to each reality of the invention
The mode of applying is explained in detail.However, it will be understood by those skilled in the art that in each implementation method of the invention,
In order that reader more fully understands the application and proposes many ins and outs.But, even if without these ins and outs and base
Many variations and modification in following implementation method, it is also possible to realize the application each claim technical side required for protection
Case.
First embodiment of the invention is related to a kind of calibration method of the clock accuracy for terminal, and the method is applied to
Following situation：Terminal has fast clock and slow clock, and the clock frequency of clock is more than the clock frequency of slow clock, fast clock soon
It is accurately.Such as, typical fast clock is the 2G clocks for operating on normal manipulation mode（For example：26MHz, referred to as " during 26M
Clock "）Or 3G clocks（For example：30.72MHz）, typical slow clock is the 2G clocks for operating on sleep pattern（For example：
32.768KHz, referred to as " 32K clocks "）.The flow of present embodiment is as shown in figure 1, specifically comprise the steps of：
Step 101, obtains fast clock and closes, the time span T that slow clock works, and timing in T time length is inclined
Difference Δ T.
Specifically, after each terminal is waken up from sleep state, terminal receives paging, and it is long to obtain the length of one's sleep
Degree, as T；Wherein, terminal is in fast clock in the sleep state time period and closes, and slow clock works；Reception number to receiving paging
According to channel estimation is carried out, the timing offset amount in length of one's sleep length is obtained, as Δ T.When being in sleep state due to terminal
Between in section, fast clock is closed, and slow clock works, and length of one's sleep length is easy to obtain, and after each terminal is waken up all
Can go to receive paging, the timing offset in length of one's sleep length can be calculated according to data are received, therefore, obtain the length of one's sleep
The timing offset produced in length and time period, can further make the calibration to slow clock accuracy, reduce to hardware according to
Rely.
Step 102, according to Δ T and T, is calculated timing offset ratio Δ R.Specifically, can be by directly calculating
The ratio of Δ T and T, and using the ratio as Δ R, so as to obtain timing offset ratio, computational methods are simple, reduce clock accuracy
Calibration duration, so as to further reduce power consumption.
Step 103, reads the proportionality coefficient of slow clock and fast clock；Wherein, the initial value of proportionality coefficient passes through hardware school
Standard is obtained.
Step 104, timing offset ratio is subtracted by the proportionality coefficient of reading, obtains new proportionality coefficient, complete to it is slow when
The calibration of clock precision.
It is below 26M clocks with fast clock, slow clock is specifically described as a example by 32K clocks.Terminal is being slept
When, to save power consumption, it will usually the control being timed using chip internal low rate clock, usually used is
32K clocks come carry out sleep timing setting.Because the inaccuracy of 32K clocks, the deviation that it causes with temperature change compared with
Greatly, so when using 32K clocks, some limitations are had, than if desired for the school that 32K clocks are carried out according to certain condition
It is accurate.Here calibration, at present use main method be hardware calibration, i.e., at the appointed time respectively to 32K clocks and 26M when
Clock is counted respectively, and both count results are carried out into certain association to time point, you can obtain a 32K clocks correspondence
X.y 26M clock, X is integer part, and y is fractional part.Because 26M clocks are accurately, obtain 32K clocks with
After 26M clock ratio relations, it is believed that 32K clocks are also accurate.
When terminal enters and sleeps, the duration that can be slept as needed needs N number of accurate 26M clocks conduct to calculate
Digit, then by this digit according to the proportionate relationship after above-mentioned calibration, it is converted to K 32K clock and J
26M clocks, wherein：J=N-K × X.y,Represent downward rounding operation.
During use, with the change of temperature, 32K clocks can occur certain change, and this when is just no longer
Can get up with the matching of calibration result before, it is therefore desirable to do calibration again.
Consider that temperature variations are relatively slow for the interval that terminal sleep wakes up now, terminal is typically slept
Maximum duration is in long evolving system（LTE）It is down 2.56s, in time division multiple acess-synchronization system（TD-S）It is down 2.56s, complete
Ball GSM（GSM）Down be 2.2s, it is generally the case that in this period temperature change will not difference it is too big.
After each software wakes up terminal under idle condition IDLE, terminal can all go to receive paging, can be counted according to data are received
Calculate timing offset.And timing offset is general by so several aspects introducings：
Terminal timing error in itself, for example error of 32K clocks；
Terminal is such as close to or away from base station because the mobile error for introducing；
Because the error that 32K clocks are introduced, magnitude may be in 10ppm magnitudes（ppm：Part per million, Bai Wanfen
One of）, and because the mobile error for introducing, calculated according to maximum 500km/h, with respect to the ratio 0.46*10 of the light velocity-6, also
It is to say magnitude less than 1ppm, it is therefore contemplated that the principal element that timing offset is introduced is 32K clocks.
In view of conclusions, the method that present embodiment can be obtained：32K clocks are improved by calibrating 32K clocks
Precision.
For the calibration of 32K clocks, above-mentioned hardware calibration method is by again to mark 26M clocks, according to 26M
The counting situation of clock accurately represents time of current 32K clocks.But, since have been obtained for sleep awakening here
Timing offset, it is possible to utilize this timing offset amendment 32K clock accuracy, specific method is as follows：
1. terminal sleep time span T before being waken up is obtained.
2. by receiving the channel estimation that data are carried out, obtaining the timing offset amount Δ T of present terminal.
3. the departure being calculated after sleep awakening is calculatedHerein, due toMagnitude it is very small,
About a few millionths, therefore Δ R can be amplified 106Times, i.e.,Calculate and store to facilitate.
4. 32K clocks and 26M clock ratio coefficients Rs are read32k/26M, i.e., one 32K clock represents R32k/26MIndividual 26M clocks,
The initial value of the parameter needs to be obtained by hardware calibration, such as fixed when just start and done, and specific practice is referring to correlation
Hardware calibration method, will not be repeated here.R32k/26MInteger part be designated as R32k/26M_int, fractional part is designated as
R32k/26M_floor, conventional parameter storage method is that, using the register of 32,16 high store integer-bit, and low 16 are deposited
Storage decimal place, i.e.,：
R32k/26M=R32k/26M_int<<16+R32k/26M_floor；
In formula,<<Represent shifted left computing.Following computational methods are carried out based on this kind of storage mode.
5. the departure that 1 unit value of integer part deviation is represented is 1 26M clock of deviation in each 32K clock,In order to the magnitude with Δ ppm is consistent, it is necessary to amplify 106Times, i.e.,
Fractional part then represents different precision according to its digit, and fractional part is represented with 16 the most frequently used 2 system method for expressing
If, then the corresponding departure of unit deviation value of each fractional part is：Equally,
In order to the magnitude with Δ ppm is consistent, and it is exaggerated 106, obtain
6. the Δ ppm that will be estimated before is converted to parameter R32k/26MModify, amending method such as following two is public
Listed by formula：
That is,：
Finally collect and obtain：
In formula, mod represents complementation computing.
7. by R32k/26MIt is updated toComplete the amendment to 32K clocks.
Compared with prior art, present embodiment is closed by obtaining fast clock, the time span that slow clock works, and
Timing offset in the time span；And timing offset ratio is calculated accordingly；By the conversion of timing offset ratio to slow clock
Proportionality coefficient with fast clock is modified, and completes the calibration to slow clock accuracy.Due to by measure slow clock work when
Between timing offset in section, and according to the slow clock of timing offset amendment and the proportionality coefficient of fast clock, reach the slow clock of calibration
Purpose, therefore so that the calibration to slow clock accuracy, reduce dependence to hardware, improve the degree of accuracy, reduce power consumption, in time
Amendment timing offset, such that it is able to further lifting terminal receptivity.
Second embodiment of the present invention is related to a kind of calibration method of the clock accuracy for terminal.Second embodiment
Further improvement is done on the basis of first embodiment, has mainly been theed improvement is that：In this second embodiment, can pass through
Statistical method, obtains the timing offset ratio of accurately slow clock, so as to ensure the robustness of clock accuracy calibration.
For the calculating process of first embodiment description, because the influence of some destabilizing factors in actual environment,
Change repeatedly such as temperature, multi-path influence and measured deviation etc., cause the adjustment amount in the calibration to slow clock to have may not be
Whole, therefore, it is necessary to consider to the measured deviation that a variety of causes is introduced, acquisition is more during implementing
Accurate measured value.Such method has more, such as by multiple averaging, or the method such as observation trend, it is industry and is familiar with
Method.After accurate measurement result is obtained, can be limited according to maximum adjustment amount, or the strategy such as trend adjustment,
To ensure robustness when realizing.
Specifically, the timing offset ratio of slow clock can be calculated by following three kinds of modes：
The first：Compare the size of Δ T and default threshold value；If Δ T is less than or equal to default threshold value,
Calculate the ratio of Δ T and T, and using ratio as Δ R；If Δ T be more than default threshold value, calculate default threshold value and
The ratio of T, and using ratio as Δ R.Threshold value herein can make the empirical value obtained by experiment statisticses, such as,
Using the average of Δ T all values in a day as threshold value.
Second：Calculate the average of predetermined number Δ T；Calculate the average of the corresponding T of predetermined number Δ T；Calculate the equal of Δ T
The ratio of the average of value and T, using ratio as Δ R.Arithmetic average be for eliminating the common method of measurement error in statistics,
Calculate simple.
The third：According to the variation tendency of predetermined number Δ T, adjusted value is determined；The ratio of adjusted value and T is calculated, will be compared
Value is used as Δ R.Direction and state estimating that trend adjustment strategy changes according to the sustainable development within the longer term, its specific measure
Using existing method, will not be repeated here.
To sum up, when realizing, measured deviation etc. is taken into consideration, method is more, but thought is still unified
, i.e., the deviation using timing estimate out changes 32K clock alignment values, so as to reach saving hardware calibration, lifting system
The purpose of energy.
Above the step of various methods divide, be intended merely to description it is clear, can be merged into when realizing a step or
Some steps are split, multiple steps are decomposed into, as long as comprising identical logical relation, all in the protection domain of this patent
It is interior；To adding inessential modification in algorithm or in flow or introducing inessential design, but its algorithm is not changed
With the core design of flow all in the protection domain of the patent.
Third embodiment of the invention is related to a kind of calibrating installation of the clock accuracy for terminal, as shown in Fig. 2 bag
Contain：Duration acquisition module, timing offset acquisition module, timing offset ratio computing module, proportionality coefficient acquisition module, clock school
Quasi-mode block.
Wherein, duration acquisition module is used to obtain fast clock closing, the time span T that slow clock works；Specifically, when
Acquisition module long obtains length of one's sleep length, as T after each terminal is waken up from sleep state；Wherein, terminal is in
Fast clock is closed in the sleep state time period, and slow clock works.
Timing offset acquisition module is used to obtain timing offset Δ T of the slow clock in T time length；Paging is received in terminal
Afterwards, channel estimation is carried out to the reception data for receiving paging, the timing offset amount in length of one's sleep length is obtained, as Δ T.
Timing offset ratio computing module is used for according to Δ T and T, is calculated timing offset ratio Δ R；Can directly count
Calculate the ratio of Δ T and T, and using ratio as Δ R.
Proportionality coefficient acquisition module is used to read the proportionality coefficient of slow clock and fast clock；Wherein, proportionality coefficient is initial
Value is obtained by hardware calibration.
Clock alignment module is used to for the proportionality coefficient of reading to subtract timing offset ratio, obtains new proportionality coefficient, complete
The calibration of slow clock accuracy in pairs.
Additionally, what deserves to be explained is, terminal has fast clock and slow clock, and the clock frequency of fast clock is more than slow clock
Clock frequency, fast clock is accurately.It is 26 megahertzs of MHz with the clock frequency of fast clock, the clock frequency of slow clock is
For as a example by 32768 hertz：
The calibrating installation of clock accuracy is also included：The register of one 32, the ratio for storing slow clock and fast clock
Example coefficients R32k/26M, wherein, 16 storage integer parts R high32k/26M_int, low 16 storage fractional parts R32k/26M_floor。
Clock alignment module is further included：Graduation of whole numbers of units departure calculating sub module, decimal unit deviation gauge operator
Module, integer adjustment submodule, decimal adjustment submodule, merging submodule.
Graduation of whole numbers of units departure calculating sub module is used to calculate the departure corresponding to the unit deviation value of integer part
Decimal unit deviation gauge operator module is used to calculate the departure corresponding to the unit deviation value of fractional part
Integer adjusts submodule and decimal adjustment submodule to be used for according to Δ R, respectively the integer part of comparative example coefficient and
Fractional part is adjusted：
Wherein,WithIt is respectively the integer part and fractional part after adjustment；Represent downward
Rounding operation；
Merging submodule is used to merge the integer part after adjustment and fractional part, obtains new proportionality coefficient：
Wherein,It is new proportionality coefficient；<<Represent shifted left computing.
It is seen that, present embodiment is the system embodiment corresponding with first embodiment, and present embodiment can be with
First embodiment is worked in coordination implementation.The relevant technical details mentioned in first embodiment still have in the present embodiment
Effect, in order to reduce repetition, repeats no more here.Correspondingly, the relevant technical details mentioned in present embodiment are also applicable in
In first embodiment.
It is noted that each module involved in present embodiment is logic module, in actual applications, one
Individual logic unit can be a part for a physical location, or a physical location, can also be with multiple physics lists
The combination of unit is realized.Additionally, in order to protrude innovative part of the invention, will not be with solution institute of the present invention in present embodiment
The unit that the technical problem relation of proposition is less close is introduced, but this is not intended that in present embodiment do not exist other lists
Unit.
Four embodiment of the invention is related to a kind of calibrating installation of the clock accuracy for terminal.4th implementation method exists
Further improvement is done on the basis of 3rd implementation method, has mainly been theed improvement is that：In the 4th implementation method, can be by system
Meter method, obtains the timing offset ratio of accurately slow clock, so as to ensure the robustness of clock accuracy calibration.
Specifically, timing offset ratio computing module is further included：Comparison sub-module, the first ratio calculation submodule
Block；Wherein, comparison sub-module is used to compare Δ T with the size of default threshold value；First ratio calculation submodule is more sub
When module judges that Δ T is less than or equal to default threshold value, the ratio of Δ T and T is calculated, and using the ratio as Δ R；And
When comparison sub-module judges that Δ T is more than default threshold value, calculate the ratio of default threshold value and T, and using the ratio as
ΔR。
Or, timing offset ratio computing module is further included：Deviation mean value computation submodule, sleep duration average meter
Operator module, the second ratio calculation submodule；Wherein, deviation mean value computation submodule is used to calculate the average of predetermined number Δ T；
Sleep duration mean value computation submodule is used to calculate the average of the corresponding T of predetermined number Δ T；Second ratio calculation submodule is used for
The ratio of the average of Δ T and the average of T is calculated, using the ratio as Δ R.
Or, timing offset ratio computing module is further included：Trend observation submodule, the 3rd ratio calculation submodule
Block；Wherein, trend observation submodule is used for the variation tendency according to predetermined number Δ T, determines adjusted value；3rd radiometer operator
Module is used to calculate the ratio of adjusted value and T, using the ratio as Δ R.
Because second embodiment is mutually corresponding with present embodiment, therefore present embodiment can be mutual with second embodiment
It is engaged implementation.The relevant technical details mentioned in second embodiment are still effective in the present embodiment, implement second
The technique effect to be reached in mode in the present embodiment similarly it is achieved that in order to reduce repetition, no longer go to live in the household of one's in-laws on getting married here
State.Correspondingly, the relevant technical details mentioned in present embodiment are also applicable in second embodiment.
It will be understood by those skilled in the art that the respective embodiments described above are to realize specific embodiment of the invention,
And in actual applications, can to it, various changes can be made in the form and details, without departing from the spirit and scope of the present invention.
Claims (14)
1. a kind of calibration method of clock accuracy for terminal, the terminal has fast clock and slow clock, and when described fast
More than the clock frequency of the slow clock, the fast clock is accurately to the clock frequency of clock, it is characterised in that comprising following step
Suddenly：
A. obtain the fast clock to close, the time span T that the slow clock works, and the timing in the T time length
Deviation delta T；
B. according to the Δ T and T, it is calculated timing offset ratio Δ R；
C. the proportionality coefficient of the slow clock and the fast clock is read；Wherein, the initial value of the proportionality coefficient passes through hardware
Calibration is obtained；
D. the proportionality coefficient of the reading is subtracted into the timing offset ratio, obtains new proportionality coefficient, completed to slow clock
The calibration of precision.
2. the calibration method of the clock accuracy for terminal according to claim 1, it is characterised in that in the step A
In, comprising following sub-step：
After each terminal is waken up from sleep state, the terminal receives paging, and obtains length of one's sleep length, used as described
T；Wherein, the terminal is in the fast clock in the sleep state time period and closes, and the slow clock works；
Reception data to receiving paging carry out channel estimation, the timing offset amount in length of one's sleep length are obtained, as the Δ
T。
3. the calibration method of the clock accuracy for terminal according to claim 1, it is characterised in that in the step B
In, comprising following sub-step：
Calculate the ratio of the Δ T and the T, and using the ratio as the Δ R.
4. the calibration method of the clock accuracy for terminal according to claim 1, it is characterised in that in the step B
In, comprising following sub-step：
Compare the size of the Δ T and default threshold value；
If the Δ T is less than or equal to default threshold value, the ratio of the Δ T and the T is calculated, and by the ratio
Value is used as the Δ R；
If the Δ T is more than default threshold value, the ratio of the default threshold value and the T is calculated, and will be described
Ratio is used as the Δ R.
5. the calibration method of the clock accuracy for terminal according to claim 1, it is characterised in that in the step B
In, comprising following sub-step：
Calculate the average of predetermined number Δ T；
Calculate the average of the corresponding T of the predetermined number Δ T；
The ratio of the average of the Δ T and the average of the T is calculated, using the ratio as the Δ R.
6. the calibration method of the clock accuracy for terminal according to claim 1, it is characterised in that in the step B
In, comprising following sub-step：
According to the variation tendency of predetermined number Δ T, adjusted value is determined；
The ratio of the adjusted value and the T is calculated, using the ratio as the Δ R.
7. the calibration method of the clock accuracy for terminal according to any one of claim 1 to 6, it is characterised in that institute
It is 26 megahertzs to state the clock frequency of fast clock, and the clock frequency of the slow clock is 32768 hertz；The slow clock and described
The proportionality coefficient R of fast clock32k/26MStored with the registers of 32, wherein, 16 storage integer parts R high32k/26M_int,
Low 16 storage fractional parts R32k/26M_floor；
In the step D, comprising following sub-step：
Calculate the departure corresponding to the unit deviation value of integer part
Calculate the departure corresponding to the unit deviation value of fractional part
According to the Δ R, the integer part and fractional part to the proportionality coefficient are adjusted respectively：
Wherein,WithIt is respectively the integer part and fractional part after adjustment；Expression is rounded downwards
Computing；
Integer part after the adjustment and fractional part are merged, new proportionality coefficient is obtained：
Wherein,It is new proportionality coefficient；<<Represent shifted left computing.
8. a kind of calibrating installation of clock accuracy for terminal, the terminal has fast clock and slow clock, and when described fast
More than the clock frequency of the slow clock, the fast clock is accurately to the clock frequency of clock, it is characterised in that included：Duration
Acquisition module, timing offset acquisition module, timing offset ratio computing module, proportionality coefficient acquisition module, clock alignment module；
The duration acquisition module is used to obtain the fast clock closing, the time span T that the slow clock works；
The timing offset acquisition module is used to obtain the timing offset Δ T in the T time length；
The timing offset ratio computing module is used for according to the Δ T and T, is calculated timing offset ratio Δ R；
The proportionality coefficient acquisition module is used to read the proportionality coefficient of the slow clock and the fast clock；Wherein, the ratio
The initial value of example coefficient is obtained by hardware calibration；
The clock alignment module is used to for the proportionality coefficient of the reading to subtract the timing offset ratio, obtains new ratio
Coefficient, completes the calibration to slow clock accuracy.
9. the calibrating installation of the clock accuracy for terminal according to claim 8, it is characterised in that the duration is obtained
Module obtains length of one's sleep length, as the T after each terminal is waken up from sleep state；Wherein, the end
Closed in the fast clock in the sleep state time period, the slow clock works；
After the terminal receives paging, the reception data to receiving paging carry out channel estimation to the timing offset acquisition module,
Timing departure in length of one's sleep length is obtained, as the Δ T.
10. the calibrating installation of the clock accuracy for terminal according to claim 8, it is characterised in that the timing is inclined
Difference ratio computing module calculates the ratio of the Δ T and T, and using the ratio as the Δ R.
The calibrating installation of 11. clock accuracies for terminal according to claim 8, it is characterised in that the timing is inclined
Difference ratio computing module is included：Comparison sub-module, the first ratio calculation submodule；
The comparison sub-module is used to compare the Δ T with the size of default threshold value；
The first ratio calculation submodule judges that the Δ T is less than or equal to default threshold value in the comparison sub-module
When, calculate the ratio of the Δ T and T, and using the ratio as the Δ R；And judge institute in the comparison sub-module
When stating Δ T more than default threshold value, the ratio of the default threshold value and the T is calculated, and using the ratio as institute
State Δ R.
The calibrating installation of 12. clock accuracies for terminal according to claim 8, it is characterised in that the timing is inclined
Difference ratio computing module is included：Deviation mean value computation submodule, sleep duration mean value computation submodule, the second ratio calculation submodule
Block；
The deviation mean value computation submodule is used to calculate the average of predetermined number Δ T；
The sleep duration mean value computation submodule is used to calculate the average of the corresponding T of the predetermined number Δ T；
The second ratio calculation submodule is used to calculate the ratio of the average of the Δ T and the average of the T, by the ratio
As the Δ R.
The calibrating installation of 13. clock accuracies for terminal according to claim 8, it is characterised in that the timing is inclined
Difference ratio computing module is included：Trend observation submodule, the 3rd ratio calculation submodule；
The trend observation submodule is used for the variation tendency according to predetermined number Δ T, determines adjusted value；
The 3rd ratio calculation submodule is used to calculate the ratio of the adjusted value and the T, using the ratio as described
ΔR。
The calibrating installation of 14. clock accuracy for terminal according to any one of claim 8 to 13, it is characterised in that
The clock frequency of the fast clock is 26 megahertzs, and the clock frequency of the slow clock is 32768 hertz；
Also include：The register of one 32, the proportionality coefficient R for storing the slow clock and the fast clock32k/26M, its
In, 16 storage integer parts R high32k/26M_int, low 16 storage fractional parts R32k/26M_floor；
The clock alignment module is included：It is graduation of whole numbers of units departure calculating sub module, decimal unit deviation gauge operator module, whole
Number adjustment submodule, decimal adjustment submodule, merging submodule；
The graduation of whole numbers of units departure calculating sub module is used to calculate the departure corresponding to the unit deviation value of integer part
The decimal unit deviation gauge operator module is used to calculate the departure corresponding to the unit deviation value of fractional part
The integer adjustment submodule and decimal adjustment submodule are used for according to the Δ R, respectively to the proportionality coefficient
Integer part and fractional part be adjusted：
Wherein,WithIt is respectively the integer part and fractional part after adjustment；Expression is rounded downwards
Computing；
The merging submodule is used to merge the integer part after the adjustment and fractional part, obtains new proportionality coefficient：
Wherein,It is new proportionality coefficient；<<Represent shifted left computing.
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| CN105578586B (en) * | 2014-10-17 | 2019-05-21 | 辰芯科技有限公司 | A kind of synchronization timing device and method |
| CN109155729B (en) * | 2016-05-18 | 2022-04-05 | 日本电信电话株式会社 | Wireless communication system, wireless terminal, and time synchronization method |
| CN105897394B (en) * | 2016-06-16 | 2019-02-15 | 桥弘数控科技（上海）有限公司 | A kind of clock synchronization adjustment method and device |
| CN109643142B (en) * | 2017-08-04 | 2022-08-02 | 深圳市汇顶科技股份有限公司 | Timing method, clock equipment and terminal equipment |
| CN107800388A (en) * | 2017-10-17 | 2018-03-13 | 广东美的制冷设备有限公司 | Control method, control device, storage medium and remote control |
| CN109799872B (en) * | 2018-12-29 | 2020-09-11 | 百富计算机技术（深圳）有限公司 | Method and device for improving awakening precision of low-resolution real-time clock and electronic equipment |
| CN111726450B (en) * | 2019-03-19 | 2021-06-08 | 安克创新科技股份有限公司 | Control method of intelligent express cabinet and intelligent express cabinet |
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| CN101959298A (en) * | 2009-07-17 | 2011-01-26 | 联芯科技有限公司 | Method and device for calibrating slow timing clock and terminal |
| CN102540868A (en) * | 2010-12-31 | 2012-07-04 | 重庆重邮信科通信技术有限公司 | Slow clock crystal frequency compensation method and device for mobile communication terminal |
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| US6691071B2 (en) * | 2002-05-13 | 2004-02-10 | Motorola, Inc. | Synchronizing clock enablement in an electronic device |
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| CN101431816A (en) * | 2008-11-19 | 2009-05-13 | 深圳华为通信技术有限公司 | Frequency difference acquiring method and terminal |
| CN101959298A (en) * | 2009-07-17 | 2011-01-26 | 联芯科技有限公司 | Method and device for calibrating slow timing clock and terminal |
| CN102540868A (en) * | 2010-12-31 | 2012-07-04 | 重庆重邮信科通信技术有限公司 | Slow clock crystal frequency compensation method and device for mobile communication terminal |
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