CN214480603U - Bluetooth clock circuit structure - Google Patents
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- CN214480603U CN214480603U CN202120729837.5U CN202120729837U CN214480603U CN 214480603 U CN214480603 U CN 214480603U CN 202120729837 U CN202120729837 U CN 202120729837U CN 214480603 U CN214480603 U CN 214480603U
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Abstract
The utility model relates to a bluetooth technical field, concretely relates to bluetooth clock circuit structure, include: the digital clock synchronizer comprises a register for controlling the whole digital circuit module, a counter for calculating the period number and a digital clock synchronizer, wherein the register provides a control interface and a software interface for the calculation module; the counter for calculating the number of cycles is used for calculating the number of digital clock cycles with high frequency, high precision and high power consumption corresponding to the digital clock cycles with low frequency, low precision and low power consumption, and storing the calculated number of digital clock cycles into the register; the digital clock synchronizer is used for synchronizing a low-frequency low-precision low-power-consumption digital clock and a high-frequency high-precision high-power-consumption digital clock. The utility model provides high bluetooth clock's accuracy, greatly reduced the consumption of bluetooth chip in the sleep stage.
Description
Technical Field
The utility model relates to a bluetooth technical field, concretely relates to bluetooth clock circuit structure.
Background
Bluetooth has obtained rapid development as a wireless link technology in the last decade, and the form of product is also more and more abundant, and people also are higher and higher to the use experience requirement of bluetooth product, require stable interlinkage promptly also to require the continuation of journey of long time. Each bluetooth unit has an internal system clock that determines the timing and frequency hopping of the receiver and transmitter. Maintaining the accuracy of the bluetooth clock is of high significance for the stability of the bluetooth link, but the power consumption paid for in maintaining the accuracy of the bluetooth clock is expected to be as low as possible to extend endurance. In the prior art, the power consumption of a low-frequency low-precision low-power-consumption digital clock used in a sleep state of a Bluetooth chip can be very low, but the accuracy of the Bluetooth clock is difficult to maintain, and if the high-frequency high-precision high-power-consumption digital clock is used for ensuring the accuracy of the Bluetooth clock, the cruising ability of the Bluetooth device is inevitably reduced.
SUMMERY OF THE UTILITY MODEL
In order to solve the problem, the utility model provides a bluetooth clock circuit structure.
A bluetooth clock circuit structure, comprising: the digital clock synchronizer comprises a register for controlling the whole digital circuit module, a counter for calculating the period number and a digital clock synchronizer, wherein the register provides a control interface and a software interface for the calculation module; the counter for calculating the number of cycles is used for calculating the number of digital clock cycles with high frequency, high precision and high power consumption corresponding to the digital clock cycles with low frequency, low precision and low power consumption, and storing the calculated number of digital clock cycles into the register; the digital clock synchronizer is used for synchronizing a low-frequency low-precision low-power-consumption digital clock and a high-frequency high-precision high-power-consumption digital clock.
Further, the registers include a first register, a second register, a third register, and an operation mode selection register,
the first register is readable and writable by software, and is used for storing a register of digital clock period N with low frequency, low precision and low power consumption. When the bluetooth device is in a sleep state, when the low-frequency low-precision low-power-consumption digital clock cycle reaches the preset sleep time cycle in the first register, the bluetooth device is awakened, the bluetooth device enters an activated state from the sleep state, and the bluetooth system runs under the high-frequency high-precision high-power-consumption digital clock, so that the calculation module in the step S1 is automatically triggered.
The second register is readable by software, and an indication signal is stored in the second register and used for indicating whether a value calculated by the whole digital circuit module is effective or not, namely indicating whether the number of high-frequency high-precision high-power-consumption digital clock cycles corresponding to N low-frequency low-precision low-power-consumption digital clock cycles stored in the third register is effective or not;
the third register is readable by software, and is used for storing high-frequency, high-precision and high-power-consumption digital clock cycles corresponding to N low-frequency, low-precision and low-power-consumption digital clock cycles;
the operation mode selection register is readable and writable by software, comprises a manual mode register and an automatic mode register and is mainly used for controlling the operation mode of the module and selecting an automatic trigger mode or a manual trigger mode.
Furthermore, the bluetooth device which is powered on after being started for the first time runs in a manual trigger mode, and when the bluetooth device enters an active state from a sleep state, the bluetooth device runs in an automatic trigger mode.
The utility model discloses following beneficial effect has:
1. the utility model discloses a bluetooth chip is all in sleep state except receiving and dispatching the package stage, the utility model discloses a digital clock of low frequency, low accuracy, low-power consumption for bluetooth chip is at the consumption greatly reduced of sleep stage.
2. Inaccurate nature to the bluetooth clock that the sleep state leads to, the utility model discloses a digital clock cycle of high frequency high accuracy high power consumption has carried out the conversion and has obtained avoiding to the bluetooth chip of feasible greatly limit increase bluetooth equipment's time of endurance when guaranteeing bluetooth clock's accuracy.
Drawings
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
Fig. 1 is a schematic diagram of a bluetooth clock circuit structure according to the present invention.
Detailed Description
The technical solutions in the embodiments will be described clearly and completely with reference to the drawings in the embodiments, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without any creative work belong to the protection scope of the present invention.
This embodiment provides a digital circuit structure of a bluetooth clock, where the bluetooth clock circuit structure is used to calculate the number of high-frequency high-precision high-power-consumption digital clock cycles corresponding to N low-frequency low-precision low-power-consumption digital clock cycles.
In a preferred embodiment, the digital circuit architecture of the bluetooth clock comprises: the digital clock synchronizer comprises a structure register for controlling the whole digital circuit structure, a counter for calculating the number of cycles and a digital clock synchronizer.
In this embodiment, the register provides a control interface and a software interface for the digital circuit structure module of the bluetooth clock. The register includes: a first register, a second register, a third register and an operation mode selection register.
The first register is readable and writable by software and is used for storing a register with low frequency, low precision and low power consumption digital clock period N; that is, the first register has a threshold cycle number, when the bluetooth device is in a sleep state, when the digital clock cycle with low frequency, low precision and low power consumption reaches the preset sleep time cycle in the first register, the bluetooth device is awakened, the bluetooth device enters an active state from the sleep state, and the bluetooth system runs under the digital clock with high frequency, high precision and high power consumption, and automatically triggers the calculation module in step S1.
The second register is readable by software, and the second register is used for storing an indication signal, where the indication signal is used to indicate whether a value calculated by the whole digital circuit module in fig. 1 is valid, that is, whether the number of high-frequency, high-precision, and high-power digital clock cycles corresponding to the N low-frequency, low-precision, and low-power digital clock cycles stored in the third register is valid. Illustratively, the initial value of the indication signal in the second register is 0, the calculation module starts a corresponding calculation process after triggering, and when the calculation is completed, the value of the indication signal in the second register becomes 1, and when the software reads that the value of the second register is 1, the value stored in the third register is taken out for operation.
The third register is readable by software, and the third register is a register used for storing high-frequency, high-precision and high-power-consumption digital clock cycles corresponding to the N low-frequency, low-precision and low-power-consumption digital clock cycles. The value stored in the third register is dynamically updated, the bluetooth device is updated once it enters an active state, and the updating mode includes: and summing the high-frequency high-precision high-power-consumption digital clock cycles corresponding to the N low-frequency low-precision low-power-consumption digital clock cycles calculated in the current activation state with the high-frequency high-precision high-power-consumption digital clock cycles corresponding to the N low-frequency low-precision low-power-consumption digital clock cycles stored in the third register, averaging, and storing the average as a new global variable in the third register.
The operation mode selection register is readable and writable by software, comprises a manual mode register and an automatic mode register and is mainly used for controlling the operation mode of the module and selecting an automatic trigger mode or a manual trigger mode.
In this embodiment, the counter for calculating the number of cycles is mainly used to calculate the number of high-frequency, high-precision and high-power-consumption digital clock cycles corresponding to the low-frequency, low-precision and low-power-consumption digital clock cycles, and store the calculated number of digital clock cycles in the third register. The counter corresponds to the calculation block in fig. 1, and thus the "calculation block" appearing in the present embodiment may be equivalent to the counter.
In this embodiment, the digital clock synchronizer is configured to synchronize a low-frequency, low-precision, low-power consumption digital clock with a high-frequency, high-precision, high-power consumption digital clock, and synchronize signals between two clock domains to reduce the occurrence of a metastable state.
For example, the present embodiment provides a specific digital circuit structure of the bluetooth clock, and as shown in fig. 1, the present invention provides a schematic diagram of a digital circuit structure involved in the method of the present invention. The digital circuit structure of the bluetooth clock comprises an input pin wakeup, an input pin ref _ clk, an input pin rc _ clk, an input pin clknb, an input pin auto/manual, an output pin cal _ done, an output pin cal _ result, a register, a synchronizer and a counter (corresponding to the computing module in fig. 1).
In this embodiment, the registers are the first register, the second register, the third register and the operation mode selection register. The synchronizer is a low-frequency low-precision low-power-consumption digital clock and a high-frequency high-precision high-power-consumption digital clock synchronizer, and is mainly used for synchronizing signals between two clock domains so as to reduce the occurrence of a metastable state. The counter is used for calculating the number of the high-frequency high-precision high-power-consumption digital clock cycles corresponding to the low-frequency low-precision low-power-consumption digital clock cycles and storing the number of the high-frequency high-precision high-power-consumption digital clock cycles in the third register.
The digital circuit structure of the Bluetooth clock further comprises pins:
the wakeup pin is an input pin of the circuit structure and is used for inputting a wakeup _ up signal, and the wakeup _ up signal is a signal of a digital clock domain with low frequency, low precision and low power consumption and is used for indicating whether the system is in a sleep state at the moment. wakeup pin one end is connected with the synchronous ware, and the other end is connected with the awakening module of bluetooth equipment.
The rc _ clk pin is used for transmitting an rc _ clk signal, and the rc _ clk signal is a low-frequency, low-precision and low-power-consumption digital clock calculated by the calculation module. One end of an rc _ clk pin is connected with the first register, and the other end of the rc _ clk pin is connected with the computing module.
The ref _ clk pin is used for transmitting a ref _ clk signal, which is a high-frequency, high-precision and high-power-consumption digital clock calculated by the calculation module. One end of an rc _ clk pin is connected with the third register, and the other end of the rc _ clk pin is connected with the computing module.
The clknb pin is used for transmitting a clknb signal which is a low-frequency, low-precision and low-power-consumption digital clock cycle N calculated by the calculation module. And one end of the clknb pin is connected with the first register, and the other end of the clknb pin is connected with the computing module.
The auto/manul pin is used for transmitting an auto/manul signal, and the auto/manul signal is used for controlling whether the operation mode of the module is selected to be automatically triggered or manually triggered. One end of the auto/mangle pin is connected with the operation mode selection register, and the other end of the auto/mangle pin is connected with the computing module.
The cal _ done pin is used to transmit a cal _ done signal, which is used to inform the software whether the final calculation result stored in the third register can be used at this time. One end of the cal _ done pin is connected with the second register, and the other end of the cal _ done pin is connected with the computing module.
The cal _ result pin is used for transmitting a cal _ result signal, and the cal _ result signal is N digital clock cycles with low frequency, low precision and low power consumption, corresponding to the high-frequency, high-precision and high power consumption digital clock cycles.
In this embodiment, the bluetooth device that is powered on when being powered on for the first time operates in the manual trigger mode, and when the bluetooth device enters the active state from the sleep state, the bluetooth device operates in the automatic trigger mode. That is to say, the manual trigger mode is mainly used when the bluetooth device is powered on for the first time and N digital clock cycles with low frequency, low precision and low power consumption corresponding to the digital clock cycles with high frequency, high precision and high power consumption are calculated for multiple times; the automatic trigger mode is mainly used when the system automatically performs N digital clock cycles with low frequency, low precision and low power consumption corresponding to the digital clock cycles with high frequency, high precision and high power consumption each time the system is woken up.
In the manual trigger mode, software first configures the first register, and then configures the manual mode register to start the whole digital circuit module shown in fig. 1. The calculation process comprises the following steps: and recording the number of digital clock cycles with low frequency, low precision and low power consumption by a counter, stopping counting when the number of cycles is equal to the threshold number of cycles of the first register, simultaneously counting the number of digital clock cycles with high frequency, high precision and high power consumption in the time period, and finally storing the number of digital clock cycles with high frequency, high precision and high power consumption in a third register.
In the auto-triggering mode, the entire digital circuit block in fig. 1 is triggered by the wakeup signal, and the software must configure the first register in advance before the trigger comes. The wakeup signal is a signal of a digital clock domain with low frequency, low precision and low power consumption, and needs to be processed by a synchronizer before entering the counter, the synchronizer is firstly utilized to convert the digital clock domain with low frequency, low precision and low power consumption into a digital clock domain with high frequency, high precision and high power consumption, and then the digital clock domain is input into the counter to participate in the logic operation of the digital clock domain with high frequency, high precision and high power consumption, so that the generation of a metastable state is reduced. The calculation process comprises the following steps: and recording the number of digital clock cycles with low frequency, low precision and low power consumption by a counter, stopping counting when the number of cycles is equal to the threshold number of cycles of the first register, simultaneously counting the number of digital clock cycles with high frequency, high precision and high power consumption in the time period, and finally storing the number of digital clock cycles with high frequency, high precision and high power consumption in a third register.
Above-mentioned technical scheme has only embodied the utility model discloses technical scheme's preferred technical scheme, some changes that this technical field's technical personnel probably made to some parts wherein have all embodied the utility model discloses a principle belongs to within the protection scope of the utility model.
Furthermore, the terms "first", "second", "third", "fourth" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated, whereby the features defined as "first", "second", "third", "fourth" may explicitly or implicitly include at least one such feature.
The foregoing is directed to embodiments of the present invention, and it is appreciated that those skilled in the art will be able to devise various changes, modifications, substitutions and alterations without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents.
Claims (3)
1. A bluetooth clock circuit structure, comprising: the digital clock synchronizer comprises a register for controlling the whole digital circuit module, a counter for calculating the period number and a digital clock synchronizer, wherein the register provides a control interface and a software interface for the calculation module; the counter for calculating the number of cycles is used for calculating the number of digital clock cycles with high frequency, high precision and high power consumption corresponding to the digital clock cycles with low frequency, low precision and low power consumption, and storing the calculated number of digital clock cycles into the register; the digital clock synchronizer is used for synchronizing a low-frequency low-precision low-power-consumption digital clock and a high-frequency high-precision high-power-consumption digital clock.
2. A Bluetooth clock circuit arrangement according to claim 1, wherein the registers include a first register, a second register, a third register and an operation mode selection register,
the first register is readable and writable by software and is used for storing a register with low frequency, low precision and low power consumption digital clock period N;
the second register is readable by software, and an indication signal is stored in the second register and used for indicating whether a value calculated by the whole digital circuit module is effective or not, namely indicating whether the number of high-frequency high-precision high-power-consumption digital clock cycles corresponding to N low-frequency low-precision low-power-consumption digital clock cycles stored in the third register is effective or not;
the third register is readable by software, and is used for storing high-frequency, high-precision and high-power-consumption digital clock cycles corresponding to N low-frequency, low-precision and low-power-consumption digital clock cycles;
the operation mode selection register is readable and writable by software, comprises a manual mode register and an automatic mode register and is mainly used for controlling the operation mode of the module and selecting an automatic trigger mode or a manual trigger mode.
3. The bluetooth clock circuit structure of claim 2, wherein the bluetooth device that is powered on for the first time is operated in the manual trigger mode, and when the bluetooth device enters the active state from the sleep state, the bluetooth device is operated in the automatic trigger mode.
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| CN113079497A (en) * | 2021-04-09 | 2021-07-06 | 思澈科技(上海)有限公司 | Calibration method and circuit structure of Bluetooth clock |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113079497A (en) * | 2021-04-09 | 2021-07-06 | 思澈科技(上海)有限公司 | Calibration method and circuit structure of Bluetooth clock |
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