CN108282186B - A kind of UART communication system, method, equipment and computer storage medium - Google Patents
A kind of UART communication system, method, equipment and computer storage medium Download PDFInfo
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- CN108282186B CN108282186B CN201810187615.8A CN201810187615A CN108282186B CN 108282186 B CN108282186 B CN 108282186B CN 201810187615 A CN201810187615 A CN 201810187615A CN 108282186 B CN108282186 B CN 108282186B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a kind of UART communication systems, on the basis of existing UART communication system, increase the low speed UART directly connecting with initial clock source, since low speed UART is directly connect with initial clock source, so the working clock frequency of low speed UART is minimum, accordingly, the frequency of low speed UART sending and receiving data at work is minimum, the power consumed when sending and receiving data is minimum, allow a kind of UART communication system disclosed by the invention by low speed UART work under low-power consumption environment, compared with prior art, the power consumption of UART communication system can be reduced to a certain extent.A kind of UART communication means, equipment and computer storage medium disclosed by the invention also solve corresponding technical problem.
Description
Technical field
The present invention relates to fields of communication technology, more specifically to a kind of UART communication system, method, equipment and meter
Calculation machine storage medium.
Background technique
(Universal Asynchronous Receiver/Transmitter, universal asynchronous receiving-transmitting pass existing UART
Defeated device) in system, each UART passes through APB (Advanced Peripheral Bus, external bus) and DMA (Direct
Memory Access, direct memory access) it connects, DMA passes through AHB (Advanced High Performance Bus, height
Grade high performance bus) it is connected with MCU (Microcontroller Unit, micro-control unit), MCU passes through ahb bus and high speed
Peripheral hardware connection, high-speed peripheral mentioned here includes GPIO (General Purpose Input Output, universal input/defeated
Out), SRAM (Static Random Access Memory, static random access memory), FLASH etc.；32KXTAL
The output port of (32K external crystal-controlled oscillation) is connect with the input terminal of PLL times of frequency module, and the output end and high speed of PLL times of frequency module are outer
If, DMA and DIV divide exactly the input terminal connection of module, the output end that DIV divides exactly module is connect with each UART.
However, it is larger to there is a problem of that power consumption consumes during application existing UART system.
It is asked in conclusion the power consumption for how reducing existing UART system is that current those skilled in the art are urgently to be resolved
Topic.
Summary of the invention
The object of the present invention is to provide a kind of UART communication system, can solve how to reduce to a certain extent existing
The technical issues of power consumption of UART system.The present invention also provides a kind of UART communication means, equipment and computer storage mediums.
To achieve the goals above, the invention provides the following technical scheme:
A kind of UART communication system, with MCU, DMA, high-speed peripheral, ahb bus, APB bus, the first preset quantity
High Speed UART, initial clock source, PLL times of frequency module, DIV divide exactly module, the low speed UART including the second preset quantity；
The first end of the DMA is connect by the ahb bus with the MCU, and the second end of the DMA passes through described
APB bus is connect with High Speed UART described in each, each described low speed UART；The high-speed peripheral is total by the AHB
Line is connect with MCU；
The output end in the initial clock source respectively with the input terminal of the PLL times of frequency module, each described low speed
UART connection；The output end and the high-speed peripheral, the DMA, the DIV of the PLL times of frequency module divide exactly the input of module
End connection；The output end that the DIV divides exactly module is connect with High Speed UART described in each；
Wherein, the working clock frequency of the High Speed UART is higher than the working clock frequency of the low speed UART.
It preferably, further include the register of the second preset quantity, each described register has the first preset quantity
Receive pin；
For register described in any one, the reception pin of the first preset quantity of the register is default with first respectively
The reception pin of the High Speed UART of quantity connects one to one；The output pin of the register low speed corresponding with itself
The reception pin of UART connects.
Preferably, first preset quantity is four, and second preset quantity is two.
Preferably, the high-speed peripheral includes GPIO, SRAM, FLASH.
Preferably, the initial clock source is 32KHz clock source.
A kind of UART communication means, applied in as above any UART communication system, comprising:
When the source address of the DMA is the reception pin of low speed UART, it is received that the DMA caches the low speed UART
Data, and after itself present frame, the interior data cached of itself present frame are transmitted to the MCU.
Preferably, further includes:
When the source address of DMA is the reception pin of High Speed UART, the DMA caches the received number of High Speed UART
According to, and after itself present frame, the interior data cached of itself present frame are transmitted to MCU.
Preferably, further includes:
When the MCU in a dormant state when, the MCU detects the reception pin or the low speed of the High Speed UART
Whether the reception pin of UART generates failing edge, if so, controlling itself into working condition.
A kind of UART communication equipment, comprising:
Memory, for storing computer program；
Processor, the step of as above any described UART communication means is realized when for executing the computer program.
A kind of computer storage medium is stored with computer program, the computer journey in the computer storage medium
The step of as above any described UART communication means is realized when sequence is executed by processor.
A kind of UART communication system provided by the invention increases directly on the basis of existing UART communication system
The low speed UART being connect with initial clock source, since low speed UART is directly connect with initial clock source, so the work of low speed UART
Make that clock frequency is minimum, correspondingly, the frequency of low speed UART sending and receiving data at work is minimum, power that when sending and receiving data consumes
It is minimum, allow a kind of UART communication system provided by the invention by low speed UART work under low-power consumption environment, and it is existing
There is technology to compare, the power consumption of UART communication system can be reduced to a certain extent.A kind of UART communication party provided by the invention
Method, equipment and computer storage medium also solve corresponding technical problem.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of structural schematic diagram of UART communication system provided in an embodiment of the present invention；
Fig. 2 is a kind of another structural schematic diagram of UART communication system provided in an embodiment of the present invention；
Fig. 3 is a kind of flow chart of UART communication means provided in an embodiment of the present invention；
Fig. 4 is that the edge UART wakes up MCU schematic diagram in a kind of UART communication means provided in an embodiment of the present invention；
Fig. 5 is that low speed UART wakes up the process of MCU in a kind of UART communication means provided by the invention in practical application
Figure；
Fig. 6 is a kind of structural schematic diagram of UART communication equipment provided in an embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Referring to Fig. 1, Fig. 1 is a kind of structural schematic diagram of UART communication system provided in an embodiment of the present invention.
A kind of UART communication system provided in an embodiment of the present invention has MCU101, DMA102, high-speed peripheral 103, AHB
Bus 104, APB bus 105, the High Speed UART 106 of the first preset quantity, initial clock source 107, PLL times of frequency module 108, DIV
Divide exactly module 109, the low speed UART110 including the second preset quantity；
The first end of DMA102 is connect by ahb bus 104 with MCU101, and the second end of DMA102 passes through APB bus 105
It is connect with each High Speed UART 106, each low speed UART110；High-speed peripheral 103 is connected by ahb bus 104 and MCU101
It connects；
The output end in initial clock source 107 connects with the input terminal of PLL times of frequency module 108, each low speed UART110 respectively
It connects；The output end of PLL times of frequency module 108 is connect with high-speed peripheral 103, DMA102, DIV input terminal for dividing exactly module 109；DIV
The output end for dividing exactly module 109 is connect with each High Speed UART 106；
Wherein, the working clock frequency of High Speed UART is higher than the working clock frequency of low speed UART.
It should be pointed out that High Speed UART mentioned here and low speed UART are a kind of opposite saying, the work of High Speed UART
Clock frequency is higher than the working clock frequency of low speed UART, and the working clock frequency of UART is the clock connected by itself
What frequency determined, so in practical application, it can judge that UART is at a high speed by judge the frequency of the clock of UART connection
UART or low speed UART, it is assumed that there are two UART, are denoted as A and B respectively, if the frequency of the clock of A connection is higher than B, A is
High Speed UART, B are low speed UART；Specifically, the High Speed UART in the present invention refers to that the output end for dividing exactly module with DIV connects
The UART connect, the present invention in low speed UART refer to the UART connecting with initial clock source.The total quantity of High Speed UART and low
The total quantity of fast UART can be determine according to actual needs.
A kind of UART communication system provided by the invention increases directly on the basis of existing UART communication system
The low speed UART being connect with initial clock source, since low speed UART is directly connect with initial clock source, so the work of low speed UART
Make that clock frequency is minimum, correspondingly, the frequency of low speed UART sending and receiving data at work is minimum, power that when sending and receiving data consumes
It is minimum, allow a kind of UART communication system provided by the invention by low speed UART work under low-power consumption environment, and it is existing
There is technology to compare, the power consumption of UART communication system can be reduced to a certain extent.
Referring to Fig. 2, Fig. 2 is a kind of another structural schematic diagram of UART communication system provided in an embodiment of the present invention.?
In Fig. 2, RX0, RX1, RX2, RX3 are the multiplexing pins of High Speed UART and low speed UART；32KXTAL is initial clock source；
PLL is PLL times of frequency module；DIV is that DIV divides exactly module；UART0, UART1, UART2, UART3 are High Speed UART；
UART32K0, UART32K1 are low speed UART；AHB Bus is ahb bus；APB Bus is APB bus；HCLK is
The clock signal of PLL times of frequency module output supplies clock signal for high performance bus；PCLK is that DIV divides exactly module output
Clock signal supplies clock signal for high-performance peripheral bus.
It can also include the register of the second preset quantity in a kind of UART communication system provided in an embodiment of the present invention,
Each register has the reception pin of the first preset quantity；
For any one register, the reception pin of the first preset quantity of the register height with the first preset quantity respectively
The reception pin of fast UART connects one to one；The reception pin of the output pin of register low speed UART corresponding with itself connects
It connects.
, can also be by the reception pin multiplexing of High Speed UART and low speed UART in practical application, and then pin resource is saved,
Only can also need to change software in the case where not changing hardware, can meet different application demands, save the development cycle and
Hardware cost, specific implementation process can be refering to the present embodiment, can also be by High Speed UART and low speed UART in concrete application scene
The default feature of the reception pin of multiplexing is set as GPIO function.It should be pointed out that the quantity of register and the quantity one of low speed UART
It causes, and the two corresponds, the quantity of the reception pin of each register is consistent with the quantity of High Speed UART, and any one is deposited
The reception pin one-to-one correspondence for receiving pin and High Speed UART of device, i.e. each reception pin of any one register are respectively connected with
One High Speed UART, and the High Speed UART of any two reception pin connection of the register is different；With UART32K0 in Fig. 2
For corresponding register, it is assumed that the reception pin of the register from top to bottom is followed successively by the first reception pin, the second reception is drawn
Foot, third receive pin and the 4th and receive pin, then the first of the register receives pin and be connected with the reception pin of UART3
Connect, second reception pin of the register is connected with the reception pin of UART2, the third of the register receive pin with
The reception pin of UART1 is connected, and the 4th reception pin of the register is connected with the reception pin of UART0.
In a kind of UART communication system provided in an embodiment of the present invention, the first preset quantity is four, and the second preset quantity is
Two.
In practical application, in a kind of UART communication system provided in an embodiment of the present invention, the quantity of High Speed UART can be
4, the quantity of low speed UART can be 2, can make a kind of UART communication system provided in an embodiment of the present invention can in this way
To meet most of requirements, and a kind of UART communication system provided in an embodiment of the present invention can be reduced to a certain extent
Overall power.
In a kind of UART communication system provided in an embodiment of the present invention, high-speed peripheral may include GPIO, SRAM,
FLASH。
In practical application, the high-speed peripheral in a kind of UART communication system provided in an embodiment of the present invention may include
GPIO, SRAM, FLASH etc., the functional mode and IO of each pin of GPIO managing I/O are multiplexed function, and SRAM, FLASH are program
Storage, operation etc. provide condition, can enrich a kind of UART communication system provided in an embodiment of the present invention to a certain extent
Function, and then improve its applicability.
In a kind of UART communication system provided in an embodiment of the present invention, initial clock source can be 32KHz clock source.
In practical application, the initial clock source in a kind of UART communication system provided in an embodiment of the present invention can be
32KHz clock source.
The present invention also provides a kind of UART communication means, with a kind of UART communication provided in an embodiment of the present invention
The correspondence effect that system has.Please referring to 3, Fig. 3 is a kind of flow chart of UART communication means provided in an embodiment of the present invention.
It is logical to be applied to UART described in any embodiment as above for a kind of UART communication means provided in an embodiment of the present invention
In letter system, it may comprise steps of:
Step S101: when the source address of DMA is the reception pin of low speed UART, DMA caches the received number of low speed UART
According to；
Step S102:DMA transmits the interior data cached of itself present frame to MCU after itself present frame.
In practical application, no matter MCU be it is in running order be in dormant state, DMA and low speed in the present embodiment
The mode that UART cooperates is equally applicable to both of these case, and the mode that DMA and low speed UART cooperates can make
UART communication system it is least in power-consuming, in concrete application scene, in order to further decrease one kind provided in an embodiment of the present invention
The power consumption of UART communication system can also cancel the transmitter of low speed UART.In addition, the length of DMA transfer data can basis
Actual needs determines.
In a kind of UART communication means provided in an embodiment of the present invention, can also include:
When the source address of DMA is the reception pin of High Speed UART, the DMA caches the received data of High Speed UART, and
After itself present frame, the interior data cached of itself present frame are transmitted to MCU.
In practical application, no matter MCU is that dormant state is in for working condition, DMA and high speed in the present embodiment
The mode that UART cooperates is equally applicable to both of these case, and when MCU is in running order, DMA and High Speed UART are coordinated
The mode of work can guarantee the timeliness and reliability of serial ports sending and receiving data, together in the higher occasion of UART interrupt priority level
When take into account MCU to the response characteristic and processing capacity of other tasks.It should be pointed out that in practical application, it can be with flexible choice UART
The working method of communication system, for example in the case where harsh to power consumption requirements, DMA and low speed UART is selected to cooperate
Working method selects the working method of DMA and High Speed UART collaborative work in the higher situation of performance requirement to system
Deng.
Referring to Fig. 4, Fig. 4 is that the edge UART wake-up MCU shows in a kind of UART communication means provided in an embodiment of the present invention
It is intended to.The end RX generates failing edge, then starts to receive data, Parity (even-odd check) is carried out after the completion of data receiver, to surprise
After the completion of even parity check, terminate the reception of data；In the process, it after MCU detects the failing edge that the end RX generates, just wakes up certainly
Body.
In a kind of UART communication means provided in an embodiment of the present invention, can also include:
When MCU in a dormant state when, the reception pin or the reception pin of low speed UART of MCU detection High Speed UART are
No generation failing edge, if so, controlling itself into working condition.
In practical application, when MCU is in suspend mode, in order to wake up MCU as early as possible, it can be waken up using the edge UART
Mode wakes up MCU, and detailed process please refers to the present embodiment.It should be pointed out that MCU detection High Speed UART reception pin or
When the reception pin of low speed UART does not generate reception pin, still in a dormant state, connecing for High Speed UART is still executed at this time
The step of whether the reception pin of spasm foot or low speed UART generate failing edge；MCU after entering operating mode by suspend mode,
Buffer data can be received to DMA to handle；In practical application, MCU is being waken up behind, can also judge DMA frame
Whether interrupt requests are overtime, if overtime, issue overtime warning；If having not timed out, judge whether to receive parity error
Interrupt requests are handled DMA buffer data if not receiving parity error interrupt requests；If receiving surprise
Even parity check error interrupt request then carries out parity error processing, and returns to execution judges whether DMA frame interrupt requests are overtime
The step of.In concrete application scene, in the case where waking up the lower situation of rate request to MCU, MCU can also judge DMA or high speed
Whether UART or low speed UART generate interruption, if so, judging that itself need to enter working condition, and then control itself into work
Make state.
In practical application, in order to guarantee to wake up the accuracy of MCU, reception pin or low speed of the MCU in detection High Speed UART
After the reception pin of UART generates failing edge, MCU controls itself and enters before working condition, can also judge High Speed UART
Whether the low level after receiving the reception pin generation failing edge of pin or low speed UART meets Configuration of baud rate, if so, holding
The step of being advanced into working condition.
Referring to Fig. 5, Fig. 5 is that low speed UART wakes up in a kind of UART communication means provided by the invention in practical application
The flow chart of MCU.
The process that low speed UART wakes up MCU in a kind of UART communication means provided by the invention in practical application can wrap
Include following steps:
Step S201: integrated chip carries out initial setting up under extraneous control, and initial setting up mentioned here includes being
System clock setting, opening house dog, opening power detecting configuration etc.；
Step S202: integrated chip judges whether the voltage of itself is less than 2.5V, if so, thening follow the steps S203；If
It is no, then follow the steps S204；
Step S203: integrated chip carries out supply voltage alarm, and returns to step S201；
The source address of itself is set as the reception pin of low speed UART by step S204:DMA under extraneous control, by itself
Destination address be set as the region SRAM defined inside MCU, by the request source of itself be set as low speed UART receive byte flag, packet
It is long to be defined as 64*16 with frame length；
Step S205:MCU makes itself in a dormant state by dormancy instruction；
Whether step S206:MCU detects first failing edge of RX pin, if so, thening follow the steps S207；If it is not, then
Execute step S205；
Step S207:MCU judges whether the low level after failing edge meets Configuration of baud rate, if so, thening follow the steps
S208；If it is not, thening follow the steps S205；
Step S208:MCU wakes up itself.
The present invention also provides a kind of UART communication equipment and computer storage mediums, all have the embodiment of the present invention and mention
A kind of correspondence effect that UART communication means has supplied.Referring to Fig. 6, Fig. 6 is a kind of UART provided in an embodiment of the present invention
The structural schematic diagram of communication equipment.
A kind of UART communication equipment provided in an embodiment of the present invention may include:
Memory 201, for storing computer program；
Processor 202 realizes UART communication means described in any embodiment as above when for executing computer program
The step of.
A kind of computer storage medium provided in an embodiment of the present invention is stored with computer journey in computer storage medium
Sequence, the step of UART communication means described in any embodiment as above is realized when computer program is executed by processor.
Relevant portion says in a kind of UART communication means provided in an embodiment of the present invention, equipment and computer storage medium
The bright detailed description for referring to corresponding part in a kind of UART communication system provided in an embodiment of the present invention, details are not described herein.
In addition, in above-mentioned technical proposal provided in an embodiment of the present invention with correspond to the consistent portion of technical solution realization principle in the prior art
Divide and unspecified, in order to avoid excessively repeat.
The foregoing description of the disclosed embodiments can be realized those skilled in the art or using the present invention.To this
A variety of modifications of a little embodiments will be apparent for a person skilled in the art, and the general principles defined herein can
Without departing from the spirit or scope of the present invention, to realize in other embodiments.Therefore, the present invention will not be limited
It is formed on the embodiments shown herein, and is to fit to consistent with the principles and novel features disclosed in this article widest
Range.
Claims (10)
1. a kind of UART communication system, with MCU, DMA, high-speed peripheral, ahb bus, APB bus, the first preset quantity height
Fast UART, initial clock source, PLL times of frequency module, DIV divide exactly module, which is characterized in that the low speed including the second preset quantity
UART；
The first end of the DMA is connect by the ahb bus with the MCU, and the second end of the DMA is total by the APB
Line is connect with High Speed UART described in each, each described low speed UART；The high-speed peripheral by the ahb bus with
MCU connection；
The output end in the initial clock source connects with the input terminal of the PLL times of frequency module, each described low speed UART respectively
It connects；The output end of the PLL times of frequency module is connect with the high-speed peripheral, the DMA, the DIV input terminal for dividing exactly module；
The output end that the DIV divides exactly module is connect with High Speed UART described in each；
Wherein, the working clock frequency of the High Speed UART is higher than the working clock frequency of the low speed UART.
2. system according to claim 1, which is characterized in that it further include the register of the second preset quantity, each institute
Stating register has the reception pin of the first preset quantity；
For register described in any one, the reception pin of the first preset quantity of the register respectively with the first preset quantity
The reception pin of High Speed UART connect one to one；The output pin of the register low speed UART corresponding with itself
Reception pin connection.
3. system according to claim 1, which is characterized in that first preset quantity is four, second present count
Amount is two.
4. system according to claim 1, which is characterized in that the high-speed peripheral includes GPIO, SRAM, FLASH.
5. system according to claim 1, which is characterized in that the initial clock source is 32KHz clock source.
6. a kind of UART communication means, which is characterized in that be applied to UART communication system as described in any one of claims 1 to 3
In system, comprising:
When the source address of the DMA is the reception pin of low speed UART, the DMA caches the received number of low speed UART
According to, and after itself present frame, the interior data cached of itself present frame are transmitted to the MCU.
7. according to the method described in claim 6, it is characterized by further comprising:
When the source address of DMA is the reception pin of High Speed UART, the DMA caches the received data of High Speed UART, and
After itself present frame, the interior data cached of itself present frame are transmitted to MCU.
8. according to the method described in claim 6, it is characterized by further comprising:
When the MCU in a dormant state when, what the MCU detected the High Speed UART receives pin or the low speed UART
Receive whether pin generates failing edge, if so, controlling itself into working condition.
9. a kind of UART communication equipment characterized by comprising
Memory, for storing computer program；
Processor realizes such as claim 6 to 8 described in any item UART communication means when for executing the computer program
The step of.
10. a kind of computer storage medium, which is characterized in that be stored with computer program, institute in the computer storage medium
State the step of UART communication means as described in any item such as claim 6 to 8 are realized when computer program is executed by processor.
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| CN111064647B (en) * | 2019-12-09 | 2021-07-16 | 浙江威星智能仪表股份有限公司 | UART communication device with low power consumption |
| CN111198776A (en) * | 2019-12-25 | 2020-05-26 | 上海亮牛半导体科技有限公司 | Method for preventing UART (universal asynchronous receiver/transmitter) from receiving lost data during deep sleep of MCU (microprogrammed control unit) |
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| CN103713543A (en) * | 2013-12-18 | 2014-04-09 | 国核自仪系统工程有限公司 | Multi-serial-port parallel processing framework based on FPGA |
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