CN101387896B - Method and device for implementing system-on-chip wake and sleep function in SOC - Google Patents
Method and device for implementing system-on-chip wake and sleep function in SOC Download PDFInfo
- Publication number
- CN101387896B CN101387896B CN2008101673569A CN200810167356A CN101387896B CN 101387896 B CN101387896 B CN 101387896B CN 2008101673569 A CN2008101673569 A CN 2008101673569A CN 200810167356 A CN200810167356 A CN 200810167356A CN 101387896 B CN101387896 B CN 101387896B
- Authority
- CN
- China
- Prior art keywords
- signal
- clock
- asynchronous reset
- wake
- sheet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Information Transfer Systems (AREA)
Abstract
The invention relates to the integrated circuit field, particularly to a method and a device which are used for realizing wakening and sleeping functions of an on-chip main system in an SOC. When the method and the device are utilized to waken the on-chip main system, the software operating instruction is reduced, and the processing efficiency and the processing speed when wakening are increased. The method of the invention comprises that after receiving a wakening signal, an asynchronous reset signal generator emits a first working signal which triggers an asynchronous reset register to access to the working state, after receiving the first working signal, the asynchronous reset register emits a second working signal which triggers a clock enabled unit to access to the working state, after receiving the second working signal, the clock enabled unit receives a chip main clock signal and transmits the chip main clock signal into a system main clock signal, after that, the clock enabled unit transmits the system main clock signal to the on-chip main system to waken the on-chip main system. The invention simultaneously discloses the device for realizing the wakening and sleeping functions of the on-chip main system in the SOC.
Description
Technical field
The present invention relates to integrated circuit fields, realize the method and apparatus of system-on-chip wake and sleep function among particularly a kind of SOC.
Background technology
Along with the develop rapidly of integrated circuit technique, the client is for consumer electronics product, and particularly the demand of portable type electronic product is more and more.Because portable type electronic product needs powered battery, so power problems shows especially day by day.Now, electronic product all is to take measures on system layer, thereby reduces power consumption, and the amplitude of chip power-consumption optimization can be more remarkable like this.
Wherein, allowing system enter sleep state is a kind of effective way.When whole SOC (system on chip, SOC (system on a chip)) has handled all tasks, and all will be in idle condition in very long a period of time the time, main system should enter into sleep state on the sheet so.When sleep, except keeping the clock source of being responsible for the relevant module needs of wake up process, the clock source that other chip and module need all can be closed.When SOC need carry out the task processing once more, can open the corresponding clock source and make total system enter duty by main system on the wake-up signal wakes sheet.
The structural representation that wakes main system on the sheet in the prior art up comprises: the clock selecting unit as shown in Figure 1; First clock enables the unit and second clock enables the unit; First register and second register; Or circuit.
As shown in Figure 1, first clock enables the unit under the control of first enable signal, selects to open or close the second frequency clock; The frequency clock after the first frequency clock or first clock enable cell enable is selected in the clock selecting unit under the control of clock selection signal; The bus write signal writes second register with second data-signal when high level, second register is exported the 3rd enable signal; When the system wake-up signal is high level first data-signal is write first register, first register is exported second enable signal; Or circuit selects second enable signal and the 3rd enable signal, and the signal after the selection is the 4th enable signal; The 4th enable signal control second clock enables the unit and opens or closes the frequency clock that the clock selecting unit sends.
SOC is when normal operation, and first enable signal is a high level, and clock selection signal is a high level, and the second frequency clock is selected in the clock selecting unit; Second enable signal is a low level, and the 3rd enable signal is a high level, so the 4th enable signal is a high level, second clock enables the unit and opens the second frequency clock that the clock selecting unit sends.
After SOC had handled all tasks, SOC at first made clock selection signal become low level, and the first frequency clock is selected in the clock selecting unit, then closes the second frequency clock; Last signal bus write signal is a high level, second data-signal is imported complete 0 data makes the 3rd enable signal become low level to second register, then the 4th enable signal becomes low level, so second clock enables the unit and closes the first frequency clock that the clock selecting unit sends, main system enters sleep state on the sheet.
When SOC needs once more Processing tasks, can produce a high level wake-up signal, first data-signal is imported complete 1 data makes second enable signal become high level to first register, so the 4th enable signal also is a high level, second clock enables the unit and opens system clock, system's master clock signal is sent to main system on the sheet, finish arousal function.
The function of main system is the duty of control SOC on the sheet, goes up main system for described and comprises clock control cell, CPU (central processing unit), system's main line and Versatile Interface Unit.Clock control cell receiving system master clock signal and handle after, after system's master clock signal after handling sent to CPU, system's main line and Versatile Interface Unit respectively, main system enters duty on the sheet, and the execution work instruction makes SOC enter duty.
The time that general wake-up signal is a high level is 1S, can cancel wake-up signal then, if but wake-up signal becomes low level in the time of 1S, at this moment main system can reenter sleep state on the sheet, in order to prevent the generation of above-mentioned situation, be at present when wake-up signal is high level, software becomes high level with the bus write signal automatically, second data-signal is imported complete 1 data makes the 3rd enable signal become high level to second register, even if wake-up signal becomes low level in the time of 1S like this, because or circuit can select high level output, so the 4th enable signal or high level, main system can not reenter sleep state on the sheet.
But said method so when waking SOC (system on a chip) up, increased the instruction of software operation, has reduced the efficient of wake-up states because the bus write signal becomes high level and must be realized by software control.
In sum, on waking sheet up, during main system, must combine and to realize by software and hardware, thereby increase the instruction of software operation at present, reduce the efficient of wake-up states.
Summary of the invention
Realize the method and apparatus of system-on-chip wake function among a kind of SOC that the embodiment of the invention provides, with respect to prior art, utilize this method and device, when waking SOC (system on a chip) up, the instruction of software operation be can reduce, treatment effeciency and speed when waking up improved.
Realize the method for system-on-chip wake function among a kind of SOC that the embodiment of the invention provides, described SOC comprises that asynchronous reset signal generator, asynchronous reset register and clock enable main system on unit and the sheet, and this method comprises:
After the asynchronous reset signal generator was received wake-up signal, transmission was used to trigger first working signal that asynchronous reset register enters duty;
After described asynchronous reset register was received described first working signal, transmission was used to trigger clock and enables second working signal that the unit enters duty;
Described clock enables after the unit receives described second working signal, the chip master clock signal that receives is converted to allows after main system enters system's master clock signal of duty on the sheet, main system sends this system's master clock signal on sheet, to wake main system on the sheet up;
Described asynchronous reset signal generator is when the level of the described wake-up signal of receiving changes, the level generation respective change of first working signal that sends, first working signal after the described level generation respective change is the reset signal that is used to trigger the former output state of asynchronous reset register;
After described asynchronous reset register is received described first working signal, keep enabling the level state of second working signal of unit transmission when the forward direction clock.
Realize the device of system-on-chip wake function among a kind of SOC that the embodiment of the invention provides, comprising:
The asynchronous reset signal generator, after being used to receive wake-up signal, transmission is used to trigger first working signal that asynchronous reset register enters duty;
Asynchronous reset register, be used to receive described first working signal after, send and to be used to trigger clock and to enable second working signal that the unit enters duty;
Clock enables the unit, after being used to receive described second working signal, the chip master clock signal that receives is converted to allows after main system enters system's master clock signal of duty on the sheet, main system sends this system's master clock signal on sheet, to wake main system on the sheet up;
Described asynchronous reset signal generator also is used for:
When the level of the described wake-up signal of receiving changes, the level generation respective change of first working signal of transmission, first working signal after the described level generation respective change is the reset signal that is used to trigger the former output state of asynchronous reset register;
Described asynchronous reset register is used for:
After receiving described first working signal, keep enabling the level state of second working signal of unit transmission when the forward direction clock.
After embodiment of the invention asynchronous reset signal generator was received wake-up signal, transmission was used to trigger first working signal that asynchronous reset register enters duty; After described asynchronous reset register was received described first working signal, transmission was used to trigger clock and enables second working signal that the unit enters duty; Described clock enables after the unit receives described second working signal, receiving chip master clock signal and described chip master clock signal is converted to allows after main system enters system's master clock signal of duty on the sheet, main system sends on sheet, wakes main system on the sheet up.During owing to main system on waking sheet up, reduced the instruction of software operation, thereby improved treatment effeciency and speed when waking up, can also effectively prevent to be strayed into sleep state after main system is waken up on the sheet simultaneously.
Description of drawings
Fig. 1 wakes the structural representation of main system on the sheet up for prior art;
Fig. 2 is an apparatus structure synoptic diagram of realizing the system-on-chip wake function among a kind of SOC of the embodiment of the invention;
Fig. 3 is an apparatus structure synoptic diagram of realizing main system sleep function on the sheet among a kind of SOC of the embodiment of the invention;
Fig. 4 is an apparatus structure synoptic diagram of realizing system-on-chip wake and sleep function among a kind of SOC of the embodiment of the invention;
Fig. 5 is a method flow synoptic diagram of realizing the system-on-chip wake function among the embodiment of the invention SOC;
Fig. 6 is a method flow synoptic diagram of realizing main system sleep function on the sheet among the embodiment of the invention SOC.
Embodiment
After embodiment of the invention asynchronous reset signal generator was received wake-up signal, transmission was used to trigger first working signal that asynchronous reset register enters duty; After asynchronous reset register is received described first working signal, transmission is used to trigger clock and enables second working signal that the unit enters duty, when wake-up signal changes, asynchronous reset register is received reset signal, still can send the state of second working signal, because only needing hardware just can realize, thereby reduce the instruction of software operation, improved treatment effeciency and speed when waking up.
Wherein, the asynchronous reset signal generator can be exported corresponding asynchronous reset signal according to the significant level (high level is effective or low level is effective) of wake-up signal.
Can wake main system on the sheet up if wake-up signal is a high level, then asynchronous reset register can be exported high level after receiving low level; After receiving high level, can keep the state (being reset mode) of existing incoming level;
Can wake main system on the sheet up if wake-up signal is a low level, then asynchronous reset register can be exported high level after receiving high level; After receiving low level, can keep the state (being reset mode) of existing incoming level.
Be that high level can wake that main system describes in further detail the embodiment of the invention on the sheet up below with the wake-up signal.
Need to prove, wake-up signal is that low level can be waken the mode of main system on the sheet and wake-up signal up to be that high level can wake on the sheet mode of main system up similar, those of ordinary skills are after having seen the embodiment of the invention, can be easy to derive wake-up signal by modes such as level conversion is the implementation that low level is waken main system on the sheet up, so repeat no more.
As shown in Figure 2, the device of realization system-on-chip wake function comprises among a kind of SOC of the embodiment of the invention: asynchronous reset signal generator 10, asynchronous reset register 20, clock enable main system 40 on unit 30 and the sheet.
Asynchronous reset signal generator 10 is used for after receiving the wake-up signal of high level, sends to be used to trigger the low level signal (i.e. first working signal) that asynchronous reset register 20 enters duty.
Wherein, wake-up signal produces after being arrived by manual activation generation or setting-up time.
Such as: when manually touching touch-screen or button, can produce wake-up signal; Perhaps,
Set a task time of origin,, can produce wake-up signal if the time arrives.
Need to prove that present embodiment is not limited to the mode of above-mentioned generation wake-up signal, any mode that can produce wake-up signal all is to use present embodiment.
In specific implementation process, asynchronous reset signal generator 10 can be a phase inverter.
Clock enables unit 30, after being used to receive high level signal from asynchronous reset register 20, the chip master clock signal that receives converted to allow after main system 40 enters system's master clock signal of duty on the sheet, main system 40 sends on sheet, wakes main system 40 on the sheet up.
Wherein, the chip master clock signal is the clock source for the main circuit operation; System's master clock signal is the signal after the chip master clock signal enables, and is the clock source of maintaining the SOC operation.
Main system 40 on the sheet, are used to control the duty of SOC, go up main system for described and comprise clock control cell, CPU (central processing unit), system's main line and Versatile Interface Unit.Clock control cell receiving system master clock signal and handle after, the system's master clock signal after handling sent to CPU, system's main line and Versatile Interface Unit respectively after, main system 40 is waken up on the sheet, the execution work instruction makes SOC enter duty.
In specific implementation process, the wake-up signal of high level can continue to send a period of time, such as 1s, can stop to send the wake-up signal of high level then, sends high level signal but asynchronous reset register 20 can continue to enable unit 30 to clock.
If the wake-up signal at high level continues owing to reasons such as equipment, to make the wake-up signal of transmission be converted to low level by high level in a period of time of transmission, then asynchronous reset signal generator 10 also is used for:
When the wake-up signal of receiving is converted to low level (level that is wake-up signal changes) by high level, respective change (promptly being converted to high level signal) also takes place in the first working signal level that sends, and first working signal after this level generation respective change is the reset signal that is used to keep asynchronous reset register 20 former output states (promptly exporting high level);
Behind the high level signal of receiving from asynchronous reset signal generator 10 (first working signal after being level generation respective change), keep enabling the state that unit 30 sends high level signal when the forward direction clock.
Then clock enables unit 30 continuation transmitting system master clock signals.
Present embodiment needs only wake-up signal high level before this, just can wake main system 40 on the sheet up, wake-up signal becomes low level in the process of transmitting even continue, can avoid also that main system 40 is strayed into sleep state on the sheet, and do not need software to participate in, be that hardware is realized all, thereby reduced the instruction of software operation, improved treatment effeciency and speed when waking up.
After SOC (system on a chip) is handled normal tasks and is finished, need allow main system enters sleep state again on the sheet, as shown in Figure 3, realize among a kind of SOC of the embodiment of the invention that the device of main system sleep function on the sheet comprises: asynchronous reset register 20 and clock enable unit 30.
Asynchronous reset register 20 is used for after receiving bus write signal and low data signal, the low data conversion of signals received is become to be used to trigger clock enable unit 30 and enter dormant low level signal (being sleep signal).
Wherein, the bus write signal is according to bus protocol, carries out the signal combination of write operation according to corresponding address (being the address of asynchronous reset register 20).
Bus write signal and low data signal are to arrive the back in the time of setting to send.
Such as: SOC does not have new task to need to handle in the time of setting after handling task, then can send bus write signal and low data signal.
Need to prove that present embodiment is not limited to the mode of above-mentioned transmission bus write signal and low data signal, any mode that can send bus write signal and low data signal all is suitable for present embodiment.
Clock enables unit 30, be used to receive low level signal from asynchronous reset register 20 after, stop the transmitting system master clock signal.
Wherein, realize among a kind of SOC of present embodiment that the device of system-on-chip wake function also has the function of the sleep of realizing, promptly with after the main system on the device wake sheet of realizing the system-on-chip wake function among the SOC of Fig. 2, when main system need enter sleep state on sheet, allow with the apparatus structure of Fig. 3 again main system enters sleep state on the sheet.
As shown in Figure 4, realize among a kind of SOC of the embodiment of the invention in the apparatus structure synoptic diagram of main system sleep and arousal function on the sheet, wake the apparatus structure of main system on the sheet up and allow on the sheet main system enter dormant apparatus structure and combine, and the chip master clock signal is that mode according to Fig. 1 produces.
Wherein, trigger pip is first enable signal among Fig. 1; High frequency clock is the second frequency clock among Fig. 1; Low-frequency clock is the first frequency clock among Fig. 1; The selection signal is the clock selection signal among Fig. 1; The chip master clock signal is the frequency clock (being the frequency clock after the first frequency clock or first clock enable cell enable) after the clock selecting unit among Fig. 1 is selected; System's master clock signal enables the clock signal of system of unit output for second clock among Fig. 1; Clock enables unit 40 and enables the unit for first clock among Fig. 1; Clock selecting unit 50 is the clock selecting unit among Fig. 1; Main system 60 is a main system on the sheet among Fig. 1 on the sheet.
As shown in Figure 5, the method for realization system-on-chip wake function comprises the following steps: among a kind of SOC of the embodiment of the invention
Wherein, wake-up signal produces after being arrived by manual activation generation or setting-up time.
Such as: when manually touching touch-screen or button, can produce wake-up signal;
Set a task time of origin,, can produce wake-up signal if the time arrives.
Need to prove that present embodiment is not limited to the mode of above-mentioned generation wake-up signal, any mode that can produce wake-up signal all is to use present embodiment.
In specific implementation process, the asynchronous reset signal generator can be a phase inverter.
Wherein, the chip master clock signal is the clock source for the main circuit operation; System's master clock signal is the signal after the chip master clock signal enables, and is the clock source of maintaining the SOC operation.
Wherein, the function of main system is the duty of control SOC on the sheet, goes up main system for described and comprises clock control cell, CPU (central processing unit), system's main line and Versatile Interface Unit.Clock control cell receiving system master clock signal and handle after, after system's master clock signal after handling sent to CPU, system's main line and Versatile Interface Unit respectively, main system enters duty on the sheet, and the execution work instruction makes SOC enter duty.
In specific implementation process, the wake-up signal of high level can continue to send a period of time, such as 1s, can stop to send the wake-up signal of high level then, sends high level signal but asynchronous reset register can continue to enable the unit to clock.
If the wake-up signal at high level continues owing to reasons such as equipment, to make the wake-up signal of transmission be converted to low level by high level in a period of time of transmission, then can further include after the step 502:
When the wake-up signal that step 503, asynchronous reset signal generator are received is converted to low level (level that is wake-up signal changes) by high level, (promptly being converted to high level signal) after the respective change also takes place in the level of first working signal that sends, and first working signal after this level generation respective change is the reset signal that is used to keep the former output state of asynchronous reset register (promptly exporting high level).
Step 504, asynchronous reset register are received from behind the high level signal of asynchronous reset signal generator (be level generation respective change after first working signal), keep enabling the state that the unit sends high level signal when the forward direction clock.
Clock enables the unit and continues the transmitting system master clock signal.
Present embodiment needs only wake-up signal high level before this, just can wake main system on the sheet up, wake-up signal becomes low level in the process of transmitting even continue, can avoid also that main system is strayed into sleep state on the sheet, and do not need software to participate in, be that hardware is realized all, thereby reduced the instruction of software operation, improved treatment effeciency and speed when waking up.
After SOC handles normal tasks and finishes, need allow main system enters sleep state again on the sheet, as shown in Figure 6, realize among a kind of SOC of the embodiment of the invention that the method for main system sleep function on the sheet comprises the following steps:
Step 600, asynchronous reset register become to be used to trigger clock with the low data conversion of signals received and enable the unit and enter dormant low level signal (being sleep signal) after receiving bus write signal and low data signal.
Wherein, the bus write signal is according to bus protocol, carries out the signal combination of write operation according to corresponding address (being the address of asynchronous reset register 20).
Bus write signal and low data signal be software time arrive the back and send.
Such as: SOC (system on a chip) does not have new task to need to handle in the time of setting after handling task, then can send bus write signal and low data signal.
Need to prove that present embodiment is not limited to the mode of above-mentioned transmission bus write signal and low data signal, any mode that can send bus write signal and low data signal all is suitable for present embodiment.
Step 601, clock enable to stop the transmitting system master clock signal after the unit receives low level signal from asynchronous reset register.
Wherein, realize among a kind of SOC of present embodiment main system sleep function on the sheet method need with a kind of SOC of Fig. 5 in realize that the method for the arousal function of main system on the sheet is used in combination, promptly wake up on the sheet after the main system with the method for Fig. 5, when main system need enter sleep state on sheet, allow with the method for Fig. 6 again main system enters sleep state on the sheet.
From the foregoing description as can be seen: after the asynchronous reset signal generator is received wake-up signal, send and to be used to trigger first working signal that asynchronous reset register enters duty; After described asynchronous reset register was received described first working signal, transmission was used to trigger clock and enables second working signal that the unit enters duty; Described clock enables after the unit receives described second working signal, receiving chip master clock signal and described chip master clock signal is converted to allows after main system enters system's master clock signal of duty on the sheet, main system sends on sheet, wakes main system on the sheet up.During owing to main system on waking sheet up, can reduce the instruction of software operation, thereby improve treatment effeciency and speed when waking up.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (8)
1. realize the method for system-on-chip wake function among the SOC, it is characterized in that described SOC comprises that asynchronous reset signal generator, asynchronous reset register and clock enable main system on unit and the sheet, this method comprises:
After described asynchronous reset signal generator was received wake-up signal, transmission was used to trigger first working signal that described asynchronous reset register enters duty;
After described asynchronous reset register was received described first working signal, transmission was used to trigger described clock and enables second working signal that the unit enters duty;
Described clock enables after the unit receives described second working signal, the chip master clock signal that receives is converted to allows after main system enters system's master clock signal of duty on the sheet, main system sends this system's master clock signal on sheet, to wake main system on the sheet up;
Described asynchronous reset signal generator is when the level of the described wake-up signal of receiving changes, the level generation respective change of first working signal that sends, first working signal after the described level generation respective change is the reset signal that is used to trigger the former output state of asynchronous reset register;
After described asynchronous reset register is received described first working signal, keep enabling the level state of second working signal of unit transmission when the forward direction clock.
2. the method for claim 1 is characterized in that, described wake-up signal is produced by manual activation or setting-up time arrives the back generation.
3. the method for claim 1 is characterized in that, this method also comprises:
Described asynchronous reset register is after receiving bus write signal and low data signal, the described low data conversion of signals received is enabled the unit and enters dormant sleep signal for being used to trigger described clock, enable the unit to described clock and send described sleep signal;
Described clock enables to stop main system transmitting system master clock signal on sheet after the unit receives described sleep signal, makes that main system enters sleep state on the sheet.
4. method as claimed in claim 3 is characterized in that, described bus write signal and described low data signal are to arrive the back in the time of setting to send.
5. realize the device of system-on-chip wake function among the SOC, it is characterized in that this device comprises:
The asynchronous reset signal generator, after being used to receive wake-up signal, transmission is used to trigger first working signal that asynchronous reset register enters duty;
Asynchronous reset register, be used to receive described first working signal after, send and to be used to trigger clock and to enable second working signal that the unit enters duty;
Clock enables the unit, after being used to receive described second working signal, the chip master clock signal that receives is converted to allows after main system enters system's master clock signal of duty on the sheet, main system sends this system's master clock signal on sheet, to wake main system on the sheet up;
Described asynchronous reset signal generator also is used for:
When the level of the described wake-up signal of receiving changes, the level generation respective change of first working signal of transmission, first working signal after the described level generation respective change is the reset signal that is used to trigger the former output state of asynchronous reset register;
Described asynchronous reset register is used for:
After receiving described first working signal, keep enabling the level state of second working signal of unit transmission when the forward direction clock.
6. device as claimed in claim 5 is characterized in that, what described wake-up signal was produced by manual activation or setting-up time arrival back produces.
7. device as claimed in claim 5 is characterized in that, described asynchronous reset register also is used for:
After receiving bus write signal and low data signal, the described low data conversion of signals received is enabled the unit and enters dormant sleep signal for being used to trigger clock, enable the unit to clock and send described sleep signal;
Described clock enables the unit and also is used for: after receiving described sleep signal, stop main system transmitting system master clock signal on sheet, make that main system enters sleep state on the sheet.
8. device as claimed in claim 7 is characterized in that, described bus write signal and described low data signal are to arrive the back in the time of setting to send.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101673569A CN101387896B (en) | 2008-10-22 | 2008-10-22 | Method and device for implementing system-on-chip wake and sleep function in SOC |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101673569A CN101387896B (en) | 2008-10-22 | 2008-10-22 | Method and device for implementing system-on-chip wake and sleep function in SOC |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101387896A CN101387896A (en) | 2009-03-18 |
| CN101387896B true CN101387896B (en) | 2010-06-23 |
Family
ID=40477348
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008101673569A Active CN101387896B (en) | 2008-10-22 | 2008-10-22 | Method and device for implementing system-on-chip wake and sleep function in SOC |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101387896B (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101944527B (en) | 2009-07-08 | 2012-11-21 | 炬才微电子（深圳）有限公司 | Integrated circuit and standby controlling method thereof |
| JP2011128813A (en) * | 2009-12-16 | 2011-06-30 | Canon Inc | Data processing circuit |
| CN103412634B (en) * | 2013-07-30 | 2016-08-10 | 深圳市汇顶科技股份有限公司 | The MCU Rouser of a kind of SOC and method |
| KR102257380B1 (en) * | 2014-12-22 | 2021-05-31 | 삼성전자주식회사 | System-on-chip including on-chip clock controller and mobile device having the same |
| CN106488460B (en) * | 2015-08-28 | 2020-06-23 | 苏州恩泽迅扬节能科技有限公司 | Wireless communication method, and corresponding master device, slave device and wireless communication system |
| CN105929996A (en) * | 2016-04-15 | 2016-09-07 | 京东方科技集团股份有限公司 | Method for controlling display panel to sleep, sleep control circuit and display apparatus |
| CN107678532A (en) * | 2017-10-20 | 2018-02-09 | 苏州国芯科技有限公司 | A kind of low-power dissipation SOC wake module and low-power dissipation SOC |
| CN116783571A (en) * | 2020-12-28 | 2023-09-19 | 华为技术有限公司 | Communication device and clock management method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1877494A (en) * | 2006-07-19 | 2006-12-13 | 北京天碁科技有限公司 | System-on-chip chip and its power consumption control method |
| CN100426177C (en) * | 2001-12-20 | 2008-10-15 | 诺基亚有限公司 | Dynamic power control in integrated circuit |
-
2008
- 2008-10-22 CN CN2008101673569A patent/CN101387896B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100426177C (en) * | 2001-12-20 | 2008-10-15 | 诺基亚有限公司 | Dynamic power control in integrated circuit |
| CN1877494A (en) * | 2006-07-19 | 2006-12-13 | 北京天碁科技有限公司 | System-on-chip chip and its power consumption control method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101387896A (en) | 2009-03-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101387896B (en) | Method and device for implementing system-on-chip wake and sleep function in SOC | |
| CN100442204C (en) | System-on-chip chip and its power consumption control method | |
| CN102869077B (en) | ZigBee-protocol-based data acquisition and transmission method of wireless sensor network | |
| TWI475373B (en) | Control device, control method, computer program product, and electronic device | |
| CN103645796B (en) | Based on high-performance hydrographic water resource telemetering terminal and the power consumption control method thereof of ARM framework | |
| WO2018157689A1 (en) | Method for implementing low power consumption on standby for bluetooth security device and bluetooth security device | |
| CN101876847A (en) | Power reduction in microcontrollers | |
| CN101859172A (en) | Integrated circuit SoC chip circuit structure capable of realizing power reduction and method thereof | |
| CN108777862B (en) | Bluetooth transmission method, Bluetooth controller and Bluetooth device | |
| CN106427835A (en) | Low-power-consumption dormancy circuit of new energy automobile electronic VCU module | |
| CN106358273A (en) | Low-power-consumption communication device | |
| CN104216500A (en) | Embedded controller and power-saving control method | |
| CN102099762A (en) | System and method for power management | |
| CN109041188A (en) | Wireless terminal, wireless terminal power-saving method and device | |
| CN106063304B (en) | System and method for message-based fine-grained system-on-chip power control | |
| CN103746819A (en) | Terminal energy saving method and terminal and system | |
| CN105119726B (en) | A kind of wireless sensing net node fast wake-up method and device thereof | |
| CN106774808B (en) | A kind of multistage low-power consumption administrative unit and its method of multi-core chip | |
| CN108345376B (en) | Low-power chip awakening method and device and low-power chip | |
| CN104916102B (en) | The wireless communication and control method of intelligent gas meter | |
| TW201017393A (en) | Embedded system with power-saving function and power-saving method thereof | |
| CN115639897B (en) | Real-time voltage control module | |
| CN114020138B (en) | Micro control unit chip and method for reducing electric quantity consumption | |
| CN104916103A (en) | Intelligent instrument wireless communication and control method | |
| CN100451885C (en) | System and method for managing actuator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20170608 Address after: 519085 C District, 1# workshop, No. 1, science and technology No. four road, hi tech Zone, Zhuhai, Guangdong, China Patentee after: ACTIONS (ZHUHAI) TECHNOLOGY Co.,Ltd. Address before: 519085 No. 1, unit 15, building 1, 1 Da Ha Road, Tang Wan Town, Guangdong, Zhuhai Patentee before: Juli Integrated Circuit Design Co., Ltd. |
|
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 519085 High-tech Zone, Tangjiawan Town, Zhuhai City, Guangdong Province Patentee after: ACTIONS TECHNOLOGY Co.,Ltd. Address before: 519085 High-tech Zone, Tangjiawan Town, Zhuhai City, Guangdong Province Patentee before: ACTIONS (ZHUHAI) TECHNOLOGY Co.,Ltd. |