CN100405863C - Method for regulating sleeping processor in mobile terminal machine process - Google Patents
Method for regulating sleeping processor in mobile terminal machine process Download PDFInfo
- Publication number
- CN100405863C CN100405863C CNB2005100569367A CN200510056936A CN100405863C CN 100405863 C CN100405863 C CN 100405863C CN B2005100569367 A CNB2005100569367 A CN B2005100569367A CN 200510056936 A CN200510056936 A CN 200510056936A CN 100405863 C CN100405863 C CN 100405863C
- Authority
- CN
- China
- Prior art keywords
- sleep
- processor
- cycle
- calibration
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 62
- 230000001105 regulatory effect Effects 0.000 title 1
- 238000012937 correction Methods 0.000 claims abstract description 35
- 230000004622 sleep time Effects 0.000 claims description 47
- 230000005540 biological transmission Effects 0.000 claims description 6
- 230000002618 waking effect Effects 0.000 claims description 4
- 230000036578 sleeping time Effects 0.000 abstract 1
- 239000013078 crystal Substances 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 230000002123 temporal effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000004445 quantitative analysis Methods 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 230000008667 sleep stage Effects 0.000 description 1
- 230000009897 systematic effect Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The present invention discloses a method for calibrating a sleeping processor in the mobile terminal standby process. The method is characterized in that a sleeping processor of the mobile terminal receives a calibration signal and sleeping duration time information which are transmitted by a main processor; a calibrating correction value for aiming at a sleeping processor clock is determined according to the calibration signal; sleeping duration time which is counted by the sleeping processor clock is corrected according to the calibrating correction value. The method extends the sleeping time of the main processor, reduces the standby power consumption of the main processor and extends the standby time of the mobile terminal.
Description
Technical field
The present invention relates to the Opportunity awaiting control for linear technology of portable terminal, relate in particular to the method for calibration sleep processor in a kind of mobile terminal standby process.
Background technology
Portable terminal all has idle function at present, under holding state, portable terminal need for example base station (NodeB) maintenance be synchronous with the terminal access device, and the primary processor of portable terminal is waken up at regular intervals and once received the paging information of sub-district, paging lasts a period of time, continues sleep then.In order to wake primary processor up, portable terminal also comprises a sleep processor, is used between the primary processor sleep period, provides a high-precision wake-up signal to primary processor, wakes primary processor up after the length of one's sleep of appointment.
But, because the clock of sleep processor and the clock frequency of primary processor are inequality, therefore there is certain deviation in time in the clock of its clock and primary processor, and the clock of sleep processor must be through providing a wake-up signal that satisfies required precision to primary processor after the calibration.
The process of in the prior art sleep processor being calibrated is finished in primary processor, be the calibration process of example explanation prior art below with synchronous CDMA (Code Division Multiple Access) of time-division (TD-SCDMA, Time Division-Synchronous Code DivisionMultiple Access) portable terminal.
Fig. 1 carries out the structure chart of timing alignment for the available technology adopting primary processor.As shown in Figure 1, comprise primary processor 101, sleep processor 102,19.2MHz high voltage stability temperature control benefit crystal oscillator (VCTCXO) 103 and 8MHz common crystals 104 in the portable terminal.Wherein VCTCXO is responsible for providing the operation clock of primary processor, and the 8MHz common crystals is responsible for providing the operation clock of sleep processor.The paging cycle 1.28s or the 5.12s of common primary processor, paging lasts 50ms.Described sleep processor 102 is a single-chip microcomputer.Described communication interface is used for the data interaction between primary processor and the sleep processor; The wake-up signal processor that is used to sleep wakes primary processor up; The 5ms signal is obtained through sleep processor counting frequency division by the 8MHz common crystals, outputs to primary processor and is used for standard of counting.Described 8MHz common crystals 104 also can be built in the sleep processor.
Fig. 2 carries out the flow chart of timing alignment for the available technology adopting primary processor.As shown in Figure 2, calibration process be along with the paging cycle of primary processor the cycle carry out, detailed process comprises:
In the n paging cycle, primary processor receive the sleep processor wake-up signal after wake up, utilize the determined N-1 calibration data of N-1 paging cycle to carry out synchronously, then carry out paging, after paging finishes, send the calibrating signal request command to the sleep processor, after the sleep processor is received this calibrating signal request command, return the calibrating signal of 5ms; Primary processor receives this calibrating signal, utilize this calibrating signal to carry out the calibration process in this cycle, this cycle of calculating i.e. n number calibration data, after calibration process finishes, primary processor sends sleep commands to the sleep processor, carry the temporal information that sleep continues in this sleep commands, for example the lasting frame number N of sleep; After sending sleep commands, primary processor carries out sleep procedure; After the sleep processor is received sleep commands, send wake-up signal to primary processor after through the N frame, primary processor is waken up after receiving wake-up signal once more, begins the N+1 paging cycle.N+1 paging cycle and follow-up paging cycle circulation repeat said process.
Below the timing accuracy and the power consumption expense of prior art are carried out quantitative analysis:
The paging cycle of supposing primary processor is that x, primary processor calibration process last y, primary processor power consumption z, then:
The timing accuracy of prior art is: 8ns* (x/5ms)=8.192us, wherein establish x=5.12s; Wherein, 8ns is the sampling error of primary processor.
The power consumption expense of prior art is:
Z* (y/x)=0.889mA wherein establishes x=5.12s, y=10ms, z=450mA;
Z* (y/x)=3.52mA wherein establishes x=1.28s, y=10ms, z=450mA.
By above-mentioned quantitative analysis as can be known, existing to carry out the Calibration Method timing accuracy by primary processor not high, and the power consumption expense of processor is big.
Because portable terminal is a kind of mobile communication equipment, therefore in order to obtain longer stand-by time, portable terminal requires very high to stand-by power consumption.Yet prior art is carried out in primary processor the timing alignment process of sleep processor, therefore increased the processing time when primary processor wakes up, shortened the length of one's sleep of primary processor relatively, and then the stand-by power consumption of increase portable terminal, the power supply of waste portable terminal makes the stand-by time of portable terminal shorten.
Summary of the invention
In view of this, main purpose of the present invention provides the method for calibration sleep processor in a kind of mobile terminal standby process, to reduce the stand-by power consumption of primary processor, the stand-by time that prolongs portable terminal.
To achieve these goals, technical scheme of the present invention specifically is achieved in that
The method of calibration sleep processor in a kind of mobile terminal standby process, this method comprises:
The sleep processor of portable terminal receives calibrating signal and the sleep time information that primary processor sends, according to the definite calibration correction value of this calibrating signal, revise according to the sleep time that this calibration correction value is counted the sleep processor clock at the sleep processor clock.
Preferably, described calibrating signal is by the clock generating of primary processor.
Preferably, described sleep processor is determined at the detailed process of the calibration correction value of sleep processor clock according to described calibrating signal: with a certain edge that receives calibrating signal between awake period is beginning, to the same edge that after this receives calibrating signal between awake period is to finish, as a calibration cycle; When calibration cycle begins, write down the value y1 of sleep processor intercycle timer, when calibration cycle finishes, write down the value y2 of this cycle timer, determine the time M of calibration cycle with sleep processor self clock; Y1 is deducted y2, and the difference that obtains multiply by the sleep time information N from primary processor that receives again divided by M, and the value that obtains is the calibration correction value.
The detailed process that the described sleep time of the sleep processor clock being counted according to this calibration correction value is revised is: the sleep time that the processor clock of will sleeping is counted adds described calibration correction value, and the value that obtains is revised sleep time.
Described sleep processor picked up counting from the moment of receiving the sleep time information that primary processor sends, and when timing reaches revised sleep time, sent wake-up signal to primary processor.
Described sleep time information N and time M from primary processor is unit with the frame, and described sleep processor picks up counting constantly from receiving sleep time information, detailed process to primary processor transmission wake-up signal when timing reaches revised sleep time is: in current paging cycle, when the sleep processor receives a certain edge of described calibrating signal, the value x1 of record cycle timer; When the sleep processor is received sleep time information N, utilize self clock to pick up counting, when timing during to the N-1 frame, during the every meter of described cycle timer one time, that whether the value of then judging timer arrives x1 and described calibration correction value and value, if do not reach, then this cycle timer continues timing, up to the value of this cycle timer reach x1 and described calibration correction value with value the time, the sleep processor sends wake-up signal to primary processor.
The moment of the value x1 of described record cycle timer is: in the current paging cycle, the sleep processor receives the moment at last edge of described calibrating signal.
In described calibration cycle, the sleep time that utilizes the determined calibration correction value of last calibration cycle that the sleep processor clock is counted is revised.
Described calibration cycle is the integral multiple of paging cycle, and this method further comprises: the thresholding time value that sets in advance the storage calibration cycle on the sleep processor; When receiving the calibrating signal edge that the calibrating signal edge is identical when beginning with calibration cycle, judgement begins whether to surpass described calibration cycle thresholding time value to the current time period from calibration cycle, if, then finish current calibration cycle, otherwise, continue current calibration cycle, when receiving the calibrating signal edge is identical when beginning with calibration cycle calibrating signal edge and beginning to surpass described calibration cycle thresholding time value, finish current calibration cycle to the time period in this moment from calibration cycle.
Calibrating signal edge when described calibration cycle begins is primary processor first edge in the calibrating signal of waking the back transmission up.
Preferably, described calibration information is that primary processor carries out sending to the sleep processor in the paging between awake period; Described sleep time information is that primary processor sends to the sleep processor when paging finishes; Described primary processor finishes the back sleep in paging.
Preferably, the cycle of described calibrating signal and described sleep processor clock is 5ms.
Because the method for the invention adopts the sleep processor to carry out timing alignment in the mobile terminal standby process, because the sleep processor is the super low-power consumption device, the about hundreds of microampere of its power consumption, so the power consumption expense can be ignored; Simultaneously, primary processor does not carry out timing alignment, so primary processor only carries out both can sleeping again after the paging after waking up, does not need to carry out timing alignment, has therefore prolonged the length of one's sleep of primary processor, reduces the stand-by power consumption of primary processor.For above-mentioned reasons, the present invention can reduce the stand-by power consumption of primary processor, prolongs the stand-by time of portable terminal.
In addition, because calibration cycle of the present invention is long, generally can reach several paging cycle, so the calibration accuracy height, by the measurement of reality, when paging cycle is 5.12s, the accuracy of timing alignment can be reached for 0.5us, satisfies actual accuracy demand fully.
Description of drawings
Fig. 1 carries out the structure chart of timing alignment for the available technology adopting primary processor;
Fig. 2 carries out the flow chart of timing alignment for the available technology adopting primary processor;
Fig. 3 carries out the structure chart of timing alignment for embodiment of the present invention adopts the sleep processor;
Fig. 4 carries out the flow chart of timing alignment process for employing sleep processor of the present invention;
Fig. 5 is that employing sleep processor of the present invention carries out the signal timing diagram in the timing alignment process.
Embodiment
Further specify implementation method of the present invention below in conjunction with the drawings and specific embodiments.
Core concept of the present invention is: the primary processor of portable terminal carries out paging between awake period, sends calibrating signal to the sleep processor simultaneously, sends sleep time information to the sleep processor when paging finishes, and paging finishes the back sleep; The sleep processor of portable terminal receives described calibrating signal and sleep time information, according to the definite calibration correction value of this calibrating signal at the sleep processor clock, revise according to the sleep time that this calibration correction value is counted the sleep processor clock, from receiving that sleep time information picks up counting constantly, when timing reaches revised sleep time, send wake-up signal to primary processor; Described primary processor wakes up when receiving wake-up signal.
Below with the TD-SCDMA portable terminal be specific embodiment the present invention will be described, the present invention go for equally other have primary processor and the sleep processor portable terminal.
Fig. 3 carries out the structure chart of timing alignment for embodiment of the present invention adopts the sleep processor.As shown in Figure 3, the structure chart of the described sleep processor of present embodiment timing alignment is similar with the structure chart of main processing timing alignment in the prior art, it is the clock of primary processor that the high voltage stability temperature control is mended crystal oscillator (VCTCXO), the 8MHz common crystals is the clock of sleep processor, to be the 5ms calibrating signal that is used to calibrate produced and outputed to the sleep processor behind primary processor counting frequency division by the high steady VCTCXO of 19.2MHz of primary processor in difference, is used for calibrating the time of the 8MHz common crystals clock of described sleep processor.
In the present embodiment, described primary processor and the sleep clock signal of processor and the cycle of calibrating signal are 5ms, i.e. a frame, but the cycle of signal of the present invention be not limited to 5ms, can other unit be the cycle also, 10ms for example, 20ms etc.
Fig. 4 carries out the flow chart of timing alignment process for employing sleep processor of the present invention.As shown in Figure 4, calibration process of the present invention also is to carry out in the cycle, but calibration cycle is the integral multiple of primary processor paging cycle.K calibration cycle with the sleep processor is that example describes below.The method of the invention comprises:
In the primary processor side, in the n paging cycle, primary processor wakes up after receiving the wake-up signal that the sleep processor sends, and carries out paging, and between the primary processor awake period, primary processor continues to send the 5ms calibrating signal to the sleep processor; After paging finishes, send sleep commands, carry the temporal information that sleep continues in this sleep commands, the frame number N that the temporal information in the present embodiment continues for sleep to the sleep processor; After sending sleep commands, primary processor finishes awakening phase, begins sleep, enters sleep stage, wakes up once more after receiving wake-up signal and enters next paging cycle, repeats aforesaid operations.
In sleep processor side, be beginning with a certain edge that receives the calibrating signal that sends between the primary processor awake period, be to finish to the same edge that after this receives the calibrating signal that sends between the primary processor awake period, as a calibration cycle; In current calibration cycle, be in the K calibration cycle as shown in Figure 4, the sleep processor receives the 5ms calibrating signal that primary processor sends, and determines in this calibration cycle calibration data at the sleep processor clock according to this calibrating signal, be the calibration correction value, be the K calibration data herein; In each paging cycle, after the sleep processor is received the sleep commands of primary processor transmission, obtain the sleep time information of wherein carrying, according to a last calibration cycle, promptly the calibration correction value of K-1 calibration cycle is revised the sleep time counted of sleep processor clock, the clock of sleep processor picked up counting from the moment of receiving sleep commands, when timing reaches revised sleep time, sent wake-up signal to primary processor.
The following describes in each calibration cycle the concrete calibration process of sleep processor inside.
Fig. 5 is that employing sleep processor of the present invention carries out the signal timing diagram in the timing alignment process.As shown in Figure 5, signal S1 is the 5ms frame signal of primary processor clock, produce by VCTCXO, operation 8 frame times after the hypothesis primary processor is waken up among Fig. 5, send out sleep commands for the sleep processor at the 8th frame then, carry the time that sleep continues in this sleep commands, sleep time herein calculates with frame number, is N frame; Notice sleep processor sends wake-up signal to primary processor after receiving sleep commands N frame.Signal S2 is the 5ms calibrating signal that primary processor outputs to the sleep processor, is also produced by VCTCXO.Signal S3 is the count signal of the inside 5ms counter of sleep processor, this 5ms counter is the one-period timer, the 5ms periodic signal of clock generating with the sleep processor is a standard, every 5ms count down to 40000 from 0, promptly from counting (CON, Counter)=0 to CON=40000, every counting once is equivalent to timing 125nS.Signal S4 is the wake-up signal that the sleep processor outputs to primary processor.The time of described calibration cycle is M 5ms, and M wherein is a natural number, and initial value is zero, and its threshold value is M0, and M0 preestablishes and stores in the sleep processor, and for example M0 can be made as 1000.M is definite by counting by the sleep processor, the sleep processor is according to the common brilliant frame clock of 8MHz of self, begin every 5ms counting once from calibration cycle, the M value is added 1, when sending wake-up signal, whether judge current M value, if then write down current M value greater than M0 at every turn, be used for determining the calibration correction value, otherwise continue to add up.Described T0 is the zero hour of current calibration cycle constantly, receive the moment at first edge of S2 signal shown in Fig. 5 for the sleep processor, described T1 is the finish time of current calibration cycle, in the paging cycle that is right after after for M shown in Fig. 5 greater than M0, the moment that the sleep processor is received first edge of S2 signal.In the paging cycle that described T2 is right after after greater than M0 for M constantly, the moment that the sleep processor is received last S2 signal edge.After described T3 is calibration correction constantly, send the moment of wake-up signal.Be a calibration cycle between described T0 and the T1, comprise M 5ms.
Described T0 and T1 also receive the S2 signal in paging cycle m edge constantly, in the scope that accuracy allows, described T2 also can be M greater than M0 after, the moment the when processor of sleeping is received any edge of S2 signal.
In a calibration cycle, after primary processor wakes startup up, send calibrating signal S2 to the sleep processor, the sleep processor writes down the value y1 of current 5ms counter signals S3 when T0, the clock that begins simultaneously with the brilliant frame of 8MHz of sleep processor is that standard is counted M, since 0, every 5ms that crosses, M is added one, when the sleep processor receives the calibrating signal edge that the calibrating signal edge is identical when beginning with calibration cycle, when waking first edge of back transmission calibrating signal up for primary processor herein, judge that whether the M value is greater than M0, if not, then continuing timing, every 5ms time M that crosses continues to add one; When receiving the calibrating signal edge that the calibrating signal edge is identical when beginning with calibration cycle once more, the sleep processor continues whether to judge the M value, with this execution that circulates greater than M0; If M value then write down current M value greater than M0 when the sleep processor received the calibrating signal edge that the calibrating signal edge is identical when beginning with calibration cycle, this constantly also be T1 constantly, finish current calibration cycle, write down the value y2 of S3 at this moment; Because S2 is from the steady TCVCXO of height, and actual about 10 seconds of calibration cycle, the frequency of VCTCXO only is subjected to temperature and voltage influence, and temperature and voltage can not be sudden changes in the short time in 10 seconds, so can think that M 5ms do not have frequency departure in the calibration cycle.Then the individual minimum of sleep processor deviation (y1-y2) is adjusted step-length (cycle) in the time of M 5ms, and each cycle is 125ns.
After processor receives the sleep commands of primary processor, from sleep commands, obtain the frame number N that sleep continues in sleep, with the definite calibration correction value of above-mentioned y1, y2, M and N value, i.e. calibration data, concrete definite process is as formula 1) shown in:
Calibration correction value=((y1-y2) * N)/M formula 1)
After having determined the calibration correction value, revise according to the sleep time that this calibration correction value is counted the sleep processor clock, the sleep time that the processor clock that is about to sleep is counted adds described calibration correction value, the value that obtains is revised sleep time, and from receiving that sleep time information picks up counting constantly, when timing reaches revised sleep time, send wake-up signal to primary processor.Detailed process is as follows:
In calibration cycle paging cycle subsequently, record S2 signal is in the end during an edge, be the T2 value x1 of S3 constantly, when the sleep processor after receive sleep commands, utilize the brilliant frame of 8MHz of self to pick up counting, since the 0th frame to the N-1 frame, when when N-1 frame S3 value arrives x1, be the sleep time counted of sleep processor clock, therefore this sleep time is added described calibration correction value, obtain revised sleep time, promptly sleep time needs timing when N-1 frame S3 value is.Therefore, when timing when the N-1 frame begins, described 5ms counter whenever adds number one time, whether the value S3 that then judges counter arrives x1+ ((y1-y2) * N)/M, if do not reach, then the value of S3 continues to add one, when the value of S3 reaches x1+ ((y1-y2) * N)/M, the sleep processor sends wake-up signal to primary processor, thereby finishes sending wake-up signal calibration constantly.
Because in different paging cycle, the value of described N may be different, therefore, in each paging cycle, the sleep processor is all determined the value x1 of S3 when T2, utilizes the value of described N again, and determined y1, y2 and M determine the calibration correction value in the last calibration cycle, and, promptly revise the time that sends wake-up signal to primary processor with the sleep time of the described sleep processor of this calibration correction value correction timing.
The variation of clock frequency mainly is subjected to the influence of temperature, voltage, when these factors vary, can cause frequency change, because T3 is to about tens seconds in the time interval of T0, temperature and voltage do not have very big sudden change during this period, therefore can think during this period of time in the frequency of T3 during the T2 equal the frequency of T1 during the T0.Therefore the method for the invention can satisfy the requirement of accuracy well.
Because the sleep processor has super low-power consumption, so the method for the relative prior art of method for self-calibrating of the present invention can be saved the primary processor power consumption of about 10ms.In addition, because the counter of sleep processor operates in 8MHz, the minimum step-length 1cycle=125ns that adjusts consider systematic error timing accuracy pact-250ns～250ns, so the present invention can satisfy the requirement of system to the portable terminal timing offset.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with the people of this technology in the disclosed technical scope of the present invention; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.
Claims (12)
1. the method for calibration sleep processor in the mobile terminal standby process is characterized in that,
The sleep processor of portable terminal receives calibrating signal and the sleep time information that primary processor sends, according to the definite calibration correction value of this calibrating signal, revise according to the sleep time that this calibration correction value is counted the sleep processor clock at the sleep processor clock.
2. the method for claim 1 is characterized in that, described calibrating signal is by the clock generating of primary processor.
3. the method for claim 1 is characterized in that, described sleep processor determine at the detailed process of the calibration correction value of sleep processor clock according to described calibrating signal be:
A certain edge with calibrating signal between the reception awake period is beginning, is to finish to the same edge that after this receives calibrating signal between awake period, as a calibration cycle; When calibration cycle begins, write down the value y1 of sleep processor intercycle timer, when calibration cycle finishes, write down the value y2 of this cycle timer, determine the time M of calibration cycle with sleep processor self clock; Y1 is deducted y2, and the difference that obtains multiply by the sleep time information N from primary processor that receives again divided by M, and the value that obtains is the calibration correction value.
4. method as claimed in claim 3, it is characterized in that, the detailed process that the described sleep time of the sleep processor clock being counted according to this calibration correction value is revised is: the sleep time that the processor clock of will sleeping is counted adds described calibration correction value, and the value that obtains is revised sleep time.
5. method as claimed in claim 4 is characterized in that, described sleep processor picked up counting from the moment of receiving the sleep time information that primary processor sends, and when timing reaches revised sleep time, sent wake-up signal to primary processor.
6. method as claimed in claim 5, it is characterized in that, described sleep time information N and time M from primary processor is unit with the frame, and described sleep processor picks up counting constantly from receiving sleep time information, and the detailed process to primary processor transmission wake-up signal when timing reaches revised sleep time is:
In current paging cycle, when the sleep processor receives a certain edge of described calibrating signal, the value x1 of record cycle timer; When the sleep processor is received sleep time information N, utilize self clock to pick up counting, when timing during to the N-1 frame, during the every meter of described cycle timer one time, that whether the value of then judging timer arrives x1 and described calibration correction value and value, if do not reach, then this cycle timer continues timing, up to the value of this cycle timer reach x1 and described calibration correction value with value the time, the sleep processor sends wake-up signal to primary processor.
7. method as claimed in claim 6 is characterized in that, the moment of the value x1 of described record cycle timer is: in the current paging cycle, the sleep processor receives the moment at last edge of described calibrating signal.
8. method as claimed in claim 3 is characterized in that, in described calibration cycle, the sleep time that utilizes the determined calibration correction value of last calibration cycle that the sleep processor clock is counted is revised.
9. method as claimed in claim 3 is characterized in that, described calibration cycle is the integral multiple of paging cycle, and this method further comprises:
On the sleep processor, set in advance the thresholding time value of storage calibration cycle; When receiving the calibrating signal edge that the calibrating signal edge is identical when beginning with calibration cycle, judgement begins whether to surpass described calibration cycle thresholding time value to the current time period from calibration cycle, if, then finish current calibration cycle, otherwise, continue current calibration cycle, when receiving the calibrating signal edge is identical when beginning with calibration cycle calibrating signal edge and beginning to surpass described calibration cycle thresholding time value, finish current calibration cycle to the time period in this moment from calibration cycle.
10. method as claimed in claim 9 is characterized in that, the calibrating signal edge when described calibration cycle begins is primary processor first edge in the calibrating signal of waking the back transmission up.
11. the method for claim 1 is characterized in that, described calibrating signal is that primary processor carries out sending to the sleep processor in the paging between awake period; Described sleep time information is that primary processor sends to the sleep processor when paging finishes; Described primary processor finishes the back sleep in paging.
12., it is characterized in that the cycle of described calibrating signal and described sleep processor clock is 5ms as each described method of claim 1 to 11.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100569367A CN100405863C (en) | 2005-03-23 | 2005-03-23 | Method for regulating sleeping processor in mobile terminal machine process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100569367A CN100405863C (en) | 2005-03-23 | 2005-03-23 | Method for regulating sleeping processor in mobile terminal machine process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1838800A CN1838800A (en) | 2006-09-27 |
| CN100405863C true CN100405863C (en) | 2008-07-23 |
Family
ID=37016029
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100569367A Active CN100405863C (en) | 2005-03-23 | 2005-03-23 | Method for regulating sleeping processor in mobile terminal machine process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100405863C (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106873750A (en) * | 2015-12-10 | 2017-06-20 | 北京信威通信技术股份有限公司 | A kind of sleep/wake method of USB slave units control |
| CN107765760B (en) * | 2017-11-17 | 2021-05-04 | 上海伟世通汽车电子系统有限公司 | RTC module clock source dynamic calibration method and RTC module clock source dynamic calibration system in instrument sleep mode |
| CN114237020B (en) * | 2021-12-10 | 2023-09-26 | 合肥兆芯电子有限公司 | Method for calibrating timer and electronic device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6453181B1 (en) * | 1999-11-04 | 2002-09-17 | Qualcomm, Incorporated | Method and apparatus for compensating for frequency drift in a low frequency sleep clock within a mobile station operating in a slotted paging mode |
| CN1451247A (en) * | 1999-11-04 | 2003-10-22 | 高通股份有限公司 | Method and apparatus for activating a high frequency clock following a sleep mode with in a mobile station operating in a slotted paging mode |
| GB2393610A (en) * | 2002-09-26 | 2004-03-31 | Nec Technologies | Clock calibration in a mobile communications device |
| GB2397465A (en) * | 2003-01-15 | 2004-07-21 | Nec Technologies | Clock calibration in a mobile radio communications device |
-
2005
- 2005-03-23 CN CNB2005100569367A patent/CN100405863C/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6453181B1 (en) * | 1999-11-04 | 2002-09-17 | Qualcomm, Incorporated | Method and apparatus for compensating for frequency drift in a low frequency sleep clock within a mobile station operating in a slotted paging mode |
| CN1451247A (en) * | 1999-11-04 | 2003-10-22 | 高通股份有限公司 | Method and apparatus for activating a high frequency clock following a sleep mode with in a mobile station operating in a slotted paging mode |
| GB2393610A (en) * | 2002-09-26 | 2004-03-31 | Nec Technologies | Clock calibration in a mobile communications device |
| GB2397465A (en) * | 2003-01-15 | 2004-07-21 | Nec Technologies | Clock calibration in a mobile radio communications device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1838800A (en) | 2006-09-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10707984B2 (en) | Techniques for synchronizing slave devices | |
| CN1130096C (en) | Synchronisation of a low power clock in a wireless communication device | |
| US20150296453A1 (en) | Correction of clock errors in a wireless station to enable reduction of power consumption | |
| US6219564B1 (en) | Time base alignment for digital mobile phones | |
| US20070217562A1 (en) | Aligning a frame pulse of a high frequency timer using a low frequency timer | |
| CN101124735A (en) | Precise sleep timer using a low-cost and low-accuracy clock | |
| EP2369438B1 (en) | Calibration method of a real time clock signal | |
| CN105142210B (en) | A kind of real-time clock synchronous calibration method and sensor for wireless sense network | |
| RU2002114547A (en) | METHOD AND DEVICE OF RE-STARTING A MOBILE STATION AT THE END OF THE STANDBY MODE | |
| CN101252720A (en) | Method and apparatus for controlling 3G and 4G terminal dormancy mode | |
| JP2001159690A (en) | Portable device and real time information production method | |
| RU2579716C2 (en) | Correction of low-accuracy clock generator | |
| CN100588280C (en) | Method and device for calibrating sleep clock of TD-SCDMA terminal | |
| US8258881B2 (en) | Method and system for drift reduction in a low power oscillator (LPO) utilized in a wireless communication device | |
| CN113346881B (en) | Digital clock calibration method, wireless remote controller and storage medium | |
| US20060190752A1 (en) | Compensating software time in processor having sleep mode | |
| CN107329399A (en) | A kind of satellite time transfer clock system Low-power-consumptiocontrol control method and clock system | |
| CN101826955A (en) | Synchronization error correction method | |
| CN106227293A (en) | A kind of system clock | |
| CN111669812B (en) | Low-power-consumption Bluetooth chip, equipment, dormancy awakening control method of equipment and communication system | |
| CN100405863C (en) | Method for regulating sleeping processor in mobile terminal machine process | |
| CN113645683B (en) | Crystal oscillator self-adaptive clock synchronization method and system | |
| US7149555B2 (en) | Mobile phone capable of stopping main clock signal | |
| CN216133319U (en) | Automatic calibration system for multipath time | |
| CN103023433B (en) | Improved high-precision oscillator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: LIANXIN SCIENCE CO., LTD. Free format text: FORMER OWNER: DATANG MOBILE COMMUNICATION APPARATUS CO., LTD. Effective date: 20090508 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20090508 Address after: 41, No. 4, No. 333, No. 333, chin Jiang Road, zip code: 200233 Co-patentee after: Datang Mobile Communication Equipment Co., Ltd. Patentee after: Lian core technology Co., Ltd. Address before: Beijing, Xueyuan Road, Haidian District No. 40: 100083 Patentee before: Datang Mobile Communication Equipment Co., Ltd. |
|
| C56 | Change in the name or address of the patentee | ||
| CP02 | Change in the address of a patent holder |
Address after: 201206 Pudong New Area Mingyue Road, Shanghai, No. 1258 Co-patentee after: Datang Mobile Communication Equipment Co., Ltd. Patentee after: Leadcore Technology Co., Ltd. Address before: 200233 Shanghai, Jiang Road, No. 41, building 4, building 333 Co-patentee before: Datang Mobile Communication Equipment Co., Ltd. Patentee before: Leadcore Technology Co., Ltd. |
|
| ASS | Succession or assignment of patent right |
Free format text: FORMER OWNER: DATANG MOBILE COMMUNICATION EQUIPMENT CO., LTD. Effective date: 20120216 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20120216 Address after: 201206 Pudong New Area Mingyue Road, Shanghai, No. 1258 Patentee after: Leadcore Technology Co., Ltd. Address before: 201206 Pudong New Area Mingyue Road, Shanghai, No. 1258 Co-patentee before: Datang Mobile Communication Equipment Co., Ltd. Patentee before: Leadcore Technology Co., Ltd. |
|
| EE01 | Entry into force of recordation of patent licensing contract | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20060927 Assignee: Shanghai Li Ke Semiconductor Technology Co., Ltd. Assignor: Leadcore Technology Co., Ltd. Contract record no.: 2018990000159 Denomination of invention: Method for regulating sleeping processor in mobile terminal machine process Granted publication date: 20080723 License type: Common License Record date: 20180615 |