CN114138056A - Display terminal clock calibration method and device and display terminal - Google Patents
Display terminal clock calibration method and device and display terminal Download PDFInfo
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- CN114138056A CN114138056A CN202111299093.9A CN202111299093A CN114138056A CN 114138056 A CN114138056 A CN 114138056A CN 202111299093 A CN202111299093 A CN 202111299093A CN 114138056 A CN114138056 A CN 114138056A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/14—Time supervision arrangements, e.g. real time clock
Abstract
The display terminal clock calibration method comprises the steps of obtaining clock deviation and interval time corresponding to two adjacent clock calibrations, calculating a unit time calibration value according to the clock deviation and the interval time corresponding to the two adjacent clock calibrations, obtaining a calibration clock period, calculating a clock calibration value corresponding to the calibration clock period according to the calibration clock period and the unit time calibration value, and calibrating clock time based on the clock calibration value. According to the method and the device, clock deviation and interval time of the clock are calibrated twice to perform uniform compensation, the accuracy of the clock of the display terminal is guaranteed, the clock calibration of the non-networked terminal is realized, clock differences caused by device aging and environmental factors can be effectively compensated, and the cost is not additionally increased.
Description
Technical Field
The application belongs to the technical field of clock calibration, and particularly relates to a display terminal clock calibration method and device and a display terminal.
Background
Clock display becomes the basic function of most display terminals, the accuracy of the clock is improved, the user experience and the product performance can be effectively improved, and the user experience of the terminal is directly influenced by the clock accuracy. In the traditional clock calibration, a plurality of timing modules are generally adopted to calculate clock errors, and then compensation is carried out to improve timing accuracy. This approach is complex to implement and overall costly. In the related art, when the clock of some display terminals runs inaccurately, the calibration of the terminal clock is realized through a network clock under the condition of networking. For example, consumer electronic display terminals all have networking functions, and a system clock is convenient for network synchronization, but display terminals of industrial equipment controller products often only have local control functions, do not have network clock synchronization conditions, and only can rely on a local clock circuit. The local clock circuit is easily affected by device differences, production processes and use environments, and clock deviation is often generated along with the lapse of time to affect the use of users.
Disclosure of Invention
In order to overcome the problems that the clock display of an unconnected display terminal is inaccurate and cannot be automatically calibrated in the related technology at least to a certain extent, the application provides a display terminal clock calibration method, a display terminal clock calibration device and a display terminal.
In a first aspect, the present application provides a display terminal clock calibration method, including:
acquiring clock deviation and interval time corresponding to two adjacent clock calibrations;
calculating a unit time calibration value according to the clock deviation and the interval time corresponding to the two adjacent clock calibrations;
acquiring a calibration clock period;
calculating a clock calibration value corresponding to the calibration clock period according to the calibration clock period and the unit time calibration value;
and calibrating the clock time based on the clock calibration value.
Further, the calculating a unit time calibration value according to the clock offset and the interval time corresponding to the two adjacent clock calibrations includes:
the unit time calibration value is the clock offset/interval time.
Further, the calculating a clock calibration value corresponding to the calibration clock cycle according to the calibration clock cycle and the unit time calibration value includes:
and the clock calibration value is the calibration clock period and the unit time calibration value.
Furthermore, the unit of the clock deviation is minutes, the unit of the interval time at least comprises days, and the unit of the calibration clock period corresponds to the unit of the interval time.
Further, the acquiring clock offsets corresponding to two adjacent clock calibrations includes:
acquiring a first clock display value before the (N + 1) th time of clock calibration;
acquiring a second clock display value after the (N + 1) th time of clock calibration;
and calculating the clock deviation corresponding to the clock calibration of two adjacent times according to the first clock display value and the second clock display value.
Further, acquiring an interval time corresponding to two adjacent clock calibrations includes:
acquiring a first time value corresponding to the Nth time of calibration clock;
acquiring a second time value corresponding to the (N + 1) th calibration clock;
calculating the interval time corresponding to the two adjacent clock calibrations according to the first time value and the second time value;
the second time value is not equal to the first time value.
In a second aspect, the present application provides a display terminal clock calibration apparatus, including:
the first acquisition module is used for acquiring clock deviation and interval time corresponding to two adjacent clock calibrations;
the first calculation module is used for calculating a unit time calibration value according to the clock deviation and the interval time corresponding to the two adjacent clock calibrations;
the second acquisition module is used for acquiring a calibration clock period;
the second calculation module is used for calculating a clock calibration value corresponding to the calibration clock period according to the calibration clock period and the unit time calibration value;
and the calibration module is used for calibrating the clock time based on the clock calibration value.
In a third aspect, the present application provides a display terminal device, comprising:
the clock module is connected with the display screen;
the controller is used for executing the display terminal clock calibration method according to the first aspect to calibrate the clock module;
the display screen is used for displaying the time corresponding to the clock module.
Further, the method also comprises the following steps:
and the power supply module provides a power supply for the display screen, the clock module and the controller.
Further, the power module includes: at least one of a rechargeable battery, a button battery and a large-capacity capacitor.
The technical scheme provided by the embodiment of the application can have the following beneficial effects:
the display terminal clock calibration method comprises the steps of obtaining clock deviation and interval time corresponding to adjacent two times of clock calibration, calculating a unit time calibration value according to the clock deviation and the interval time corresponding to the adjacent two times of clock calibration, obtaining a calibration clock period, calculating a clock calibration value corresponding to the calibration clock period according to the calibration clock period and the unit time calibration value, calibrating the clock time based on the clock calibration value, and uniformly compensating the clock deviation and the interval time of the two times of calibration clocks.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.
Fig. 1 is a flowchart illustrating a method for calibrating a clock of a display terminal according to an embodiment of the present disclosure.
Fig. 2 is a flowchart of a method for calibrating a clock of a display terminal according to another embodiment of the present application.
Fig. 3 is a functional block diagram of a display terminal clock calibration apparatus according to an embodiment of the present application.
Fig. 4 is a functional structure diagram of a display terminal according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described in detail below. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the examples given herein without making any creative effort, shall fall within the protection scope of the present application.
Fig. 1 is a flowchart of a display terminal clock calibration method according to an embodiment of the present application, and as shown in fig. 1, the display terminal clock calibration method includes:
s11: acquiring clock deviation and interval time corresponding to two adjacent clock calibrations;
s12: calculating a unit time calibration value according to the clock deviation and the interval time corresponding to the adjacent two clock calibrations;
s13: acquiring a calibration clock period;
s14: calculating a clock calibration value corresponding to the calibration clock period according to the calibration clock period and the unit time calibration value;
s15: and calibrating the clock time based on the clock calibration value.
When the display of the clock of some display terminals is inaccurate, the calibration of the clock of the terminal is realized through the network clock under the condition of networking. For example, consumer electronic display terminals all have networking functions, and a system clock is convenient for network synchronization, but display terminals of industrial equipment controller products often only have local control functions, do not have network clock synchronization conditions, and only can rely on a local clock circuit. The local clock circuit is easily affected by device differences, production processes and use environments, and clock deviation is often generated along with the lapse of time to affect the use of users.
In this embodiment, the method for calibrating the clock of the display terminal includes obtaining clock skew and interval time corresponding to two adjacent clock calibrations, calculating a unit time calibration value according to the clock skew and interval time corresponding to the two adjacent clock calibrations, obtaining a calibration clock period, calculating a clock calibration value corresponding to the calibration clock period according to the calibration clock period and the unit time calibration value, and performing uniform compensation by combining the clock skew and the interval time of the two clock calibrations, so that the accuracy of the clock of the display terminal is guaranteed, the clock skew caused by aging of devices and environmental factors can be effectively compensated, and the cost is not additionally increased.
Fig. 2 is a flowchart of a display terminal clock calibration method according to another embodiment of the present application, and as shown in fig. 2, the display terminal clock calibration method includes:
s201: acquiring a first clock display value before the (N + 1) th time of clock calibration;
when the user performs the time setting operation, the set time is written into the clock chip, and the time is the set time (the set time is recorded as N).
S202: acquiring a second clock display value after the (N + 1) th time of clock calibration;
s203: and calculating the clock deviation corresponding to the two adjacent clock calibrations according to the first clock display value and the second clock display value.
The unit of clock offset is minutes, and in some embodiments, the time offset M (minutes) of this calibration is calculated from the time before the last set time and twice after the set time.
S204: acquiring a first time value corresponding to the Nth time of calibration clock;
s205: acquiring a second time value corresponding to the (N + 1) th calibration clock;
s206: calculating the interval time corresponding to the two adjacent clock calibrations according to the first time value and the second time value;
the first time value and the second time value are dates, the second time value is not equal to the first time value, and if the first time value and the second time value are on the same day, the interval time is calculated according to hours or minutes by the first time value and the second time value.
The units of the interval time correspond to the units of the calibration clock cycle, including but not limited to days, hours, or minutes.
And calculating the period P (days) of the set time according to the time difference between the current N +1 and the last set time N. If the time is the first set time, namely N is 1, the calculation is started from the next set time.
S207: calculating a unit time calibration value according to the clock deviation and the interval time corresponding to the adjacent two clock calibrations;
the unit time calibration value is the clock offset/interval time.
S208: acquiring a calibration clock period;
s209: calculating a clock calibration value corresponding to the calibration clock period according to the calibration clock period and the unit time calibration value;
and the clock calibration value is the calibration clock period and the unit time calibration value.
S210: and calibrating the clock time based on the clock calibration value.
The calibration clock period is, for example, R (days), and the time T ═ R × M/P required for calibration every R days is calculated. Since the time error is usually very small, and the deviation of several minutes usually occurs after accumulating several months, the calibration clock period may be selected to be relatively long, such as R ═ 10 (days). Thus, the times of manually setting the time by the user are less and less, and the clock deviation is smaller and smaller.
In some embodiments, daily compensation is used, i.e., T1 ═ M/P, which allows the clock to achieve greater accuracy.
In some embodiments, after the time setting is completed, the display terminal pops up a dialog box to prompt the user of the number of times of calibrating the clock, the compensated time and whether the calibration is successful or not, and the method is convenient and friendly to a user interaction interface.
In the embodiment, the clock time display method and the clock device have the advantages that the system clock time (current time) set by a user is compared with the time recorded by the clock chip, and cycle uniformity compensation is performed by combining the periods of setting time nearly twice, so that the clock display is more accurate, the frequency of time set by the user can be greatly reduced, automatic correction and calibration of the time of an unconnected network type terminal are realized, clock deviation caused by device and environment difference is effectively avoided, the cost is lower, and the economic benefit is obvious.
An embodiment of the present invention provides a display terminal clock calibration apparatus, as shown in a functional structure diagram of fig. 3, the display terminal clock calibration apparatus includes:
the first obtaining module 31 is configured to obtain a clock offset and an interval time corresponding to two adjacent clock calibrations;
in this embodiment, the first obtaining module 31 is configured to:
acquiring a first clock display value before the (N + 1) th time of clock calibration;
acquiring a second clock display value after the (N + 1) th time of clock calibration;
and calculating the clock deviation corresponding to the two adjacent clock calibrations according to the first clock display value and the second clock display value.
Acquiring a first time value corresponding to the Nth time of calibration clock;
acquiring a second time value corresponding to the (N + 1) th calibration clock;
calculating the interval time corresponding to the two adjacent clock calibrations according to the first time value and the second time value;
the second time value is not equal to the first time value.
The first calculation module 32 is configured to calculate a unit time calibration value according to the clock offset and the interval time corresponding to two adjacent clock calibrations;
a second obtaining module 33, configured to obtain a calibration clock period;
a second calculating module 34, configured to calculate a clock calibration value corresponding to the calibration clock period according to the calibration clock period and the unit time calibration value;
and the calibration module 35 is configured to calibrate the clock time based on the clock calibration value.
In this embodiment, the clock offset and the interval time corresponding to two adjacent clock calibrations are acquired through the first acquisition module, the first calculation module calculates the calibration value of unit time according to the clock offset and the interval time corresponding to the two adjacent clock calibrations, the second acquisition module acquires the calibration clock period, the second calculation module calculates the clock calibration value corresponding to the calibration clock period according to the calibration clock period and the unit time calibration value, the calibration module calibrates the clock time based on the clock calibration value, and performs uniform compensation by combining the clock offset and the interval time of the two calibration clocks, so that the accuracy of the clock of the display terminal is guaranteed, the calibration of the non-networked terminal clock is realized, the clock differences caused by aging of devices and environmental factors can be effectively compensated, and the cost is not additionally increased.
An embodiment of the present invention provides a display terminal, and as shown in a functional structure diagram of fig. 4, the display terminal includes:
a display screen 41, a clock module 42, and a controller 43;
the controller 43 is configured to perform the display terminal clock calibration method according to the above embodiment to calibrate the clock module 42;
the display screen 41 is used for displaying the time corresponding to the clock module 42.
In this embodiment, the clock module is, for example, a PCF8563 clock chip, and can operate independently without depending on a clock crystal oscillator in the MCU.
In some embodiments, further comprising:
and the power supply module 44, the power supply module 44 provides power supply for the display screen 41, the clock module 42 and the controller 43.
In some embodiments, power module 44 includes, but is not limited to: rechargeable batteries, button batteries, large-capacity capacitors and the like.
The energy storage unit with larger capacity, such as a rechargeable battery, a button battery or a large-capacity capacitor, can enable the clock module to have longer power-down endurance.
The clock chip continues to work after short-term power failure, and the condition of resetting time caused by abnormal power failure is prevented.
The display screen 41 is, for example, an LCD.
In some embodiments, the display screen 41 is used to display a friendly clock calibration interface to facilitate clock calibration.
In this embodiment, the clock module is calibrated by the controller executing the display terminal clock calibration method, the display screen is used for displaying the time corresponding to the clock module, the system clock time set by the user is compared with the time recorded by the clock chip, and cycle uniformity compensation is performed by combining the two time setting periods, so that the clock display is more accurate.
It is understood that the same or similar parts in the above embodiments may be mutually referred to, and the same or similar parts in other embodiments may be referred to for the content which is not described in detail in some embodiments.
It should be noted that, in the description of the present application, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Further, in the description of the present application, the meaning of "a plurality" means at least two unless otherwise specified.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and the scope of the preferred embodiments of the present application includes other implementations in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present application.
It should be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present application may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc.
In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.
It should be noted that the present invention is not limited to the above-mentioned preferred embodiments, and those skilled in the art can obtain other products in various forms without departing from the spirit of the present invention, but any changes in shape or structure can be made within the scope of the present invention with the same or similar technical solutions as those of the present invention.
Claims (10)
1. A display terminal clock calibration method is characterized by comprising the following steps:
acquiring clock deviation and interval time corresponding to two adjacent clock calibrations;
calculating a unit time calibration value according to the clock deviation and the interval time corresponding to the two adjacent clock calibrations;
acquiring a calibration clock period;
calculating a clock calibration value corresponding to the calibration clock period according to the calibration clock period and the unit time calibration value;
and calibrating the clock time based on the clock calibration value.
2. The method for calibrating a clock of a display terminal according to claim 1, wherein the calculating a unit time calibration value according to the clock skew and the interval time corresponding to the two adjacent clock calibrations comprises:
the unit time calibration value is the clock offset/interval time.
3. The method for calibrating a clock of a display terminal according to claim 2, wherein said calculating a clock calibration value corresponding to the calibration clock cycle according to the calibration clock cycle and the unit time calibration value comprises:
and the clock calibration value is the calibration clock period and the unit time calibration value.
4. The method according to claim 3, wherein the clock skew is measured in minutes, the interval time is measured in units of at least days, and the calibration clock period is measured in units of the interval time.
5. The method for calibrating a clock of a display terminal according to claim 1, wherein the obtaining clock offsets corresponding to two adjacent clock calibrations comprises:
acquiring a first clock display value before the (N + 1) th time of clock calibration;
acquiring a second clock display value after the (N + 1) th time of clock calibration;
and calculating the clock deviation corresponding to the clock calibration of two adjacent times according to the first clock display value and the second clock display value.
6. The method for calibrating the clock of the display terminal according to claim 5, wherein the obtaining of the interval time corresponding to two adjacent clock calibrations comprises:
acquiring a first time value corresponding to the Nth time of calibration clock;
acquiring a second time value corresponding to the (N + 1) th calibration clock;
calculating the interval time corresponding to the two adjacent clock calibrations according to the first time value and the second time value;
the second time value is not equal to the first time value.
7. A display terminal clock calibration apparatus, comprising:
the first acquisition module is used for acquiring clock deviation and interval time corresponding to two adjacent clock calibrations;
the first calculation module is used for calculating a unit time calibration value according to the clock deviation and the interval time corresponding to the two adjacent clock calibrations;
the second acquisition module is used for acquiring a calibration clock period;
the second calculation module is used for calculating a clock calibration value corresponding to the calibration clock period according to the calibration clock period and the unit time calibration value;
and the calibration module is used for calibrating the clock time based on the clock calibration value.
8. A display terminal, comprising:
the clock module is connected with the display screen;
the controller is used for executing the display terminal clock calibration method according to any one of claims 1-6 to calibrate the clock module;
the display screen is used for displaying the time corresponding to the clock module.
9. The display terminal of claim 8, further comprising:
and the power supply module provides a power supply for the display screen, the clock module and the controller.
10. The display terminal of claim 9, wherein the power module comprises:
at least one of a rechargeable battery, a button battery and a large-capacity capacitor.
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| CN202111299093.9A CN114138056A (en) | 2021-11-04 | 2021-11-04 | Display terminal clock calibration method and device and display terminal |
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