CN102169719A - One time programmable (OTP) resistive random access memory (RRAM) as well as read-write circuit and programming method thereof - Google Patents
One time programmable (OTP) resistive random access memory (RRAM) as well as read-write circuit and programming method thereof Download PDFInfo
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Abstract
The invention belongs to the technical field of resistive random access memories (RRAMs), in particular relating to an one time programmable (OTP) RRAM as well as a read-write circuit and programming method thereof; by using a symmetric 2T2R structure, the OTP RRAM can be used for judging a data storage state by comparing the currents flowing through two memistors R; and meanwhile, in combination with a characteristic that an OTP RRAM user only needs to program one time, the memistors R in the OTP RRAM are all placed in a high impedance state and consigned to the user for programming. The OTP RRAM has the characteristics of low power consumption, small area and power analysis attack resistance in programming, thereby being especially suitable for the embedded application.
Description
Technical field
The invention belongs to resistance random access memory technical field (Resistive Random Access Memory, RRAM), relate in particular to a kind of based on 2T (Transistor, gate tube) 2R (Resistance, memory resistor) structure, have ability that anti-power consumption analysis attacks, disposable programmable (On-Time Progamable, OTP) resistance random access memory, and the read/write circuit of this one-time programmable resistance random access memory and method of operating thereof.
Background technology
The incompatible canned data of data set of semiconductor memory use " 0 " or " 1 ", form each memory device unit of mass storage and can store data (" 0 " or " 1 ").Usually, whether continue to be stored in the storer to judge with the data of power down background storage, storer can and be divided into volatile memory and nonvolatile memory, wherein data can continue to keep after the nonvolatile memory power down.
Simultaneously, at information security field, the level security of storer institute canned data is an important aspect.For example, be used for storing the storer of password, need the security of height.And power consumption analysis (Power Analysis) attack is one of the most frequently used attack means of hacker, promptly by storage unit is carried out read operation, power consumption size when each storage unit is carried out read operation can analysis and judgement go out each storage unit institute stored data states.The power consumption of storer when reading " 0 " and reading " 1 " that the ultimate principle that above power consumption analysis is attacked is based on prior art is inequality.
For RRAM, power consumption analysis mainly is the power consumption that electric current produced by the memory resistor of " high-impedance state " or " low resistance state ", for traditional RRAM structure, because the read signal that applies is certain, power consumption by " high-impedance state " memory resistor is much smaller than the power consumption by " low resistance state " memory resistor, therefore, can easily pick out the resistance states of memory resistor, and then sense data.
Simultaneously, disposable programmable (OTP) storer is widely used in various embedded systems, and usually, embedded system requirement otp memory is low in energy consumption, area occupied is little, simultaneously, also requires to have the characteristics of information stores safety, especially can resist power consumption analysis to attack.Therefore, this invention has proposed the OTP resistance random access memory that a kind of anti-power consumption analysis is attacked, low in energy consumption, that area is little in conjunction with the characteristics of resistance random access memory.
Summary of the invention
The technical problem to be solved in the present invention is, low and otp memory embeds the low-power consumption of using, the requirement of small size based on existing otp memory data-carrier store security performance, and proposes a kind of OTP resistance random access memory, read/write circuit and programmed method thereof.
OTP resistance random access memory provided by the invention can be used for anti-power consumption analysis to be attacked, and comprising:
First memory resistor,
First gate tube that is used for described first memory resistor of gating,
Second memory resistor, and
Second gate tube that is used for described second memory resistor of gating;
Wherein, before the disposable programmable operation, first memory resistor and second memory resistor all place high-impedance state; During the disposable programmable operation, be low resistance state with one of them memory resistor set operation;
Wherein, described memory resistor is binary or the above multi-element metal oxide of binary, and described first memory resistor and second memory resistor are connected to first bit line, second bit line.
According to OTP resistance random access memory provided by the invention, wherein, after described one-time programmable resistance random access memory was programmed operation, when first memory resistor was in high-impedance state and second memory resistor and is in low resistance state, described resistance random access memory was stored first data mode; When first memory resistor was in low resistance state and second memory resistor and is in high-impedance state, described resistance random access memory was stored second data mode.The control end of described first gate tube and second gate tube is connected in parallel in same word line.Described metal oxide is one of oxide, titanyl compound, the oxide of zirconium, the oxide of aluminium, the oxide of niobium, the oxide of tantalum, the oxide of hafnium, the oxide of molybdenum, the oxide of zinc of oxide, the nickel of copper.Described first memory resistor is identical with the second memory resistor structural parameters, and described first gate tube is identical with the second gate tube structural parameters.
According to OTP resistance random access memory provided by the invention, wherein, when reading first data mode of described one-time programmable resistance random access memory or second data mode, apply the read operation signal respectively simultaneously in first memory resistor, second memory resistor on first bit line and second bit line, the electric current sum that flows through on the electric current that flows through on first bit line and second bit line is identical.Described read operation signal is current signal or voltage signal.
As preferred embodiment, described first gate tube and second gate tube are metal-oxide-semiconductor.Be connected in parallel in same source line simultaneously as the source end of the metal-oxide-semiconductor of first gate tube and source end as the metal-oxide-semiconductor of second gate tube.The drain terminal and first memory resistor as the metal-oxide-semiconductor of first gate tube are connected in series, and are connected in series as the drain terminal and second memory resistor of the metal-oxide-semiconductor of second gate tube.
According to still another embodiment of the invention, described first gate tube and second gate tube are triode or diode.
The present invention provides the read/write circuit of the above OTP resistance random access memory simultaneously, is used for described one-time programmable resistance random access memory is arranged the one-time programmable resistance random access memory array program that forms according to the form of row and column, and it comprises:
The reading circuit module is used to read the data mode of described one-time programmable resistance random access memory;
Driver module is write in set, is used to finish the set programming operation that memory resistor changes to low resistance state from high-impedance state; And
Outer filling formula port, be used for importing the external reset circuit module reset signal, with first memory resistor of described one-time programmable resistance random access memory and second memory resistor all reset operation be high-impedance state.
According to the read/write circuit of OTP resistance random access memory provided by the present invention, wherein, described OTP resistance random access memory array comprises:
Be used to control the whether bit line gate tube of conducting of bit line; And
The selection wire that is used for control bit line selection siphunculus.
Described read/write circuit also comprises the source line, the shared source line of OTP journey resistance random access memory of every adjacent two row.Described outer filling formula port is connected in described source line.
Further, the present invention also provides the programmed method of OTP resistance random access memory.This method may further comprise the steps:
(1) before described one-time programmable resistance random access memory is dispatched from the factory encapsulation, connect the external reset circuit module through outer filling formula port, the reset signal that the external reset circuit module is produced all is written as high-impedance state with first memory resistor or second memory resistor of one-time programmable resistance random access memory;
When (2) user uses, choose the one-time programmable resistance random-access memory unit of desiring programming operation at one-time programmable resistance random access memory array; And
(3) write driver module by set and apply asserts signal, a memory resistor in this one-time programmable resistance random-access memory unit is written as low resistance state in the one-time programmable resistance random-access memory unit of having chosen.
As the preferred embodiment of this programmed method, also be included in the step (1b) between step (1) and the step (2): cut off outer filling formula port.
Technique effect of the present invention is, the OTP resistance random access memory adopts the 2T2R structure of symmetry, also relies on the mutual comparison of the size of current of passing through two memory resistor R respectively to differentiate store status, therefore the power consumption when reading " 1 " and reading " 0 " is all identical, attacks thereby can be used in anti-power consumption analysis; Further, the characteristics that only need one-time programming in conjunction with OTP resistance random access memory user, all placing high-impedance state to consign to user program memory resistor R in the OTP resistance random access memory uses, utilization to low in energy consumption, the Set pulse signal characteristic of simple of the Set (position) of low resistance state process, can realize the low-power consumption of OTP resistance random access memory, the characteristics of small size from high-impedance state.
Description of drawings
Fig. 1 is the structural representation of the OTP resistance random access memory that provides of the embodiment of the invention;
Fig. 2 is the programming synoptic diagram of prior art 1T1R resistance random access memory;
Fig. 3 is the read/write circuit structural representation of the OTP resistance random access memory that provides of the embodiment of the invention;
Fig. 4 is the read/write circuit structural representation of the OTP resistance random access memory that provides of further embodiment of this invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
Figure 1 shows that the structural representation of the OTP resistance random access memory that the embodiment of the invention provides.As shown in Figure 1, provided the OTP resistance random access memory 10 of a storage unit.OTP resistance random access memory 10 comprises first memory resistor 11 and first gate tube 12, second memory resistor 13 that is in series with first memory resistor and second gate tube 14 that is in series with second memory resistor.Memory resistor is defined as R (Resistance), gate tube is defined as T (Transistor), so this resistance random access memory is the 2T2R structure.In this embodiment, an end of first memory resistor 11 is connected with first gate tube 12, and the other end also is connected with bit line 1; One end of second memory resistor 13 is connected with second gate tube 14, and the other end also is connected with bit line 2.First gate tube 12 and second gate tube 14 can make its conducting and shutoff by electric signal, in the present embodiment, with the gate tube is (conducting when applying high level signal on the grid) explanation of NMOS pipe, in other embodiments, gate tube also can be PMOS pipe or triode or diode etc., the particular type of gate tube is not limited by the present invention, and those skilled in the art can need as the case may be and select dissimilar gate tubes.When gate tube is the NMOS pipe, the grid end of the grid end of first gate tube 12 and second gate tube 142 is parallel-connected to same word line simultaneously, the drain terminal of first gate tube 12 directly is connected with first memory resistor 11, the leakage of second gate tube 14 is disconnected directly to be connected with second memory resistor 13, and the source end of the source end of first gate tube 12 and second gate tube 14 is parallel to same source line simultaneously.First gate tube 12 is two identical gate tubes with second gate tube 14, has identical structural parameters, and same, first memory resistor 11 also is two identical memory resistor with second memory resistor 13, has identical structural parameters.First gate tube 12 and second gate tube 14 can made in same process for making and finish for a collection of device, and therefore, both have basic identical threshold voltage, essentially identical conducting resistance etc.First memory resistor 11 and second memory resistor 13 are preferably with a collection of memory resistor and finish in same process for making, because first memory resistor 11 and second memory resistor 13 can be two adjacent memory resistor on physical space, thereby can maximum possible avoid because the technological fluctuation difference causes the property difference of two memory resistor, therefore, first memory resistor 11 and second memory resistor 13 have essentially identical storage characteristics.
Continue as shown in Figure 1, first memory resistor 11, second memory resistor 13 is binary or the above multi-element metal oxide of binary with storage characteristics, first memory resistor and second memory resistor can be the oxide of copper, the oxide of nickel, titanyl compound, the oxide of zirconium, the oxide of aluminium, the oxide of niobium, the oxide of tantalum, the oxide of hafnium, the oxide of molybdenum or the oxide of zinc, these metal oxides can realized high-impedance state (High Resistance under electric signal (comprising voltage signal and current signal) effect, HR) and low resistance state (LowResistance, LR) conversion back and forth between, thus realize data storage.
Figure 2 shows that the programming synoptic diagram of prior art 1T1R resistance random access memory.In the 2T2R structure OTP resistance random access memory shown in Figure 1, first memory resistor 11 and first gate tube 12 got wherein are exactly the 1T1R structural resistance random access memory shown in Fig. 2 the right.This 1T1R resistance random access memory is the structure of traditional type, and the left side has schematically provided the programming signal synoptic diagram of 1T1R resistance random access memory among Fig. 2.When memory resistor 11 is high-impedance state, apply specific voltage pulse signal or current pulse signal at its two ends, memory resistor 11 can be converted to low resistance state from high-impedance state, this process is referred to as set (Set) process, and this specific voltage pulse signal or current pulse signal also are referred to as the Set pulse; On the contrary, when when memory resistor 11 is low resistance state, apply specific voltage pulse signal or current pulse signal at its two ends, memory resistor 11 can be converted to high-impedance state from low resistance state, this process (Reset) process that is referred to as to reset, this specific voltage pulse signal or current pulse signal also are referred to as the Reset pulse.In the prior art, the Set of resistance random access memory and Reset operation need the pulse signal shown in the left side among Fig. 2 usually, and as shown in Figure 2, wherein 16 is the Set pulse, and 18 is the Reset pulse.For various resistance random access memories based on metal oxide materials, the Set pulsion phase is low and the burst length is long to the Reset pulse height, and therefore, the Set pulsion phase is to simply.And in other further embodiment, the Reset pulse may adopt stride to increase progressively the pulse of form, and therefore, the algorithm of Set pulse also may be simple relatively.Simple Set pulse waveform means that the periphery programming driving circuit of the storer that is used to produce this Set pulse waveform wants simple and occupy less chip area.Simultaneously, according to power basic calculating formula: P=I
2R, because Set when operation resistance R is a high-resistance resistors, the Resistance states resistance when Reset operate, therefore, the electric current I that the electric current I of Set operation is operated much smaller than Reset.And then the power consumption of the Set operation of resistance random access memory is much smaller than the power consumption of Reset operation.
Continue as shown in Figure 1, power consumption based on the Set of resistance random access memory operation only need be used the disposable programmable process much smaller than the power consumption and the OTP resistance random access memory of Reset operation in client, therefore our the OTP resistance random access memory embodiment illustrated in fig. 1 of proposition also has following characteristics: before the disposable programmable operation, first memory resistor 11 and second memory resistor 13 all place high-impedance state; During the disposable programmable operation, be low resistance state with one of them memory resistor set operation.Like this, can make full use of that the Set operative algorithm is simple, pulse waveform is simple, characteristics low in energy consumption, so the needed chip periphery driving circuit of this embodiment OTP resistance random access memory is simple relatively and low in energy consumption.In a certain embodiment, OTP resistance random access memory shown in Figure 1 can be a low resistance state with first memory resistor, 11 set operation when disposable programmable is operated, and at this moment the store status of OTP resistance random access memory is defined as " 1 "; Can be low resistance state with second memory resistor, 11 set operation also, this be that the store status of OTP resistance random access memory at this moment is defined as " 0 ".Because OTP resistance random access memory embodiment illustrated in fig. 1 is the 2T2R structure of symmetry, the definition mode of concrete store status is not limited by the present invention, promptly also can define first memory resistor 11 for high-impedance state, when second memory resistor is low resistance state, the store status of OTP resistance random access memory is defined as " 1 "; Define first memory resistor 11 for low resistance state, when second memory resistor is high-impedance state, the store status of OTP resistance random access memory is defined as " 0 ".
Further, the read operation characteristics in conjunction with Fig. 1 embodiment OPT resistance random access memory illustrate the characteristics that it sees the power consumption analysis attack.
Read operation method for OTP resistance random access memory 10, shown in 1, at first, apply signal on the word line and make first gate tube 12,13 conductings simultaneously of second gate tube, apply voltage (perhaps electric current) signal of read operation between bit line 1 and the source line, also apply voltage (perhaps electric current) signal of same read operation between bit line 2 and the source line, finish the memory resistor two ends and apply read operation electric signal step, need to prove that this read operation voltage (perhaps electric current) signal can not produce obviously influence to the resistance states of memory resistor, promptly read operation voltage (perhaps electric current) signal is lower than memory resistor 11,13 Reset (resetting) operating voltage and Set (set) operating voltage; Secondly, the current signal that flows through of the current signal that flows through by first memory resistor, 11 two ends and second memory resistor, 13 two ends compares the data mode of judgement resistance random access memory 10.In this embodiment, during current signal that the current signal that first memory resistor, 11 two ends are flow through flows through greater than second memory resistor, 13 two ends, resistance random access memory 10 is in second data mode, thereby has read data " 1 "; During current signal that the current signal that first memory resistor, 11 two ends are flow through flows through less than second memory resistor, 13 two ends, resistance random access memory 10 is in first data mode, thereby has read data " 0 ".
According to the method for above-mentioned read operation as can be known, because the OTP resistance random access memory 10 of this 2T2R structure is a symmetrical structure, no matter be storage " 0 " or storage " 1 ", always have a memory resistor to be in high-impedance state, another memory resistor is in low resistance state, therefore, no matter be to read " 0 " or reading " 1 ", the electric current sum that flows through on bit line 1 and the bit line 2 is identical, under the same read signal condition, the power consumption of reading that each resistance random access memory produced also is identical.Need to prove, above-described " identical " be identical on the theory significance just, realization circuit in the reality is not the identical of absolute sense, may be for roughly the same, promptly described " electric current sum ", " reading power consumption " can there are differences within the specific limits, this " difference " is the difference that the analytical attack of hacker in the prior art is difficult to recognize, for example its difference can be 10
-6Ampere or 10
-6In the order of magnitude scope of watt.Therefore, OTP resistance random access memory embodiment illustrated in fig. 1 is outside having low-power consumption, the simple advantage of peripheral drive circuit, also have the characteristics that anti-power consumption analysis is attacked, this OTP resistance random access memory especially is adapted to the embedded OTP storage of low-power consumption requirement, high data security memory requirement and uses.
Further, this invention provides the read/write circuit of OTP resistance random access memory shown in Figure 1.
Figure 3 shows that the read/write circuit structural representation of the OTP resistance random access memory that the embodiment of the invention provides.As shown in Figure 3, this embodiment provides the read/write circuit structure of OTP resistance random access memory, and this read/write circuit structure is used for the OTP resistance random access memory array 20 that comprises a plurality of OTP resistance random access memories shown in Figure 1 is carried out read-write operation.In this embodiment, the read/write circuit of corresponding OTP resistance random access memory array 20 comprises that reading circuit module 30, set writes driver module 40 and outer filling formula port 50.In the OTP resistance random access memory array 20, be equipped with a bit line gate tube on every bit lines.The control end of bit line gate tube is connected in selection wire (Sel), and two bit lines of same OTP resistor random-access memory unit correspondence are controlled by same selection wire.As shown in Figure 3, the bit line gate tube on bit line BL1, the BL1_ is connected in same selection wire Sel1, and the bit line gate tube on bit line BL2, the BL2_ is connected in same selection wire Sel2.By selection wire can control bit line selection siphunculus conducting with close, therefore, can be by applying signal on word line (WL) and the selection wire, certain OTP resistor random-access memory unit of desire programming operation in the selection array.Connect among two bit lines BL, the BL_ of reading circuit module 30, BL is connected with the bit line of odd bits in the array, and BL_ is connected with the bit line of even bit in the array.BL, BL_ are connected in parallel in set and write driver module 40, thereby the Set signal of writing driver module 40 can put on the memory resistor of bit line.Further, in this embodiment, the shared source line SL of adjacent two row OTP resistor random-access memory units, outer filling formula port 50 is connected in the storage array neutrality line by source line (SL).Simultaneously, can connect outside reset circuit module 60 on the outer filling formula port 50, outside reset circuit module 60 applies the Reset signal in by filling formula port 50, thereby can carry out set programming to memory resistor in the array.What need further specify is, the memory resistor that is applicable to that Reset is opposite with the Set direction of operating embodiment illustrated in fig. 3, i.e. and the polarity of signal that Reset pulse and Set pulse put on memory resistor respectively is opposite.
Continuation describes its operation scheme for programming with reference to figure 3.
The first step, the OTP resistance random access memory dispatches from the factory before the encapsulation, connect external reset circuit module 60 through outer filling formula port 50, apply the Reset pulse signal, all memory resistor in the OTP resistance random access memory array are programmed for high-impedance state by reset circuit module 60.Because the Reset operating impulse relative complex of resistance random access memory, reset circuit module be therefore relative complex also, still, this reset circuit module is outside, is not interposing in the chip, therefore can save chip area.In this embodiment, switch reset_en conducting, the Reset signal that reset circuit module 60 is produced passes through reset_en, SL, gate tube, memory resistor, bit line gate tube, reset_en successively to earth terminal.After all memory resistor all placed high-impedance state, the OTP resistance random access memory placed initial state, was prepared for the OTP programming.
In second step, when the user uses, choose the OTP resistance random access memory of desiring programming operation by word line or selection wire.In this embodiment, for example, can on WL1 and Sel1, apply high level and make its gate tube conducting of controlling, thus the OTP resistor random-access memory unit of choosing desire to programme.
In the 3rd step, write driver module 40 by set and apply Set signal certain memory resistor, thereby this memory resistor set operation is become low resistance state, thereby realize writing " 0 " or one writing in the OTP resistance random access memory of choosing.In this embodiment, switch set_en conducting, set is write set operation signal that driver module 40 produced and is passed through set_en, trans1 or trans2 (trans1 and trans2 are by the Data_ctr signal controlling, and both are not both conducting), bit line, memory resistor, gate tube, set_en successively to earth terminal.
In another operation scheme for programming embodiment, can the first step after, increased before second step and cut off outer filling formula port 50 steps, from then on outer filling formula port 50 no longer is connected with the external reset circuit module.Show as on product, after dispatching from the factory, this outer filling formula port 50 does not have the packed port of drawing.Therefore, the 3rd the step finish write operation after, this OTP resistance random access memory cannot be operated by Reset again, thus the data that can avoid being stored in the OTP resistance random access memory attacked by Reset, further improve the security of data storage.
Further, other embodiment of the read/write circuit structure of the OTP resistance random access memory that can also propose to be applicable to that Reset is identical with the Set direction of operating.Figure 4 shows that the read/write circuit structural representation of the OTP resistance random access memory that further embodiment of this invention provides.Contrast this Fig. 3 and embodiment illustrated in fig. 4, its main difference is that outer filling formula port 50 and set are write driving 40 and all is connected in the same end of memory resistor, and therefore, to the memory resistor programming operation time, Reset is identical with the Set direction of operating.The programmed method of the OTP resistance random access memory of the programmed method of the OTP resistance random access memory of the read/write circuit of Fig. 4 embodiment and read/write circuit embodiment illustrated in fig. 3 is basic identical, is not described in detail at this.
Under situation without departing from the spirit and scope of the present invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the specific embodiment described in the instructions.
Claims (17)
1. one-time programmable resistance random access memory is characterized in that comprising:
First memory resistor,
First gate tube that is used for described first memory resistor of gating,
Second memory resistor, and
Second gate tube that is used for described second memory resistor of gating;
Before the disposable programmable operation, first memory resistor and second memory resistor all place high-impedance state; During the disposable programmable operation, be low resistance state with one of them memory resistor set operation;
Wherein, described memory resistor is binary or the above multi-element metal oxide of binary, and described first memory resistor and second memory resistor are connected to first bit line, second bit line.
2. one-time programmable resistance random access memory according to claim 1, it is characterized in that, after described one-time programmable resistance random access memory is programmed operation, when first memory resistor was in high-impedance state and second memory resistor and is in low resistance state, described resistance random access memory was stored first data mode; When first memory resistor was in low resistance state and second memory resistor and is in high-impedance state, described resistance random access memory was stored second data mode.
3. one-time programmable resistance random access memory according to claim 1 is characterized in that, the control end of described first gate tube and second gate tube is connected in parallel in same word line.
4. one-time programmable resistance random access memory according to claim 1 is characterized in that, described first gate tube and second gate tube are metal-oxide-semiconductor.
5. one-time programmable resistance random access memory according to claim 4 is characterized in that, is connected in parallel in same source line simultaneously as the source end of the metal-oxide-semiconductor of first gate tube and source end as the metal-oxide-semiconductor of second gate tube.
6. one-time programmable resistance random access memory according to claim 4 is characterized in that, is connected in series as the drain terminal and first memory resistor of the metal-oxide-semiconductor of first gate tube, is connected in series as the drain terminal and second memory resistor of the metal-oxide-semiconductor of second gate tube.
7. one-time programmable resistance random access memory according to claim 1, it is characterized in that described metal oxide is one of oxide, titanyl compound, the oxide of zirconium, the oxide of aluminium, the oxide of niobium, the oxide of tantalum, the oxide of hafnium, the oxide of molybdenum, the oxide of zinc of oxide, the nickel of copper.
8. one-time programmable resistance random access memory according to claim 1 is characterized in that, described first memory resistor is identical with the second memory resistor structural parameters, and described first gate tube is identical with the second gate tube structural parameters.
9. one-time programmable resistance random access memory according to claim 1, it is characterized in that, when reading first data mode of described one-time programmable resistance random access memory or second data mode, apply the read operation signal respectively simultaneously in first memory resistor, second memory resistor on first bit line and second bit line, the electric current sum that flows through on the electric current that flows through on first bit line and second bit line is identical.
10. one-time programmable resistance random access memory according to claim 9 is characterized in that, described read operation signal is current signal or voltage signal.
11. one-time programmable resistance random access memory according to claim 1 is characterized in that, described first gate tube and second gate tube are triode or diode.
12. read/write circuit of one-time programmable resistance random access memory according to claim 1, be used for one-time programmable resistance random access memory is according to claim 1 arranged the one-time programmable resistance random access memory array program that forms according to the form of row and column, it is characterized in that, comprising:
The reading circuit module is used to read the data mode of described one-time programmable resistance random access memory;
Driver module is write in set, is used to finish the set programming operation that memory resistor changes to low resistance state from high-impedance state; And
Outer filling formula port, be used for importing the external reset circuit module reset signal, with first memory resistor of described one-time programmable resistance random access memory and second memory resistor all reset operation be high-impedance state.
13. read/write circuit according to claim 12 is characterized in that, described one-time programmable resistance random access memory array comprises:
Be used to control the whether bit line gate tube of conducting of bit line; And
The selection wire that is used for control bit line selection siphunculus.
14. read/write circuit according to claim 12 is characterized in that, described read/write circuit also comprises the source line, the shared source line of one-time programmable resistance random access memory of every adjacent two row.
15. read/write circuit according to claim 14 is characterized in that, described outer filling formula port is connected in described source line.
16. the programmed method of one-time programmable resistance random access memory according to claim 1 is characterized in that, may further comprise the steps:
(1) in described one-time programmable resistance random access memory, connect the external reset circuit module through outer filling formula port, the reset signal that the external reset circuit module is produced all is written as high-impedance state with first memory resistor or second memory resistor of one-time programmable resistance random access memory;
(2) select to desire the one-time programmable resistance random-access memory unit of programming operation at one-time programmable resistance random access memory array; And
(3) write driver module by set and apply asserts signal, a memory resistor in this one-time programmable resistance random-access memory unit is written as low resistance state in the one-time programmable resistance random-access memory unit of having chosen.
17. programmed method as claimed in claim 16 is characterized in that, also is included in the step (1b) between step (1) and the step (2): cut off outer filling formula port.
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| WO2015131775A1 (en) * | 2014-03-03 | 2015-09-11 | 山东华芯半导体有限公司 | 2-1t1r rram storage unit and storage array |
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| CN105047225B (en) * | 2015-07-14 | 2018-10-16 | 复旦大学 | A kind of write-protect circuit for the nonvolatile memory for preventing from rewriting |
| CN105047225A (en) * | 2015-07-14 | 2015-11-11 | 复旦大学 | Nonvolatile memory write protection circuit capable of avoiding rewriting |
| CN106856101A (en) * | 2015-12-08 | 2017-06-16 | 华邦电子股份有限公司 | Resistive memory and its memory cell |
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