CN100573724C - The prison mistake and the error correction method of software and hardware combining - Google Patents
The prison mistake and the error correction method of software and hardware combining Download PDFInfo
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Abstract
The invention belongs to the semiconductor memory technologies field, be specially fault monitoring and error correction method that a kind of hardware combines with software.This method is based on following specific memory structure: have at least two information recording devices (as: 2 stored charges are with the electric capacity of characterization information state, 2 resistance with different resistance values characterization information state, 2 transistors that come the characterization information state with the threshold voltage difference or the like) in the storage unit; Each information recording device has the ability of storage n (n is natural number and n＞2) attitude information; These 2 information recording devices can carry out independently writing and read operation separately.Under this specific memory structure, use the wrong error correcting technique of prison of software and hardware combining of the present invention, can simplify the complexity of Software correction part greatly, while is with respect to two error-detecting of classic method, application of the present invention will realize whole error-detecting, thereby improve the reliability of circuit operate as normal.
Description
Technical field
The invention belongs to the semiconductor memory technologies field, be specifically related to a kind of semiconductor memory fault monitoring and error correction method, relate in particular to a kind of based on particular memory structure and particular memory state fault monitoring and error correction method definition, software and hardware combining.
Background technology
For the various mechanism of makeing mistakes possible in the semiconductor memory, up to the present existing a lot of research.The various mistakes that occur in the semiconductor memory, can roughly be divided into two classes: the first kind is called " hard error ", mainly damages institute by various defectives or nonvolatil device physics and causes; Second class is called " soft error ", and they are mainly caused by α particle, ion doping or temporary radiation interference etc.These mistakes will seriously influence the reliability of storer operate as normal.Concerning the commercial production of reality, the integrity problem that various mistakes cause will have influence on the yield of product, be that satisfactory number of chips that can make on the same wafer, final will be limited by various interference and wrong and can not get guaranteeing, cause the decline of yield rate and the rising of cost at last.
For these problems, the way that people mainly take has 2 kinds: and static redundancy (Static Redundancy) and error recovery code method (Error Correction Codes, ECC).The former is applicable to the very little situation of the average error probability of storage unit of storer.And, reach the semiconductor memory of dynamic RAM more than the megabyte etc. as storage density for high density, and the various wrong mechanism that produce, its influence will aggravate.At this moment, the cell-average error probability raises greatly, adopts the required circuit of redundancy approach will be difficult to stand.Therefore, require the occasion of high reliability again in high-density applications, people generally adopt the method for error-correcting code (ECC).
The essence of ECC method is information redundancy.Concretely, be to realize the check code that error recovery adds, its characteristics are that it can transmit than the required information more information of storage it self.
In the storer, apply error-correcting code and carry out the method for error checking and correction and have a lot.Wherein the simplest, the most frequently used method is the parity checking method.Promptly be generally 2 system canned data A for one group
1～A
n, add several extra A
N+1A
mThe position, thus constitute A
1A
2... A
m, and A
N+1... A
mEach numerical value (0 or 1) will make A
1A
2... A
mIn, the number of " 1 " is an even number.Like this, in storage subsequently, in case a certain position A in the memory contents
xNumerical value be subjected to certain influence and make mistakes A
1A
2A
mIn the number of " 1 " will become odd number.Can judge canned data thus and have or not and make mistakes, and by certain algorithm (A that locates errors
x) the position, and then finish wrong correction.
The method of this error-correcting code (ECC), abominable or require the higher occasion of reliability for the residing environmental baseline of storer, use very extensive.But it has some shortcomings.
At first, realize that this method need add a lot of extra circuit, this is unfavorable to improving storage density undoubtedly.
Secondly, error-correcting code can not be corrected all mistakes.Such as top example, at single error correcting.For this error correction, if make mistakes when information of same more than 2 or 2 is arranged in the memory contents, then these mistakes will can not discovered (although these wrong single relatively mistakes of possibility that take place are much smaller).
Once more, the figure place of under the method for error-correcting code, may make mistakes (and wanting error correction) is many more, and the extra check code figure place of the required adding of this method also can be many more, and chip occupying area is big more, and the algorithm of error correction simultaneously is also complicated more.
At last, for polymorphic memory storing, the information that same one group of figure place is identical (be n system but not 2 systems this moment, and n is the state number of polymorphic storage), be converted to that the figure place of information will increase greatly after the 2 system arrays, cause also at double the increase of check bit that needs add.If be not converted to 2 system data but directly handle, parity checking is no doubt no longer suitable, just and additive method both can operate in theory, but because per 1 information state is too many, the complexity of supervising wrong error correction algorithm will sharply rise, and be difficult to stand.
Therefore, use error-correcting code (to be generally parity check code, in the time of ECC), in general, for the consideration of reliability, to improve yield rate, reduce cost often but not place hope on by parity checking.Present normally used ECC generally is the double two error-detecting of single error correcting.If guarantee higher reliability to two mistakes in addition more the mistake of multidigit detect and correct, adopt the circuit and the algorithm complex of ECC method to increase greatly.
For present employed storer, be semiconductor memory substantially, it has 3 kinds of basic developing direction: high density, high speed and non-volatile.
The representative of high density storage is dynamic RAM (DRAM), but it is subject to the interference of soft error and makes electric capacity not do too for a short time when size is dwindled, and generally will keep about 25fF.This makes it difficult when size is dwindled.
The representative of high speed storing is static RAM (SRAM), and its storage unit is made of 6 transistors, and area is very big, reaches 50～80F
2(F is a characteristic dimension), leakage problem is very outstanding simultaneously, causes power consumption high.
The main representative of non-volatile storage is flash memory (Flash), and its uses floating boom to come stored charge, and then the difference of the threshold voltage that how much reflects according to the electron amount on the floating boom, comes canned data thus.But since flash memory write and erase mechanism relies on specific physical mechanism, a lot of key parameters, as write voltage and be difficult to reduce still are in the level of 12V at present.Simultaneously, for the consideration of reliability, there is lower limit in the attenuate of the insulation course between floating boom and the channel region, and roughly at 7～8nm, therefore, people estimate that flash memory will be difficult to continue to make below 45nm.
Deficiency at above-mentioned 3 big class storeies, people wish to find a kind of high storage density, low-power consumption, the electricity operation, can directly write, the realization of High Speed state exchange, highly stable and and existing " complementation-metal-oxide layer-semiconductor (Complementary Metal Oxide Semiconductor, CMOS) " nonvolatile memory.
In this process, phase transition storage (Phase Change Memory, PCM) show one's talent, with its high density, simple in structure, directly can write, non-volatile, with existing CMOS technology highly compatible and can realize that characteristics such as polymorphic storage become one of candidate that is hopeful to replace present multiple storer and is used widely.Phase transition storage is based on phase-change material and can transforms mutually between crystalline state and amorphous state and cause that the characteristic of resistance difference produces.And because the difference of these different states is atomic arrangement mode difference, thereby the information of every kind of state can preserve after outage, and the storer that utilizes phase-change material to make will have non-volatile characteristic.These effects are mentioned in No. 3,530,441, No. 3,271,591, Ovshinsky (on September 6th, 1966) United States Patent (USP) and (on September 22nd, 1970) United States Patent (USP).Here the invention in these patents is collectively referred to as " Ovshinsky patent ".
As said in " Ovshinsky patent ", writing under the excitation of adding, phase-change material can be changed between two kinds of structure/states.Under a kind of state, material has very strong decrystallized tendency, and the atomic arrangement order is very poor, the resistivity height; Under the another kind of state, material has stronger crystallization tendency, and atomic arrangement is comparatively orderly, and resistivity is low.
Phase-change material not only can be changed between amorphous state and polycrystalline attitude, can also be in different, obviously differentiated, various states between complete amorphous state and complete crystalline state each other under the pulse in suitable writing, and the resistance of these intermediateness correspondences will be between complete amorphous resistance and complete polycrystalline resistance.This just means and utilizes phase-change material can produce the nonvolatile memory of many-valued storage.
In phase transformation, phase-change material is referred to as " set pulse " (SET pulse) by the single signal pulse that the high resistant amorphous state is converted into low-resistance polycrystalline attitude; Phase-change material is converted into the amorphous single signal pulse of high resistant by low-resistance polycrystalline attitude is referred to as " reset pulse (RESET pulse) ".
Because phase-change material essence when phase transformation takes place is the atomic arrangement and the crystalline network of material variation has taken place, thereby external interference has good stability relatively.Can directly write (need not to wipe) owing to phase-change material simultaneously, thereby all be better than flash memory (Flash) in above-mentioned several respects.While phase transition storage and CMOS technology highly compatible (can in the CMOS backend process, make), and simple in structure, area is little, helps obtaining very high storage density.
Except above characteristics, phase transition storage also has a most important characteristic: the volume that dwindles phase-change material will effectively shorten crystallization time, reduce the required electric current of writing simultaneously.The former has improved the access speed of phase transition storage, and the latter has then reduced power consumption.Therefore, phase transition storage has become the focus that people pay close attention to.
In brief, do not have a kind of existing solid-state memory system at present, have the so many advantage that phase transition storage has: low-cost, be easy to make, with existing C MOS technology highly compatible, can directly write, antijamming capability is strong, single memory cell can be realized many-valued storage and can realize high storage density.Undoubtedly, phase transition storage is expected to become the main flow of following nonvolatile memory to be selected, in addition become integrate at a high speed, high density and non-volatile " big unification " storer.
In the present existing phase transition storage design proposal, (storage unit only is 1 phase change resistor to mainly contain 0T1R, as shown in Figure 1), (storage unit is 1 transistor and 1 phase change resistor to 1T1R, as shown in Figure 2), (storage unit is 2 transistors and 2 phase change resistors to 2T2R, storage unit as shown in Figure 3).These cellular constructions are all stored based on binary states (being scale-of-two: " 0 ", " 1 ") at present.
Yet before phase transition storage was used widely, it was to be solved to still have some problems to have:
The first, the distribution problem of the amorphous state of material and polycrystalline attitude resistance.Attempt by dwindling phase-change material itself at phase transition storage with when reaching raising phase transformation speed and reducing power consumption, reduce that size brings do not match and technological fluctuation etc. will make phase change resistor value on the same chip produce very big difference (to see people such as W.Y.Cho " A 0.18 μ m 3.0V64Mb Non-Volatile Phase-Transition Random-Access Memory (PRAM) ", Dig.of Tech.PapersISSCC, page (s): 40-512 Vol.1,2004).This will reduce the antijamming capability of storer greatly.Along with reducing of characteristic dimension, resistance distribute and will disperse more (see people such as Y.N.Hwang, " Writing current reduction for high-densityphase change PRAM ", IEDM Tech.Dig, pp.893-896,2003).Finally, in case overlapping appears in the Standard resistance range of resistance, so theoretically, the storage array on the entire chip can't use unified extraneous reference source to offer the output terminal sense amplifier and use, and the differentiation of signal will become a serious problem.
The second, the retention performance that the resistance of material is passed in time.Bibliographical information is arranged at present, As time goes on certain drift can take place in the resistance of phase-change material, simultaneously because various application scenario, external environment also can impact resistance the interference of material, thereby to improve retention performance on the phase transition storage one side material as far as possible, to consider the influence that material drifts about with designing in the structure of circuit on the other hand.
For present existing 0T1R, 1T1R and 2T2R unit, two problems all exist for 1D1R and 1T1R unit, and along with the dwindling of characteristic dimension, especially these 2 problems can integrity problem occur all the more easily because of the aggravation of technological fluctuation and interference.
Opposite is, the 2T2R unit by the complementary signal of inside, unit comparison and sense amplifier to the inhibition of common-mode signal and successful solution these 2 problems.The 2T2R unit is that complementary storage 1bit information is on 2 phase change resistors at present.Because these 2 phase change resistors tighten the neighbour in the position, be subjected to extraneous identical interference, have and be close to identical technological fluctuation and resistance drift, therefore when the signal differential output of two bit lines, various interference finally can not produce any influence to output result (being store status), have guaranteed the reliability of memory circuit thus.The problem of 2T2R unit is: the unit complexity, storage density is lower.
Except phase transition storage, also has controlled (equivalent resistance) many-valued ability of writing based on the MFIS in the ferroelectric memory (Metal-Ferroelectricmaterial-Insulator-Semiconductor, i.e. " metal-ferroelectric material-insulation course-semiconductor " structure).The transistor of MFIS structure, different because the degree of polarization of ferroelectric material is subjected to the change of extraneous control signal, thereby can obtain different threshold voltages.Externally can present different conducting resistance under certain condition.While, MFIS structure itself also can be used as the non-volatile resistor device owing to the ferroelectric material polarization characteristic is non-volatile.Thereby in the phase transition storage based on phase-change material, as long as change phase change resistor R into MFIS device, put into above-mentioned 2T2R circuit again on the principle as resistance, also can realize similarly storage and under small size, have certain anti-interference capability.
But because extraneous interference has uncertainty, therefore much requiring the occasion that reliability is high or interference is very big, only depending on 2C2S (is that 2 gating gauge tap devices (2C) and 2 information recording devices (2S) are arranged in the storage unit, 2T2R is a kind of special case of 2C2S, that is: switch control device uses transistor T, and information stores is used resistance R) difference output mode that similar structures provides, integrity problem still exists.For this problem, the error correcting code that people use traditionally (ECC) mode still is being extensive use of.Its various shortcomings impel people extensively to seek new easy and effective method, and prison mistake novel, software and hardware combining and error correction method arise at the historic moment thus among the present invention.
Summary of the invention
The objective of the invention is to propose a kind of traditional error correcting code (Error Correction Code, ECC) wrong error correction method of prisons method, storage data that be applicable to polymorphic storage, software and hardware combining of being different from.
Prison mistake, the error correction method of the software and hardware structure that the present invention proposes, on the circuit structure of physics, based on a kind of particular storage structure, and to various store statuss, employing is the area definition of guiding with ratio, and the number of boundary of setting according to peripheral circuit is between several region with this ratio spatial division then, wherein, comprising: " legal interval " and " illegal interval "; Whether last basis " ratio of certain physical quantity " falls into " legal interval " is judged whether this store status makes mistakes.
As previously mentioned, be applicable to prison mistake, the error correction method of this software and hardware combining, storage unit should have following characteristic:
Have at least two information recording devices (as: 2 stored charges are with electric capacity or 2 resistance with different resistance values characterization information state of characterization information state, or 2 transistors that come the characterization information state with the threshold voltage difference or the like) in 1 storage unit.
2 each information recording device have the ability of storage n (n is natural number and n＞2) attitude information.
3 these 2 information recording devices can carry out independently writing and read operation separately.
At present, meet that the storage unit of above-mentioned requirements is most typical to be foregoing 2C2S structure, its representative in phase transition storage is the 2T2R structure, and (this structure is at the article " Full integration and ReliabilityEvaluation of Phase-change RAM Based on 0.24um-CMOS technologies " of Y.N.Hwang etc., Symposium on VLSITech Digest of Tech papers, had mentioned in 2003) or to adopt the 2T2MFIS structure (be in the phase change memory structure of 2T2R, phase change resistor R is replaced by " metal-ferroelectric material-insulation course-semiconductor " structure) ferroelectric memory, or even the 2T2C structure (is in the phase change memory structure of 2T2R, phase change resistor R is replaced by capacitor C, how much realizes polymorphic storage according to the electric charge on the capacitor C) dynamic RAM or the like.
Therefore, the inventive method is on the circuit structure of physics, based on a kind of particular storage structure: have at least 2 information recording devices and at least 2 gating switches in this storage unit; At least 2 information recording devices in the unit have the ability of storage n (n is natural number and n＞2) attitude information, and these 2 information recording devices can independently be write and read operation under the control of corresponding gating switch.
In the definition of store status, based on a kind of with ratio be the guiding the state define method.That is: the size of ratio is definition or distinguishes unique foundation of various different storage states, and the ratio here (as resistance, electric charge, electric current, voltage etc.) is meant the ratio of " certain physical quantity " 2 information recording devices in the storage unit, that be used to store various states.These 2 information recording devices have the ability of storage n (n is natural number and n＞2) attitude information, have many-valued ability of writing and this ability derives from these 2 information recording devices (foregoing) " certain physical quantity ".For example, the information recording device in the phase transition storage---phase change resistor has the ability of polymorphic storage, is because phase change resistor is used to store " certain physical quantity "---the resistance of various states, has the many-valued ability of writing.
Based on the circuit structure of aforesaid store status definition and physics, when storage unit realized polymorphic storage, the numerical values recited scope that the ratio of " certain physical quantity " of 2 information recording devices has in the unit was called " ratio range ".This " ratio range " is one dimension, so be called " one dimension ratio space ".
For above-mentioned " one dimension ratio space ", mark off each interval again, its boundary line each other is some predefined " number of boundary ".These " number of boundary " are set by the physical parameter of some transistors (as metal-insulator grid-semiconductor field effect transistor) in the Peripheral storage circuit (as peripheral sense amplifier) (as the ratio of the breadth length ratio of different crystal pipe).The redesign of these physical parameters in the peripheral circuit, with " number of boundary " of these settings again, with the concrete size matching in " one dimension ratio space ".
In " one dimension ratio space ", marking mutual each other non-conterminous some section definitions is legal interval, represents different effective store statuss separately.The quantity in legal interval is the polymorphic number n (n＞2) when the storage unit realization is polymorphic stores.And between other remaining area, be distributed in each legal interval both sides, and they are defined as illegal interval---whether " forbidden zone " is specifically designed to the monitoring canned data and makes mistakes.Like this, each legal interval both sides is " forbidden zone " of catching illegal state.
Because the information recording device in the storage unit possesses polymorphic ability of writing, especially to " metal-ferroelectric material-insulation course-semiconductor " structure in phase change resistor in the phase transition storage and the ferroelectric memory, their " certain physical quantity "---the dynamic change scope of resistance characteristic has 10
3The above order of magnitude (being that maximum resistance is more than 1000 times of minimum resistance), therefore the broadness of " ratio range " makes that " the ratio width " of " forbidden zone " is very big, promptly " forbidden zone " is very wide.Simultaneously, because the state definition is guiding with ratio, and it is adjacent on interior 2 the information recording device positions of storage unit, therefore approximately uniform drift change takes place in " certain physical quantity " of 2 information recording devices when being interfered, so it is minimum that its " ratio of certain physical quantity " changes, for its absolute value, " ratio " stable much better.
" ratio of certain physical quantity " of 2 information recording devices is relatively stable in the storage unit, and broad " forbidden zone ", make under various interference: " ratio of certain physical quantity " of 2 information recording devices is with unable go beyond any one " forbidden zone ".At this moment, output by peripheral sense amplifier is compared, in case finding " ratio of certain physical quantity " (as resistance ratio etc.) falls among a certain " forbidden zone ", mean that then canned data makes a mistake, also mean simultaneously: the unit that information is made mistakes, its correct content only may be one of legal interval 2 states representing respectively of 2 of this " forbidden zone " both sides, be just " 2 select 1 " that ensuing Software correction will be done, and " n selects 1 " in the non-traditional error correction (n is the state number of polymorphic storage).Like this, follow-up error correction work will be simplified greatly, and promptly peripheral circuit will obtain simplifying, and the storage density of storer will be promoted, and its access speed also will obtain to improve.At last, owing to whether each unit only makes mistakes this unit of need inspection self need not to involve other unit, therefore, can write all simultaneously or sensing element is monitored, " all the writing/read the fault monitoring of position " of realizing thus be under traditional error correction " two fault monitoring " can not compare.
In sum, core content of the present invention is: for the storage unit that satisfies particular requirement, under the state definition that with ratio is guiding, in storage unit in " the one dimension ratio space " that ratio constituted of " certain physical quantity " of 2 information recording devices, marking some section definitions not adjacent to each other is legal interval, represents different store statuss separately.The quantity in legal interval is the polymorphic number n (n＞2) when the realization individual unit is polymorphic to be stored.And between other remaining area, distribute and each legal interval both sides, they are defined as illegal interval---whether " forbidden zone " is specifically designed to the monitoring canned data and makes mistakes.Like this, each legal interval both sides is " forbidden zone " of illegal state correspondence.
Thus, the wrong error correction method of the prison of software and hardware combining can realize classic method institute can not " all writing/read the fault monitoring of position ", can simplify polymorphic (n attitude, n＞2) storage complexity of error correction work down simultaneously greatly, change " n selects 1 " is " 2 select 1 ".In addition, because the wrong work of prison is only relevant with the unit of being monitored, and error correction at any time all only needs " 2 select 1 ", thereby the wrong error correction method of the prison of this software and hardware combining, its circuit complexity can not increase with the number of error unit and sharply increase, and this also is that classic method can not be by comparison.
Compare classic method, the wrong error correction method of the prison of software and hardware combining of the present invention when guaranteeing reliability, has been simplified the error correction workload, has strengthened the wrong ability of prison, helps improving storage density and access speed.
Brief description is carried out in the concrete operations that state area is divided below, is described in detail and sees " specific implementation ".Many-valued write method about information recording device, the existing report of pertinent literature, article " Multiple Programming Method and Circuitry for a Phase Change Nonvolatile Random AccessMemory (PRAM) " (IEICE Trans.Electron as people such as M.TAKATA, VOL.E87-C, No.10,2004) point out: phase change resistor is written as multiple state corresponding to different resistances, the different pulse of quantity gets final product by it is applied same waveform.For many-valued the writing of " metal-ferroelectric material-insulation course-semiconductor " in the ferroelectric memory, making uses the same method gets final product.This very helps the simplification of physical circuit operation undoubtedly.
The differentiation of each state then realizes by the relative size that compares (2 information recording devices in the unit) " ratio of certain physical quantity " and (being determined by peripheral circuit) " number of boundary ".
When being illegal state pairing " forbidden zone " in the both sides in each pairing legal interval of effective status, the differentiation of realization state needs the relative size of comparison (2 information recording devices in the unit) " ratio of certain physical quantity " and two " number of boundary " of some forbidden zones.Therefore, if store status is made mistakes, when promptly " ratio of certain physical quantity " fell into " forbidden zone " adjacent with former legal interval, this ratio certainly led to different comparative results with 2 number of boundary of a certain " forbidden zone " when comparing.On the contrary, if store status do not make mistakes, represent that " ratio of certain physical quantity " of this store status falls into legal interval, the comparative result of this ratio and 2 number of boundary of a certain " forbidden zone " is all with consistent.According to this characteristics, can judge concrete " forbidden zone " position that whether memory contents makes mistakes and (if makeing mistakes) ratio falls into.Thus, follow-up Software correction work can begin.More than these are exactly concrete method of operating, in " specific implementation ", will use circuit to realize.
Description of drawings
Being stored as example with 8 attitudes in the realization of the phase transition storage under the 2T2R structure unit below describes.2 information recording devices in the 2T2R unit are phase change resistor, and they can be written as 4 kinds of different states separately, corresponding 4 kinds of different resistance ranges.
Fig. 1 is the storage array of 0T1R.
Fig. 2 is the storage organization synoptic diagram of 1T1R.
Fig. 3 is the storage organization synoptic diagram of 2T2R.
Fig. 4 is in the storage array of phase transition storage, (this figure draws from W.Y.Cho et al. " A 0.18 μ m 3.0V 64Mb Non-Volatile Phase-TransitionRandom-Access Memory (PRAM) " in the distribution of phase change resistor resistance under initial state, polycrystalline attitude and amorphous three state, Dig.ofTech.Papers ISSCC, page (s): 40-512 Vol.1,2004)
Fig. 4 is 4 attitude distribution of resistance synoptic diagram of phase change resistor in the unit.
Fig. 5 is the distribution plan of ratio in " one dimension ratio space " of two phase change resistor resistance value ratios in the storage unit.
Fig. 6 is the comparator circuit read and the prison mistake and the error correction circuit of software and hardware combining.
Fig. 7 is the situation that resistance R adopts ferroelectric MFIS structure in the 2T2R unit.
Number in the figure: the 1st, bit line, the 2nd, word line, the 3rd, phase change resistor, the 4th, the output terminal sense amplifier, 5 for being used for the reference source that state is distinguished, the 6th, output terminal, 7 is the gating switch pipe in the unit, 8 are the driving source of read/write operation, and the resistance distribution range of 4 kinds of states of 9,10,11 and 12 expressions is designated as R successively
1, R
2, R
3And R
413 is the low resistance of complete polycrystalline attitude, 14 is the complete amorphous high value, 8 kinds of store statuss of 15～22 expressions, 23～36 represent the border of 15-228 kind store status respectively, 37 driving source power supplys when the read operation, and 38 is the output current driver module, 39 and 40 are respectively the electric current of the phase change resistor that is connected odd number bit line and even number bit line of flowing through, 41 and 42 is the electric current that produces again through the current drives module, and 43 is comparative result, and 44 are the output sense amplifier, 45 is output combinational logic and driver module, 46 is comparator module, and 47 is the Software correction module, and 48 is error flag, 49 is the positional information of wrong ratio forbidden zone of living in, and 50 is the MFIS structure.
Embodiment
In the greatest problem of people for the solution phase transition storage---when excessive operating current reduces characteristic dimension, between high storage density and the high-reliability storage contradiction has taken place, and this contradiction intensifies gradually along with reducing of characteristic dimension.These were described in detail in " background technology " lining, no longer repeated here.
Under the small size, contradiction between high storage density and the high-reliability storage, can realize the requirement of high-reliability storage by the 2C2S similar structures described in " background technology ", high storage density then depends on realizes that under similar 2C2S structure polymorphic storage realizes in the unit.
Be example with the 2C2S structure in the phase transition storage (being the 2T2R structure) below, at adopting with ratio is the state define method of guiding, when realizing polymorphic storage, the wrong error correction method of prison of the present invention, novel, that software and hardware combines is carried out further concrete the introduction in the unit.Here, the storage unit of each 2T2R realizes the storage of 8 attitudes, and 2 information recording device elements are phase change resistor; Each phase change resistor in each 2T2R unit has 4 attitudes, corresponding 4 kinds of Standard resistance ranges.
Fig. 1 is the storage organization synoptic diagram of 0T1R.The 1st, bit line, the 2nd, word line, the 3rd, phase change resistor
Fig. 2 is the storage organization synoptic diagram of 1T1R.1～3 implication is identical with Fig. 1, and the 4th, the output terminal sense amplifier, 5 for being used for the reference source that state is distinguished, the 6th, output terminal.For phase transition storage, 1T1R is simple in structure, the storage density height.When reading, at first need selected cell is applied specific incentives; Then, response and the specific reference source of exporting compared, realize traditional 2 attitudes storage differentiation of state down thus.
Fig. 3 is the storage organization synoptic diagram of 2T2R.Wherein, 1A, 1B, 2,3,4,6 are respectively odd number bit line, even number bit line, word line, phase change resistor, output terminal sense amplifier and output terminal; 7 is the gating switch pipe in the unit, and 8 are the driving source of read/write operation, provide 3 kinds of pulse signals: read pulse, reset pulse and set pulse.For phase transition storage, gating gauge tap device 7 uses the MOS field effect transistor usually, and the information recording device in the unit is 2 phase change resistors 3.Owing to be close on 2 phase change resistor positions in the 2T2R unit, be subjected to being close to identical interference constantly, change much at one takes place, therefore will respond accordingly when exporting sense amplifier at 2 bit lines, the mechanism that difference is exported will be got rid of the influence of interference fully.This makes the 2T2R unit have high antijamming capability, thereby has realized high-reliability storage.
Fig. 4 is that individual unit is realized 8 attitudes when storage, to the requirement of phase change resistor: have the ability that is written as 4 kinds of states, and every kind of resistance distribution range that state is corresponding different, promptly as shown in Figure 49,10,11 and 12.Hereinafter with in the table 19,10,11 and 12 be designated as R respectively
1, R
2, R
3And R
4These distribution ranges with regard to its resistance, are between the low resistance 13 and complete amorphous high value 14 of complete polycrystalline attitude.
For 8 kinds of states (15～22) that are used to characterize canned data, its each self-corresponding ratio range distribution in the resistance ratio space of one dimension, as shown in Figure 5.Because phase change resistor (as Fig. 4) has 4 kinds of different conditions, corresponding 4 kinds of Standard resistance range R
1～R
4, so the ratio of 2 phase change resistors in each unit, its molecule and denominator can be at R
1～R
4In choose arbitrarily, have 16 kinds of possible situations.In these possible situations, 8 kinds of canned data states 15～22 as shown in Figure 5, the situation of its resistance ratio is respectively: R
1/ R
4, R
2/ R
4, R
1/ R
3, R
1/ R
2, R
2/ R
1, R
3/ R
1, R
4/ R
2, R
4/ R
1, be taken as effective status here, characterize 8 kinds of store statuss respectively, corresponding 8 legal intervals are shown in shade among Fig. 5.The size in these legal intervals is stipulated by predefined interval border several 23～36.Hereinafter with table 1 in, number of boundary 23～36 is designated as respectively: 1/g, 1/f, 1/e, 1/d, 1/c, 1/b, 1/a, a, b, c, d, e, f, g.And the value size of these number of boundary self is then set by some special parameters of special transistor in the peripheral sense amplifier.
Truth table is compared in the output of various states during the storage of table 18 attitude
Truth table was compared in the output of various states when table 1 was the storage of 8 attitudes, had wherein listed corresponding to the comparative result of the output sense amplifier under every kind of state and the output state of every kind of store status correspondence.A
xThe current ratio that carry out for peripheral sense amplifier (x=0～13), in fact reflected resistance than with the specific border number relatively.Number of boundary is decided by transistorized parameter in the peripheral sense amplifier of setting, as a in the table 1, b, c, d, e, f, g etc." ratio of certain physical quantity " by 2 information recording devices in the comparison selected cell (is the identical current ratio of reading under the voltage in the table 1, in fact be reflected as the situation of resistance ratio) with the relation of each number of boundary, and then which legal interval " ratio of certain physical quantity " of 2 information recording devices is within the determining unit, realizes determining of store status thus.
(in 8 attitudes a kind) corresponding interval all is legal interval because any effective status, and its ratio can not be in " forbidden zone ": among [1/g, 1/f], [1/e, 1/d], [1/c, 1/b], [1/a, a], [b, c], [d, e], [f, the g], thereby A under the normal condition
0And A
1, A
2And A
3, A
4And A
5, A
6And A
7, A
8And A
9, A
10And A
11, A
12And A
13Output for any effective status all should be mutually the same; Otherwise, if canned data is subjected to external interference and makes mistakes, then ratio must fall among " forbidden zone " adjacent with former legal interval, and promptly ratio must drop on interval [1/g, 1/g], [1/e, 1/d], [1/c, 1/b], [1/a, a], [b, c], [d, e], in one of [f, g] ([1/g, g] is possible maximum interval of phase change resistor ratio here).At this moment, compare with 2 number of boundary in both sides of ratio " forbidden zone " of living in and this ratio, its result is inevitable different, thereby A
0And A
1, A
2And A
3, A
4And A
5, A
6And A
7, A
8And A
9, A
10And A
11, A
12And A
13This moment can not be all mutually the same.According to this characteristics, can produce corresponding circuit, and when makeing mistakes, produce corresponding signal, tell follow-up Software correction circuit with 2 legal intervals (being possible former correct status) adjacent, " forbidden zone " position that ratio falls into it.
Fig. 6 is the wrong error correction circuit of the prison of the comparator circuit read and software and hardware combining.Wherein, 1A, 1B, 2,3,6,7,8 are respectively odd number bit line, even number bit line, word line, phase change resistor, output terminal, gating switch pipe, read-write driving source circuit.37 driving source electric currents when the read operation, 39 and 40 are respectively the electric current of the phase change resistor that is connected odd number bit line and even number bit line of flowing through.When read operation, adopt under the identical voltage drive electric current difference relatively and then judge the way of resistance ratio, therefore 1A and the 1B equipotential of this moment, electric current 39 and 40 size and phase change resistor resistance are inversely proportional to.The 38th, the output current driver module, it produces the electric current 41 and 42 identical with 39 and 40 again according to the size of identical voltage drive lower unit shunting, and it is sent in the follow-up output sense amplifier 44.Output sense amplifier 44 is different from common sense amplifier 4, and it is responsible for realizing the comparison of current ratio (being the inverse ratio of resistance ratio in the unit) and each number of boundary.Comparative result is 43, i.e. A in the table 1
0～A
13Output combinational logic and driver module 45 and comparator module 46 are sent in the output of comparative result 43 simultaneously.Module 45 is according to A
0～A
13The result send 32 system numbers according to the relation of table 1, thereby reach the output of 8 attitudes storages.46 comparisons of comparator module A
0And A
1, A
2And A
3, A
4And A
5, A
6And A
7, A
8And A
9, A
10And A
11, A
12And A
13Whether mutually the same, and then determine whether wrong generation.48 is the error flag position, if make mistakes, the signal of zone bit 48 prevents that with closing module 45 wrong information is read out, and activates follow-up Software correction module 47 simultaneously.47 when being activated by 48 error signal, will receive simultaneously comparator module 46 that send here, according to ratio residing " forbidden zone " positional information 49 relatively that determine, mistake of having carried out.Software correction module 47 is judged " forbidden zone " shown in the immediate vicinity information 49 two possible former normal conditions, to determine original correct status according to the situation of positional information 49.Writing again with control circuit subsequently omitted here.
Here need to prove, output sense amplifier 44, necessary state area timesharing when realizing normal output, also comparator module 46 is needed just for its comparative result.And comparator module 46 is the circuit of realizing all stored data bit fault monitorings among the present invention.This shows that output sense amplifier 44 had both been realized normal output function, served fault monitoring circuit of the present invention again simultaneously, this makes circuit (the comparing traditional E CC method) complexity that will additionally apply when realizing fault monitoring reduce greatly.
Simultaneously, comparator module 46 is through comparing, make mistakes if find, the information of then sending into follow-up ECC circuit part correction module 47 also not only is an error flag position 48, also provide " candidate " of possible 2 former correct status, 2 the legal interval corresponding states in the both sides of the forbidden zone that ratio falls into of promptly reading.This makes 47 need of follow-up module judge in 2 possibilities " candidate " that positional information 49 provides, and needn't go for from 8 kinds of states altogether, has reduced the complexity of workload and circuit undoubtedly.And this change " n (n is the state number of polymorphic storage) selects 1 " is that " 2 select 1 " is suitable equally for storage more polymorphic in the unit.This means: the error correction that the fault monitoring circuit has has been shared a part of error correction task, makes follow-up error correction circuit only carry out the work of " 2 select 1 " all the time, and algorithm and circuit structure help simplifying the operation.
Fig. 7 is the structure that R adopts " metal-ferroelectric material-insulation course-semiconductor (MFIS) " structure in the 2T2R unit, and principle is identical with the employing phase change resistor, no longer repeats here.Among the figure, 1A, 1B, 2A, 2B, 4,6,7,8 are respectively word line, the control of odd number bit line, even number bit line, control gating switch pipe the MFIS structure are carried out the many-valued word line of writing, peripheral sense amplifier, output terminal, gating switch pipe and read-write driving source circuit.50 is the MFIS structure, and resistance can present different resistance states under the effect of 2B, thereby reaches the effect same with phase change resistor R.
In sum, compare traditional error-correcting code (ECC is generally parity check code) method, of the present invention, soft or hard That part combines, with the closely-related fault monitoring of multiple-state storage and error correction method and unit in multiple-state storage good compatibility is arranged The property. When the wrong error correction of prison of carrying out the storage data, fall although inevitably increased the complexity of whole memory circuit Low storage density, but carried out covert compensation by multiple-state storage in the unit. Simultaneously, the fault monitoring circuit fills on the one hand Divide and utilized the required circuit of normal output (sense amplifier array etc.), born on the one hand a part of error correction task. This makes Follow-up error correction work is simplified greatly, rest on all the time the degree of " 2 select 1 ", and do not have with the state number of multiple-state storage Close. And because unit and state definition itself, whether every storage data make mistakes when judging and other unit Irrelevant, thereby realized the fault monitoring of total data position, these all are that conventional method is beyond power.
Claims (1)
1, the wrong error correction method of a kind of prison of software and hardware combining, it is characterized in that on the circuit structure of physics, based on a kind of particular storage structure, and to various store statuss, employing is the area definition of guiding with ratio, and the number of boundary of setting according to peripheral circuit is between several region with this ratio spatial division then, wherein, comprising: " legal interval " and " illegal interval "; Whether last basis " ratio of certain physical quantity " falls into " legal interval " is judged whether this store status makes mistakes; Wherein:
Described particular memory location structure is: have at least 2 information recording devices and at least 2 gating switches in this storage unit; At least 2 information recording devices in the unit have the ability of storing n attitude information, and n is natural number and n＞2, and these 2 information recording devices can independently be write and read operation under the control of corresponding gating switch;
Described is the area definition of guiding with ratio: the size of ratio is definition or distinguishes unique foundation of various different storage states, and the ratio here is meant the ratio of " certain physical quantity " 2 information recording devices in the storage unit, that be used to store various states; The numerical values recited scope that claims this ratio to have is one dimension ratio space;
Described number of boundary is set by the ratio of some the transistorized length breadth ratios in the Peripheral storage circuit; According to the number of boundary of setting, in one dimension ratio space, be legal interval with the mutual each other non-conterminous some section definitions that mark, represent different effective store statuss separately; Whether remaining interval is distributed in each legal interval both sides, is defined as illegal interval, be specifically designed to the monitoring canned data and make mistakes;
Described certain physical quantity is meant a kind of of resistance, electric charge, electric current, voltage.
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