CN110415744B - Nonvolatile memory based on ferroelectric transistors - Google Patents
Nonvolatile memory based on ferroelectric transistors Download PDFInfo
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- CN110415744B CN110415744B CN201910626112.0A CN201910626112A CN110415744B CN 110415744 B CN110415744 B CN 110415744B CN 201910626112 A CN201910626112 A CN 201910626112A CN 110415744 B CN110415744 B CN 110415744B
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Abstract
本发明公开了一类基于铁电晶体管的非易失存储器，包括基于铁电晶体管设计的非易失存储器的单元电路和阵列电路，其单元电路结构包括两个晶体管或三个晶体管，多个单元之间通过电气连接的方式可组合成若干行若干列的阵列布局方式。本发明利用铁电晶体管漏源电流‑栅极电压的滞回特性，完成对存储器的高效率读写操作。
The invention discloses a type of non-volatile memory based on ferroelectric transistors, including a unit circuit and an array circuit of the non-volatile memory designed based on ferroelectric transistors. The unit circuit structure includes two transistors or three transistors, a plurality of units The electrical connection between them can be combined into an array layout with several rows and several columns. The invention utilizes the hysteresis characteristic of the drain-source current-gate voltage of the ferroelectric transistor to complete the high-efficiency read-write operation of the memory.
Description
Technical Field
The invention relates to the technical field of low-power-consumption nonvolatile memory structure design, in particular to a nonvolatile memory based on a ferroelectric transistor.
Background
In recent times, with the increasing expansion of information volume, people put higher demands on the nonvolatile performance of memories in order to prevent the loss of stored information. Many memories, such as DRAM (dynamic random access memory), lose information stored on the memory due to a reduction in power to the circuit device when no external power is applied for an extended period of time. Random access NVM (nonvolatile memory) can effectively solve the above problems. The current nonvolatile memories include PCRAM, ReRAM, FeRAM, STT-MRAM, etc., but these memories have more defects in terms of energy and time delay consumed by data access, process compatibility, device durability, circuit design complexity, etc.
Currently, fefets (ferroelectric transistors) based on new materials and manufacturing processes enable designed memories to have good process compatibility and low power consumption characteristics, and have good endurance and moderate operating voltage, for example, recent test results published in the industry indicate that the bias voltage for fefets read/write operations can be reduced to within 1.5V. These characteristics show that the ferroelectric transistor has great application potential in the fields of array design, distributed data storage (distributed data storage), and neural network computing (neural computing). Furthermore, a Nonvolatile memory array with two transistors in each circuit unit is designed in Nonvolatile memory design based on ferroelectric FETs, so that higher energy efficiency is realized; however, this design has a high read/write voltage and fails to fully exploit the potential of high energy efficiency of ferroelectric transistors.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art.
Therefore, an object of the present invention is to provide a circuit unit designed based on a ferroelectric transistor, which makes full use of the drain-source current-gate voltage hysteresis characteristic of the ferroelectric transistor to design a novel circuit structure and operation mode, so as to achieve the purpose of a nonvolatile memory with lower power consumption.
Another object of the present invention is to provide a corresponding array circuit based on the circuit unit designed by the ferroelectric transistor.
In order to achieve the above object, an embodiment of a first aspect of the present invention provides a circuit unit designed based on a ferroelectric transistor, including: the memory comprises a first transistor, a second transistor, a bit line, a first word line and a second word line, wherein the grid electrode of the first transistor is connected with the first word line, the drain electrode of the first transistor is connected with the bit line, the source electrode of the first transistor is connected with the drain electrode of the second transistor, the grid electrode of the second transistor is connected with the second word line, the source electrode of the second transistor is grounded or biased at a preset potential, and at least one transistor in the first transistor and the second transistor is a ferroelectric transistor.
In order to achieve the above object, a second embodiment of the present invention provides an array circuit based on ferroelectric transistor design, including: at least one circuit unit as described in the above embodiment, and the units of the array circuit are combined into a layout of multiple rows and multiple columns by electrical connection, wherein the first word lines of the circuit units in the same row are connected, the second word lines of the circuit units in the same row are connected, and the bit lines of the circuit units in the same column are connected.
According to the circuit unit and the array circuit based on the ferroelectric transistor design, for the nonvolatile memory with each circuit unit provided with two transistors, the energy delay product of writing operation can be lower, so that the drain-source current-grid voltage hysteresis characteristic of the ferroelectric transistor is fully utilized, a novel circuit structure and an operation mode are designed, and the purpose of the nonvolatile memory with lower power consumption is achieved.
In addition, the array circuit based on the ferroelectric transistor design according to the above embodiment of the present invention may also have the following additional technical features:
further, in an embodiment of the present invention, when a read operation is performed on data stored in the circuit unit, a voltage of the second word line of the circuit unit turns on the second transistor of the circuit unit, so as to distinguish the data stored in the circuit unit according to a magnitude of a resistance value between drain and source of the first transistor of the circuit unit or an influence of the magnitude of the resistance value on a change of a voltage or a current on a bit line of the circuit unit.
Further, in an embodiment of the present invention, when writing data stored in the circuit unit, voltages of the bit line and the first word line are controlled to make polarization characteristics of the first transistor of the circuit unit consistent with the data to be stored.
Further, in an embodiment of the present invention, when writing data stored in the circuit unit, the bit line voltage is biased at a high level or a low level, the voltage of the first word line is restored to an original voltage after the low voltage and the high voltage respectively stay for a certain period of time, and the voltage of the second word line turns off the second transistor of the circuit unit.
In order to achieve the above object, a circuit unit designed based on a ferroelectric transistor is provided in an embodiment of the third aspect of the present invention, which includes: the memory comprises a first transistor, a second transistor, a third transistor, a first bit line, a second bit line, a first word line, a second word line and a third word line, wherein the grid electrode of the first transistor is connected with the first word line, the drain electrode of the first transistor is connected with the grid electrode of the second transistor, the source electrode of the first transistor is connected with the first bit line, the drain electrode of the second transistor is connected with the source electrode of the third transistor, the source electrode of the second transistor is connected with the second word line, the grid electrode of the third transistor is connected with the third word line, and the drain electrode of the third transistor is connected with the second bit line, wherein at least one of the first transistor, the second transistor and the third transistor is a ferroelectric transistor.
In addition, the circuit unit designed based on the ferroelectric transistor according to the above embodiment of the present invention may also have the following additional technical features:
further, in one embodiment of the present invention, the first bit line and the second bit line are merged into one bit line in a shorted form.
In order to achieve the above object, a fourth aspect of the present invention provides an array circuit based on a ferroelectric transistor design, including: at least one circuit unit as described in the above embodiment, and the units of the array circuit are electrically connected to form a layout in which the units are combined into a plurality of rows and columns, wherein the first word lines of the circuit units in the same row are connected, the second word lines of the circuit units in the same row are connected, the third word lines of the circuit units in the same row are connected, the first bit lines of the circuit units in the same column are connected, and the second bit lines of the circuit units in the same column are connected.
According to the circuit unit and the array circuit designed based on the ferroelectric transistor, disclosed by the embodiment of the invention, for the nonvolatile memory with three transistors in each circuit unit, the energy delay product of writing operation is effectively reduced, the normal state of other circuit units cannot be influenced by the writing operation of a certain circuit unit, and meanwhile, the circuit unit only needs the maintenance operation of single voltage, so that the drain-source current-grid voltage hysteresis characteristic of the ferroelectric transistor is fully utilized, a novel circuit structure and an operation mode are designed, and the purpose of the nonvolatile memory with lower power consumption is achieved.
In addition, the array circuit based on the ferroelectric transistor design according to the above embodiment of the present invention may also have the following additional technical features:
further, in an embodiment of the present invention, when a read operation is performed on the data stored in the circuit unit, the voltage of the third word line turns on the third transistor, so as to distinguish the data stored in the circuit unit according to the magnitude of the resistance value between the drain and the source of the second transistor or the influence thereof.
Further, in an embodiment of the present invention, when writing data stored in the circuit unit, voltages of the second word line and the first bit line are controlled to make polarization characteristics of the second transistor of the circuit unit consistent with the data to be stored.
Further, in an embodiment of the present invention, when writing data stored in the circuit unit, the first bit line voltage is biased at a high level or a low level, the first transistor is turned on by the voltage of the first word line, and the third transistor is turned off by the voltage of the third word line.
Further, in an embodiment of the present invention, when writing data stored in the circuit unit, the voltage of the second word line is restored to the original voltage after the low voltage and the high voltage respectively stay for a period of time.
Further, in one embodiment of the present invention, the first bit line and the second bit line are merged into one bit line in a shorted form.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a circuit symbol diagram of a ferroelectric transistor according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of one structure of a ferroelectric transistor according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating an exemplary drain-source conductance-gate-source voltage hysteresis characteristic of a ferroelectric transistor according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating the structure and read/write operation of a circuit unit comprising two transistors according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of an array circuit based on ferroelectric transistor design according to an embodiment of the present invention;
FIG. 6 is a diagram illustrating an array structure of a first memory according to an embodiment of the invention;
FIG. 7 is a diagram illustrating transient waveforms under different operations of a first memory according to an embodiment of the present invention;
FIG. 8 is a diagram illustrating the structure and read/write operations of a circuit unit including three transistors according to an embodiment of the present invention;
FIG. 9 is a diagram illustrating an array structure of a second memory according to an embodiment of the invention;
FIG. 10 is a diagram illustrating an array structure of a third memory according to an embodiment of the invention;
FIG. 11 is a graph showing the comparison of the write delay-average write energy, read delay-average read energy, and write delay-kinetic energy of different non-volatile memories based on ferroelectric transistor design according to an embodiment of the present invention;
FIG. 12 is a graph illustrating a comparison of performance metrics between different non-volatile memories based on ferroelectric transistor designs, in accordance with an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
The embodiment of the invention mainly relates to a nonvolatile memory based on ferroelectric transistors, which comprises a unit circuit and an array circuit of the nonvolatile memory designed based on the ferroelectric transistors, wherein the unit circuit structure comprises two transistors or three transistors, a plurality of units can be combined into a layout mode of a plurality of rows and a plurality of columns in an electrical connection mode.
A circuit cell and a memory based on a ferroelectric transistor design proposed according to an embodiment of the present invention will be described below with reference to the accompanying drawings, and first, a circuit cell based on a ferroelectric transistor design proposed according to an embodiment of the present invention will be described with reference to the accompanying drawings.
The circuit unit based on the ferroelectric transistor design comprises: the memory cell comprises a first transistor, a second transistor, a bit line, a first word line and a second word line.
The grid electrode of the first transistor is connected with a first word line, the drain electrode of the first transistor is connected with a bit line, the source electrode of the first transistor is connected with the drain electrode of the second transistor, the grid electrode of the second transistor is connected with a second word line, the source electrode of the second transistor is grounded or biased at a preset potential, and at least one of the first transistor and the second transistor is a ferroelectric transistor. The circuit unit of the embodiment of the invention can fully utilize the drain-source current-grid voltage hysteresis characteristic of the ferroelectric transistor, design a novel circuit structure and an operation mode, and achieve the aim of a nonvolatile memory with lower power consumption.
The preset potential may be understood as a source bias of the second transistor at a fixed potential, and a person skilled in the art may set the preset potential according to practical situations, and is not limited specifically herein.
It should be noted that the circuit symbol of the ferroelectric transistor is shown in fig. 1, a structure of the ferroelectric transistor is shown in fig. 2, and a typical case of the drain-source conductance-gate-source voltage hysteresis characteristic curve of the ferroelectric transistor is shown in fig. 3.
A circuit cell based on a ferroelectric transistor design will be further elucidated by means of a specific embodiment.
As shown in fig. 4, the ferroelectric transistor T2 has a gate connected to the word line WLW, a drain connected to the bit line BL, and a source connected to the drain of the transistor T1 for a nonvolatile memory having a two-transistor structure per circuit unit; the gate of transistor T1 is connected to word line WLR and the source is biased at a fixed potential of 0.
Without external energy injection, the bit line BL and both write word lines WLW, WLR are biased at 0 potential, at which time the gate-source voltage V of the ferroelectric transistorGSAt 0, the ferroelectric transistor operates within the hysteresis interval of the drain-source current-gate voltage hysteresis curve. When energy is injected, when the data of the memory cell is not read or written, the WLW potential is biased at VDD/2, the WLR potential is biased at 0, and under the condition, the polarization of the ferroelectric transistor cannot be changed, namely, the stored information cannot be changed.
When a read operation is performed on the memory cell, WLR is biased at VDD, T1 is in a conducting state, and WLW is biased at VDD/2. Judging the read information by using the method of measuring the bit line voltage variation, as shown in (a) (b) of fig. 4: BL is biased at VDD, if the ferroelectric transistor is in positive polarization state, the voltage on BL will be reduced from VDD to 0; if the state is negative polarization, the voltage on BL is always kept at VDD. The above-mentioned change can be detected by measuring the voltage on the BL with a voltage amplifier. In addition, the information read by the change judgment of the current on the BL can be measured, and for a large-scale array, the time delay is lower by the current change judgment compared with the voltage change judgment, because the capacitance on the BL needs to be charged and discharged when the voltage change judgment is carried out.
In the write operation to the memory cell, as shown in fig. 4 (c) (d), WLR is biased at 0 potential and the transistor T1 is in an off state, and if '1' is written to the memory cell, BL potential is biased at VDD and potential on WLW is biased twice: firstly biasing to VDD and then biasing to 0, when the information originally stored in the T2 is not changed when the information is biased to VDD for the first time, and when the information is biased to 0 for the second time, the T2 is changed into negative polarization, namely writing '1'; if a memory cell is written with '0', the BL potential is biased to 0, WLW performs the same operation as described above, T2 becomes positive when biased to VDD for the first time, i.e., when writing '0', and when biased to 0 for the second time, the previously written '0' is not changed. In addition, the writing operation can be realized by biasing the upper potential of WLW to 0 and then to VDD.
Considering the influence of the initial potential of each electrode of the transistor of the circuit unit on the correctness of the read-write operation, the memory designed by the principle can ensure the correctness of the read-write operation, because the potential on WLW is biased at VDD/2 before the read-write operation, so that the polarization state of T2 is not changed.
Next, an array circuit based on a ferroelectric transistor design proposed according to an embodiment of the present invention is described with reference to the drawings.
Fig. 5 is a schematic diagram of the structure of an array circuit based on a ferroelectric transistor design according to an embodiment of the present invention.
As shown in fig. 5, the array circuit based on the ferroelectric transistor design includes: at least one circuit unit as the above embodiment, and the units of the array circuit are combined into a layout of multiple rows and multiple columns by means of electrical connection, wherein the first word lines of the circuit units in the same row are connected, the second word lines of the circuit units in the same row are connected, and the bit lines of the circuit units in the same column are connected.
Further, in an embodiment of the present invention, when a read operation is performed on data stored in the circuit unit, the voltage of the second word line turns on the second transistor, so as to distinguish the data stored in the circuit unit according to a change influence of a magnitude of a resistance value between a drain and a source of the first transistor or a magnitude of a resistance value on a voltage or a current on the bit line.
Further, when writing data stored in the circuit unit, the voltages of the bit line and the first word line are controlled to make the polarization characteristic of the first transistor consistent with the data to be stored.
Further, when data stored in the circuit unit is written, the bit line voltage is biased at a high level or a low level, the voltage of the first word line is restored to an original voltage after the low voltage and the high voltage respectively stay for a period of time, and the voltage of the second word line enables the second transistor to be turned off.
In addition, as shown in fig. 6, fig. 6 is a schematic diagram of an array structure of the first memory according to the present invention, and a schematic diagram of transient waveforms under different operations of the first memory is shown in fig. 7.
According to the circuit unit and the array circuit based on the ferroelectric transistor design provided by the embodiment of the invention, for the nonvolatile memory with each circuit unit provided with two transistors, the energy delay product of the writing operation can be lower, so that the drain-source current-grid voltage hysteresis characteristic of the ferroelectric transistor is fully utilized, a novel circuit structure and an operation mode are designed, and the aim of the nonvolatile memory with lower power consumption is fulfilled.
The second embodiment of the present invention provides another circuit unit based on a ferroelectric transistor design based on the above embodiment, which has a respective emphasis on the description, and reference may be made between the embodiments without any further description. The second embodiment of the present invention will be explained in detail below.
The circuit unit based on the ferroelectric transistor design comprises: the first transistor, the second transistor, the third transistor, the first bit line, the second bit line, the first word line, the second word line and the third word line.
The grid electrode of the first transistor is connected with a first word line, the drain electrode of the first transistor is connected with the grid electrode of the second transistor, the source electrode of the first transistor is connected with a first bit line, the drain electrode of the second transistor is connected with the source electrode of the third transistor, the source electrode of the second transistor is connected with a second word line, the grid electrode of the third transistor is connected with the third word line, and the drain electrode of the third transistor is connected with the second bit line, wherein at least one transistor of the first transistor, the second transistor and the third transistor is a ferroelectric transistor.
In the second embodiment, each circuit unit uses three transistors and has two bit lines, as shown in fig. 8(a), a transistor T1 has a gate connected to a word line WLW, a drain connected to the gate of the ferroelectric transistor T2, and a source connected to a bit line BLW; the drain of the ferroelectric transistor T2 is connected to the source of the transistor T3, the source of which is connected to the word line WLRW; the gate of transistor T3 is connected to word line WLR and the drain is connected to bit line BLR;
under the condition of no external energy injection or external energy injection but no read-write operation on the data of the memory cell, the three word lines and the two bit lines are all biased at 0 potential, at the moment, the ferroelectric transistor works in a hysteresis interval of a drain-source current-gate voltage hysteresis curve, and the stored information cannot be changed.
When reading the memory cell, the WLR potential is biased at VDD, the WLW, BLW and WLRW potentials are all biased at 0, T1 is in the off state, and T3 is in the on state. As shown in fig. 8(a), the information stored in the circuit unit is judged by the change of the voltage on the BLR: biasing the BLR upper voltage at VDD, if T2 is negatively polarized, the BLR potential remains at VDD at all times; if positive, the BLR potential will decrease to 0. The change of the current on the BLR can also be judged to judge the information stored by the circuit unit, and an effective mode is provided for realizing the energy delay idealization of a large-scale storage array.
In a write operation to the memory cell, WLW is biased at VDD, WLR is biased at GND, T1 is in an on state, and T3 is in an off state. As shown in fig. 8(c) (d), if '1' is written into the memory cell, the BLW potential is biased at 0, and the WLWR is biased twice: first biased to VDD and then biased to 0, where when biased to VDD for the first time, T2 becomes negatively polarized, i.e. a '1' is written, and when biased to 0 for the second time, the previously written '1' is not changed; if '0' is written into the memory cell, the BLW potential is biased at VDD, WLWR performs the same operation as described above, the polarization state of T2 is not changed when biased to VDD for the first time, and T2 becomes positive when biased to 0 for the second time, i.e., writing '0'. In addition, the writing operation can be realized by biasing the upper potential of WLWR to 0 first and then to VDD.
The array circuit proposed according to the above embodiments based on ferroelectric transistor design is described next.
The array circuit based on ferroelectric transistor design includes: at least one circuit unit as in the second embodiment, and the units of the array circuit are combined into a layout manner of multiple rows and multiple columns by an electrical connection manner, wherein the first word lines of the circuit units in the same row are connected, the second word lines of the circuit units in the same row are connected, the third word lines of the circuit units in the same row are also connected, the first bit lines of the circuit units in the same column are connected, and the second bit lines of the circuit units in the same column are also connected.
Further, in an embodiment of the present invention, when a read operation is performed on data stored in the circuit unit, a voltage of the third word line turns on the third transistor, so as to distinguish the data stored in the circuit unit according to a magnitude of a resistance value between a drain and a source of the second transistor or an influence thereof.
Further, when writing data stored in the circuit unit, the voltages of the second word line and the first bit line are controlled, so that the polarization characteristic of the second transistor is consistent with the data required to be stored.
Further, when writing data stored in the circuit unit, the first bit line voltage is biased at a high level or a low level, the first transistor is turned on by the voltage of the first word line, and the third transistor is turned off by the voltage of the third word line.
Further, when the data stored in the circuit unit is written, the voltage of the second word line is restored to the original voltage after the low voltage and the high voltage respectively stay for a period of time.
In addition, as shown in fig. 9, fig. 9 is a schematic diagram of an array structure of a second memory.
According to the circuit unit and the array circuit which are designed based on the ferroelectric transistor, provided by the embodiment of the invention, for the nonvolatile memory with three transistors in each circuit unit, the energy delay product of the writing operation is effectively reduced, the normal state of other circuit units cannot be influenced by the writing operation of a certain circuit unit, and meanwhile, the circuit unit only needs the maintenance operation of single voltage, so that the drain-source current-grid voltage hysteresis characteristic of the ferroelectric transistor is fully utilized, a novel circuit structure and an operation mode are designed, and the purpose of the nonvolatile memory with lower power consumption is achieved.
Further, the first bit line and the second bit line in the second embodiment of the present invention may be merged into one bit line in a short form, and therefore, the third embodiment of the present invention provides another circuit unit based on a ferroelectric transistor design, and this embodiment and the above embodiments have each emphasis on the description, and all the embodiments may be referred to each other where not described in detail. The third embodiment of the present invention will be explained in detail below.
The circuit unit based on the ferroelectric transistor design comprises: the memory cell comprises a first transistor, a second transistor, a third transistor, a bit line, a first word line, a second word line and a third word line.
The grid electrode of the first transistor is connected with a first word line, the drain electrode of the first transistor is connected with the grid electrode of the second transistor, the source electrode of the first transistor is connected with a bit line, the drain electrode of the second transistor is connected with the source electrode of the third transistor, the source electrode of the second transistor is connected with the second word line, the grid electrode of the third transistor is connected with the third word line, and the drain electrode of the third transistor is connected with the bit line, wherein at least one transistor of the first transistor, the second transistor and the third transistor is a ferroelectric transistor.
In the third embodiment, three transistors are used in each circuit unit, and only one bit line is used, as shown in fig. 8(b), the gate of the transistor T1 is connected to the word line WLW, the drain is connected to the gate of the ferroelectric transistor T2, and the source is connected to the bit line BL; the drain of transistor T2 is connected to the source of transistor T3, the source being connected to word line WLRW; the gate of the transistor T3 is connected to the word line WLR, and the drain is connected to the bit line BL;
under the condition of no external energy injection or external energy injection but no read-write operation on the data of the memory cell, the three word lines and the bit lines are all biased at 0 potential, and at the moment, the ferroelectric transistor works in a hysteresis interval of a drain-source current-gate voltage hysteresis curve, and the stored information cannot be changed.
When reading the memory cell, the WLR potential is biased at VDD, the WLW and WLRW potentials are both biased at 0, T1 is in the off state, and T3 is in the on state. Judging the information stored by the circuit unit through the change of the voltage on the BL: biasing the voltage on BL at VDD, if T2 is in negative polarization, BL potential is always kept at VDD; if it is in positive polarization, the BL potential will decrease to 0. Determining the change in current on the BL may also determine the information stored by the circuit cell.
When the memory cell is written, the working principle of the memory cell is the same as that of the second memory circuit unit, and the writing operation of the third memory circuit unit can be realized only by changing the operation on BLW into BL operation and keeping other operations unchanged. For the second and third memories, the initial potential of each pole of the transistor of the circuit unit has no influence on the polarization of the ferroelectric transistor, i.e. the correctness of the read-write operation of the circuit unit is not influenced.
The array circuit proposed according to the above embodiments based on ferroelectric transistor design is described next.
The array circuit based on ferroelectric transistor design includes: at least one circuit unit as in the third embodiment, and the units of the array circuit are combined into a layout manner of multiple rows and multiple columns by an electrical connection manner, wherein the first word lines of the circuit units in the same row are connected, the second word lines of the circuit units in the same row are connected, the third word lines of the circuit units in the same row are also connected, and the bit lines of the circuit units in the same column are connected.
Further, in an embodiment of the present invention, when a read operation is performed on the data stored in the circuit unit, the voltage of the third word line turns on the third transistor, so as to distinguish the data stored in the circuit unit according to the magnitude of the resistance value between the drain and the source of the second transistor or the influence thereof.
Further, when writing data stored in the circuit unit, the voltages of the second word line and the bit line are controlled, so that the polarization characteristic of the second transistor is consistent with the data to be stored.
Further, when writing data stored in the circuit unit, the bit line voltage is biased at a high level or a low level, the first transistor is turned on by the voltage of the first word line, and the third transistor is turned off by the voltage of the third word line.
Further, when the data stored in the circuit unit is written, the voltage of the second word line is restored to the original voltage after the low voltage and the high voltage respectively stay for a period of time.
In addition, as shown in fig. 10, fig. 10 is a schematic diagram of an array structure of a third memory.
According to the circuit unit and the array circuit which are designed based on the ferroelectric transistor, provided by the embodiment of the invention, for the nonvolatile memory with three transistors in each circuit unit, the energy delay product of the writing operation is effectively reduced, the normal state of other circuit units cannot be influenced by the writing operation of a certain circuit unit, and meanwhile, the circuit unit only needs the maintenance operation of single voltage, so that the drain-source current-grid voltage hysteresis characteristic of the ferroelectric transistor is fully utilized, a novel circuit structure and an operation mode are designed, and the purpose of the nonvolatile memory with lower power consumption is achieved.
Further, on the basis of the above three embodiments, as shown in fig. 11 and fig. 12, fig. 11 is a comparison of three performances of write delay-average write energy, read delay-average read energy, and write delay-kinetic energy coefficient of different nonvolatile memories based on ferroelectric transistor design, and fig. 12 is a comparison of performance indexes between different nonvolatile memories based on ferroelectric transistor design.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (11)
1. A circuit cell designed based on a ferroelectric transistor, comprising: a first transistor, a second transistor, a bit line, a first word line, and a second word line,
the grid electrode of the first transistor is connected with the first word line, the drain electrode of the first transistor is connected with the bit line, the source electrode of the first transistor is connected with the drain electrode of the second transistor, the grid electrode of the second transistor is connected with the second word line, the source electrode of the second transistor is grounded or biased at a preset potential, and at least one of the first transistor and the second transistor is a ferroelectric transistor; when writing data stored in the circuit unit, the bit line voltage is biased at a high level VDD or a low level 0, the voltage of the first word line is recovered to the original voltage after the low voltage and the high voltage respectively stay for a period of time, and the voltage of the second word line enables a second transistor of the circuit unit to be cut off;
when writing data stored in the circuit unit, the voltage of the first word line is restored to the original voltage after the low voltage and the high voltage respectively stay for a period of time, including: when energy is injected, when the read-write operation is not carried out on the circuit unit data, the potential of the first word line is biased at VDD/2, the potential of the second word line is biased at 0, and the stored information cannot be changed; the second word line potential is biased at 0 potential, the second transistor is in a cut-off state, if 1 is written into the circuit unit, the bit line potential is biased at VDD, and the first word line potential is biased twice: biasing to VDD first and then to 0, wherein when the first biasing is to VDD, the information originally stored by the first transistor is not changed, when the first biasing is to 0, the first transistor is changed into negative polarization, and writing 1 is negative polarization; if 0 is written into the circuit unit, the potential of the bit line is biased to be 0, when the potential of the first word line is biased to VDD for the first time, the first transistor becomes positive, the written 0 is positive, and when the potential of the first word line is biased to be 0 for the second time, the written 0 is not changed; or the first word line potential is biased to 0 first and then to VDD, and the writing operation can also be realized.
2. An array circuit based on a ferroelectric transistor design, comprising:
at least one circuit unit according to claim 1, wherein the units of the array circuit are electrically connected to each other to form a layout with a plurality of rows and a plurality of columns, wherein the first word lines of the circuit units in the same row are connected to each other, the second word lines of the circuit units in the same row are connected to each other, and the bit lines of the circuit units in the same column are connected to each other.
3. The array circuit of claim 2, wherein,
when reading the data stored in the circuit unit, the voltage of the second word line of the circuit unit enables the second transistor of the circuit unit to be turned on, so that the data stored in the circuit unit is read and distinguished according to the resistance value between the drain and the source of the first transistor of the circuit unit or the change of the resistance value on the voltage or the current on the bit line of the circuit unit.
4. The array circuit of claim 2, wherein,
when writing the data stored in the circuit unit, the voltages of the bit line and the first word line are controlled to make the polarization characteristic of the first transistor of the circuit unit consistent with the data to be stored.
5. A circuit cell designed based on a ferroelectric transistor, comprising: a first transistor, a second transistor, a third transistor, a first bit line, a second bit line, a first word line, a second word line, and a third word line,
the grid electrode of the first transistor is connected with the first word line, the drain electrode of the first transistor is connected with the grid electrode of the second transistor, the source electrode of the first transistor is connected with the first bit line, the drain electrode of the second transistor is connected with the source electrode of the third transistor, the source electrode of the second transistor is connected with the second word line, the grid electrode of the third transistor is connected with the third word line, and the drain electrode of the third transistor is connected with the second bit line, wherein at least one of the first transistor, the second transistor and the third transistor is a ferroelectric transistor; under the condition of no external energy injection or external energy injection but no read-write operation on circuit unit data, three word lines and two bit lines are all biased at 0 potential, the ferroelectric transistor works in a hysteresis interval of a drain-source current-grid voltage hysteresis curve, and stored information cannot be changed;
during reading operation, the potential of the second word line is biased at VDD, the potentials of the first word line, the first bit line and the third word line are all biased at 0, the first transistor is in a cut-off state, and the third transistor is in a conducting state; judging the information stored by the circuit unit through the change of the voltage on the second bit line: biasing the voltage on the second bit line to VDD, and if the second transistor is in negative polarization, keeping the potential of the second bit line at VDD all the time; if the second transistor is in positive polarization, the second bit line potential will decrease to 0;
during writing operation, all three word lines and bit lines are biased at 0 potential, the ferroelectric transistor works in a hysteresis interval of a drain-source current-gate voltage hysteresis curve, stored information cannot be changed, when the circuit unit is written, the first word line potential is biased at VDD, the second word line potential is biased at 0 potential, the first transistor is in a conducting state, and the third transistor is in a stopping state; if 1 is written into the circuit unit, the first bit line potential is biased at 0, and the third word line potential is biased twice: firstly biasing to VDD and then biasing to 0, when the first biasing is to VDD, the second transistor becomes negative polarization, writing 1 is negative polarization, and when the second biasing is to 0, the written 1 is not changed; if 0 is written into the circuit unit, the potential of the first bit line is biased to VDD, the polarization state of the second transistor is not changed when the potential of the third word line is biased to VDD for the first time, the second transistor is changed into positive polarization when the potential of the third word line is biased to 0 for the second time, and the writing of 0 is positive polarization; or the potential of the third word line is biased to 0 first and then to VDD, and the writing operation can also be realized.
6. The circuit cell of claim 5, wherein the first bit line and the second bit line are merged into one bit line in a shorted form.
7. An array circuit based on a ferroelectric transistor design, comprising:
at least one circuit unit according to claim 5, wherein the units of the array circuit are electrically connected to each other to form a layout with a plurality of rows and a plurality of columns, wherein the first word lines of the circuit units in the same row are connected to each other, the second word lines of the circuit units in the same row are connected to each other, the third word lines of the circuit units in the same row are connected to each other, the first bit lines of the circuit units in the same column are connected to each other, and the second bit lines of the circuit units in the same column are connected to each other.
8. The array circuit of claim 7, wherein,
when reading the data stored in the circuit unit, the voltage of the third word line enables the third transistor to be turned on, so as to read and distinguish the data stored in the circuit unit according to the resistance value between the drain and the source of the second transistor or the change of the resistance value to the voltage or the current on the bit line of the circuit unit.
9. The array circuit of claim 7, wherein,
when writing the data stored in the circuit unit, controlling the voltages of the second word line and the first bit line to make the polarization characteristic of the second transistor of the circuit unit consistent with the data to be stored.
10. The array circuit of claim 9, wherein,
when writing data stored in the circuit unit, the first bit line voltage is biased at a high level or a low level, the first transistor is turned on by the voltage of the first word line, and the third transistor is turned off by the voltage of the third word line.
11. The array circuit according to any one of claims 7 to 10, wherein the first bit line and the second bit line are merged into one bit line in a shorted form.
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| CN112133339B (en) * | 2020-08-12 | 2023-03-14 | 清华大学 | Memory bit-by-bit logic calculation circuit structure based on ferroelectric transistor |
| CN112927738B (en) * | 2021-01-04 | 2022-10-25 | 清华大学 | Nonvolatile device based circuit and charge domain memory computing method |
| CN112967743B (en) * | 2021-04-07 | 2024-11-26 | 无锡舜铭存储科技有限公司 | Ferroelectric memory and operation method thereof |
| CN113257300B (en) | 2021-06-03 | 2023-06-06 | 清华大学 | Storage devices based on ferroelectric capacitors |
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| JP2921812B2 (en) * | 1992-12-24 | 1999-07-19 | シャープ株式会社 | Nonvolatile semiconductor memory device |
| JPH0745794A (en) * | 1993-07-26 | 1995-02-14 | Olympus Optical Co Ltd | Drive method for ferroelectric memory |
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