CN110415744A - Nonvolatile storage based on ferroelectric transistor - Google Patents
Nonvolatile storage based on ferroelectric transistor Download PDFInfo
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- CN110415744A CN110415744A CN201910626112.0A CN201910626112A CN110415744A CN 110415744 A CN110415744 A CN 110415744A CN 201910626112 A CN201910626112 A CN 201910626112A CN 110415744 A CN110415744 A CN 110415744A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2253—Address circuits or decoders
- G11C11/2255—Bit-line or column circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2253—Address circuits or decoders
- G11C11/2257—Word-line or row circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2273—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2275—Writing or programming circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2297—Power supply circuits
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Abstract
Nonvolatile storage the invention discloses one kind based on ferroelectric transistor, element circuit and array circuit including the nonvolatile storage designed based on ferroelectric transistor, its element circuit structure includes two transistors or three transistors, being combined into the array layout modes of several row several columns by way of electrical connection between multiple units.The present invention utilizes ferroelectric transistor drain-source current-grid voltage hysteretic characteristic, completes the high efficiency read-write operation to memory.
Description
Technical field
The present invention relates to low-power consumption Nonvolatile memory structure design fields, in particular to a kind of to be based on ferroelectric crystal
The nonvolatile storage of pipe.
Background technique
Under current era, with being growing for information content, people store information loss in order to prevent, to the non-of memory
More stringent requirements are proposed for volatile performance.Lots of memory, for example, (dynamic random access memory is moved DRAM
State random access memory), when having served as not having external power supply for a long time, the information stored on memory can be because of circuit devcie energy
It reduces and loses.Random-access NVM (nonvolatile memory, nonvolatile storage) can ask so that effective solution is above-mentioned
Topic.Current nonvolatile storage has PCRAM, ReRAM, FeRAM, STT-MRAM etc., but these memories are in data access
The energy of consumption and delay, the design complexities of processing compatibility, device durability degree, circuit etc. still have more deficiency
Place.
Currently, FeFET (the ferroelectric field effect based on new material and manufacture craft
Transistor, ferroelectric transistor) make the memory of design possess good processing compatibility and low power consumption characteristic, and
With preferable durability degree and moderate operating voltage, for example, the nearest test result delivered in the industry shows that FeFET reads and writes
The bias voltage of operation can be reduced within 1.5V.These features show ferroelectric transistor in Array Design, distributed number
It calculates the field (neuromorphic computing) according to storage (distributed data storage), neural network and gathers around
There is very big application potential.Further, in Nonvolatile memory design based on ferroelectric
Each circuit unit is devised in FETs and gathers around non-volatile memory array there are two transistor, realizes higher energy efficiency；
But design read-write voltage is higher, fails the potentiality for the energy-efficient for giving full play to ferroelectric transistor.
Summary of the invention
The present invention is directed to solve at least some of the technical problems in related technologies.
For this purpose, an object of the present invention is to provide the circuit unit that one kind is designed based on ferroelectric transistor, the circuit
Unit takes full advantage of drain-source current-grid voltage hysteretic characteristic of ferroelectric transistor, designs novel circuit structure and behaviour
Make mode, achievees the purpose that more low-power consumption nonvolatile storage.
It is another object of the present invention to propose corresponding battle array based on the circuit unit of aforementioned ferroelectric transistor design
Column circuits.
In order to achieve the above objectives, first aspect present invention embodiment proposes a kind of circuit based on ferroelectric transistor design
Unit, comprising: the first transistor, second transistor, bit line, the first wordline and the second wordline, wherein the first transistor
Grid is connected with first wordline, and the drain electrode of the first transistor is connected with the bit line, the source of the first transistor
Pole is connected with the drain electrode of the second transistor, and the grid of the second transistor is connected with second wordline, and described second
The source electrode of transistor is grounded or is biased in preset potential, and at least one transistor in the first transistor and second transistor
It is ferroelectric transistor.
In order to achieve the above objectives, second aspect of the present invention embodiment proposes a kind of array based on ferroelectric transistor design
Circuit, comprising: at least one circuit unit as described in above-described embodiment, and each unit of the array circuit pass through it is electrical
The mode of connection is combined into the layout type of multiple lines and multiple rows, wherein the first wordline with the circuit unit of a line is connected, same to a line
The second wordline of circuit unit be connected, the bit line of the circuit unit of same row is connected.
The circuit unit and array circuit based on ferroelectric transistor design of the embodiment of the present invention, for each circuit unit
The nonvolatile storage there are two transistor is gathered around, the energy delay product of write operation can be lower, to take full advantage of ferroelectricity
The drain-source current of transistor-grid voltage hysteretic characteristic designs novel circuit structure and mode of operation, has reached lower function
Consume the purpose of nonvolatile storage.
In addition, it is according to the above embodiment of the present invention based on ferroelectric transistor design array circuit can also have it is following
Additional technical characteristic:
Further, in one embodiment of the present of invention, wherein in the data stored to the wherein described circuit unit
When carrying out read operation, the second transistor of the circuit unit is connected in the voltage of the second wordline of the circuit unit, with
According to resistance value size between the drain-source of the first transistor of the circuit unit or the resistance value size to the circuit list
The variation of voltage or electric current on the bit line of member influences to differentiate the data of the circuit unit storage.
Further, in one embodiment of the present of invention, wherein in the data stored to the wherein described circuit unit
When carrying out write operation, the voltage of the bit line and first wordline is controlled, the pole of the first transistor of the circuit unit is made
It is consistent with the data of required storage to change characteristic.
Further, in one embodiment of the present of invention, wherein in the data stored to the wherein described circuit unit
When carrying out write operation, bit-line voltage is biased in high level or low level, and the voltage of first wordline is in low-voltage and height
Voltage restores after staying for some time respectively again to the voltage of script, and the voltage of second wordline makes the circuit unit
Second transistor cut-off.
In order to achieve the above objectives, third aspect present invention embodiment proposes a kind of circuit based on ferroelectric transistor design
Unit, comprising: the first transistor, second transistor, third transistor, the first bit line, the second bit line, the first wordline, the second word
Line and third wordline, wherein the grid of the first transistor is connected with first wordline, the drain electrode of the first transistor
It is connected with the grid of the second transistor, the source electrode of the first transistor is connected with first bit line, second transistor
Drain electrode be connected with the source electrode of third transistor, the source electrode of the second transistor is connected with second wordline, the third
The grid of transistor is connected with the third wordline, and the drain electrode of the third transistor is connected with second bit line, wherein institute
Stating at least one transistor in the first transistor, second transistor and third transistor is ferroelectric transistor.
In addition, it is according to the above embodiment of the present invention based on ferroelectric transistor design circuit unit can also have it is following
Additional technical characteristic:
Further, in one embodiment of the invention, the shape of first bit line and second bit line to be shorted
Formula merges into a bit line.
In order to achieve the above objectives, fourth aspect present invention embodiment proposes a kind of array based on ferroelectric transistor design
Circuit, comprising: at least one circuit unit as described in above-described embodiment, and each unit of the array circuit pass through it is electrical
The mode of connection is combined into the layout type of multiple lines and multiple rows, wherein the first wordline with the circuit unit of a line is connected, same to a line
Circuit unit the second wordline be connected, the third wordline with the circuit unit of a line is also connected, the circuit unit of same row
First bit line is connected, and the second bit line of the circuit unit of same row is also connected.
The circuit unit and array circuit based on ferroelectric transistor design of the embodiment of the present invention, for each circuit unit
The nonvolatile storage there are three transistor is gathered around, the energy delay product of write operation is effectively reduced, to some circuit unit
Write operation will not influence the normal condition of other circuit units, meanwhile, circuit unit only needs the maintenance of single voltage to operate,
To take full advantage of drain-source current-grid voltage hysteretic characteristic of ferroelectric transistor, novel circuit structure and behaviour are designed
Make mode, achievees the purpose that more low-power consumption nonvolatile storage.
In addition, it is according to the above embodiment of the present invention based on ferroelectric transistor design array circuit can also have it is following
Additional technical characteristic:
Further, in one embodiment of the invention, wherein in the number stored to the wherein described circuit unit
When according to carrying out read operation, the third transistor is connected in the voltage of the third wordline, according to the second transistor
Drain-source between resistance value size or its influence to differentiate the data of circuit unit storage.
Further, in one embodiment of the invention, wherein in the number stored to the wherein described circuit unit
When according to carrying out write operation, the voltage of second wordline and first bit line is controlled, the second crystal of the circuit unit is made
The polarization characteristic of pipe is consistent with the data of required storage.
Further, in one embodiment of the invention, wherein in the number stored to the wherein described circuit unit
When according to carrying out write operation, first bit-line voltage is biased in high level or low level, and the voltage of first wordline makes
The first transistor conducting, the voltage of the third wordline end the third transistor.
Further, in one embodiment of the invention, wherein in the number stored to the wherein described circuit unit
When according to carrying out write operation, the voltage of second wordline restores again after low-voltage and high voltage stay for some time respectively to original
This voltage.
Further, in one embodiment of the invention, the shape of first bit line and second bit line to be shorted
Formula merges into a bit line.
The additional aspect of the present invention and advantage will be set forth in part in the description, and will partially become from the following description
Obviously, or practice through the invention is recognized.
Detailed description of the invention
Above-mentioned and/or additional aspect and advantage of the invention will become from the following description of the accompanying drawings of embodiments
Obviously and it is readily appreciated that, in which:
Fig. 1 is the circuit symbol schematic diagram according to the ferroelectric transistor of the embodiment of the present invention；
Fig. 2 is the schematic diagram according to a kind of structure of the ferroelectric transistor of the embodiment of the present invention；
Fig. 3 is ferroelectric transistor drain-source conductance-gate source voltage hysteretic characteristic curve one kind according to the embodiment of the present invention
Typical case schematic diagram；
Fig. 4 is to be illustrated according to the structure and read-write operation of the circuit unit comprising two transistors of the embodiment of the present invention
Figure；
Fig. 5 is the structural schematic diagram according to the array circuit based on ferroelectric transistor design of the embodiment of the present invention；
Fig. 6 is a kind of array structure schematic diagram according to the first memory of the embodiment of the present invention；
Fig. 7 is according to the transient waveform schematic diagram under the first memory different operation of the embodiment of the present invention；
Fig. 8 is to be illustrated according to the structure and read-write operation of the circuit unit comprising three transistors of the embodiment of the present invention
Figure；
Fig. 9 is a kind of array structure schematic diagram according to second of memory of the embodiment of the present invention；
Figure 10 is a kind of array structure schematic diagram according to the third memory of the embodiment of the present invention；
Figure 11 is the different non-volatile memory write-in delay-based on ferroelectric transistor design according to the embodiment of the present invention
Energy averagely is written, read latch-averagely reads energy, the comparison schematic diagram of three kinds of performances of delay-kinetic energy coefficient is written；
Figure 12 is performance between the different non-volatile memory based on ferroelectric transistor design according to the embodiment of the present invention
The comparison schematic diagram of index.
Specific embodiment
The embodiment of the present invention is described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning to end
Same or similar label indicates same or similar element or element with the same or similar functions.Below with reference to attached
The embodiment of figure description is exemplary, it is intended to is used to explain the present invention, and is not considered as limiting the invention.
The embodiment of the present invention is mainly a kind of nonvolatile storage based on ferroelectric transistor, including is based on ferroelectric transistor
The element circuit and array circuit of the nonvolatile storage of design, element circuit structure include two transistors or three crystal
It manages, is combined into the layout type of several row several columns, the embodiment of the present invention between multiple units by way of electrical connection
Using ferroelectric transistor drain-source current-grid voltage hysteretic characteristic, the high efficiency read-write operation to memory is completed.
The circuit unit based on ferroelectric transistor design that describes to propose according to embodiments of the present invention with reference to the accompanying drawings and
Memory describes the circuit unit based on ferroelectric transistor design proposed according to embodiments of the present invention with reference to the accompanying drawings first.
The circuit unit based on ferroelectric transistor design includes: the first transistor, second transistor, bit line, the first word
Line and the second wordline.
Wherein, the grid of the first transistor is connected with the first wordline, and the drain electrode of the first transistor is connected with bit line, and first is brilliant
The source electrode of body pipe is connected with the drain electrode of second transistor, and the grid of second transistor is connected with the second wordline, second transistor
Source electrode is grounded or is biased in preset potential, and at least one transistor is ferroelectricity crystalline substance in the first transistor and second transistor
Body pipe.The circuit unit of the embodiment of the present invention can make full use of drain-source current-grid voltage hysteretic characteristic of ferroelectric transistor,
Novel circuit structure and mode of operation are designed, has achieved the purpose that more low-power consumption nonvolatile storage.
Preset potential can be understood as the source-biased of second transistor and fix current potential at certain, and those skilled in the art can be with
It is configured, is not specifically limited herein according to the actual situation.
It should be noted that the circuit symbol of ferroelectric transistor as shown in Figure 1, ferroelectric transistor a kind of structure such as Fig. 2
Shown, a kind of typical case of ferroelectric transistor drain-source conductance-gate source voltage hysteretic characteristic curve is as shown in Figure 3.
It will be further elaborated below by a specific embodiment to based on the circuit unit that ferroelectric transistor designs.
For each circuit unit, there are two the nonvolatile storages of transistor arrangement, as shown in figure 4, ferroelectric transistor T2
Grid be connected with wordline WLW, drain electrode be connected with bit line BL, source electrode is connected with the drain electrode of transistor T1；The grid of transistor T1
It is connected with wordline WLR, source-biased is in fixed current potential 0.
In the case where the injection of no external energy, bit line BL and two write word lines WLW, WLR are biased in 0 current potential, this
When ferroelectric transistor gate source voltage VGS=0, ferroelectric transistor works in drain-source current-grid voltage hysteresis loop hysteresis area
Between it is internal.When there is energy injection, when not being written and read to memory cell data, WLW current potential is biased in VDD/2, WLR electricity
Position is offset to 0, and ferroelectric transistor polarization will not change under above situation, that is, the information stored will not change.
When being read to storage unit, WLR current potential is offset to VDD, and T1 is in the conductive state, and WLW current potential is inclined
It sets in VDD/2.The information read using the method judgement of measurement bit-line voltage variation, such as (a) (b) of Fig. 4: BL current potential is biased in
VDD, if ferroelectric transistor is positive polarization state, the upper voltage of BL can be reduced to 0 from VDD；If it is negative polarization state, BL is powered on
Pressure remains at VDD.Above-mentioned variation can measure the voltage detecting on BL with voltage amplifier and arrive.Further, it is also possible to measure
The information that the variation judgement of the upper electric current of BL is read judges compared to passing through voltage large-scale array by curent change
Variation judgement delay is lower, the reason is that the upper capacitor of BL needs charge and discharge when being judged by voltage change.
When carrying out write operation to storage unit, as shown in (c) (d) of Fig. 4, WLR is biased in 0 current potential, at transistor T1
In off state, if BL current potential is biased in VDD, the upper current potential of WLW is biased twice toward storage unit write-in ' 1 ': first partially
VDD is set, then is biased to 0, the information that T2 was originally stored when being biased to VDD for the first time is biased to 0 there is no variation for the second time
When, T2 becomes negative polarization, that is, is written ' 1 '；If it is above-mentioned same that BL current potential is biased in 0, WLW progress toward storage unit write-in ' 0 '
The operation of sample, T2 becomes positive polarization when being biased to VDD for the first time, that is, is written ' 0 ', when being biased to 0 for the second time, has been written into before
' 0 ' there is no variation.In addition, current potential on WLW is first biased again 0, then it is biased to VDD, is also able to achieve write operation.
Consider that influence of the initial potential of each pole of circuit unit transistor to read-write operation correctness, principle design are deposited
Reservoir can guarantee the correctness of read-write operation, the reason is that the current potential on WLW can be biased in VDD/2 before read-write operation, make
The polarized state for obtaining T2 does not change.
The array circuit based on ferroelectric transistor design proposed according to embodiments of the present invention referring next to attached drawing description.
Fig. 5 is the structural schematic diagram of the array circuit based on ferroelectric transistor design of one embodiment of the invention.
As shown in figure 5, should include: at least one electricity such as above-described embodiment based on the array circuit that ferroelectric transistor designs
Road unit, and each unit of array circuit is combined into the layout type of multiple lines and multiple rows by way of electrical connection, wherein it is same
First wordline of the circuit unit of a line is connected, and the second wordline with the circuit unit of a line is connected, the circuit unit of same row
Bit line be connected.
Further, in one embodiment of the present of invention, wherein carried out to the data of the wherein circuit unit storage
When read operation, the second transistor is connected in the voltage of second wordline, according to the drain-source of the first transistor
Between resistance value size or resistance value size the variation of voltage or electric current on the bit line is influenced to differentiate the circuit unit
The data of storage.
Further, when carrying out write operation to the data of the wherein circuit unit storage, the bit line and institute are controlled
The voltage for stating the first wordline keeps the polarization characteristic of the first transistor consistent with the data of required storage.
Further, when carrying out write operation to the data of the wherein circuit unit storage, the biasing of institute's bitline voltage
In high level or low level, and the voltage of first wordline is extensive again after low-voltage and high voltage stay for some time respectively
The multiple voltage to script, the voltage of second wordline end the second transistor.
In addition, Fig. 6 is a kind of array structure schematic diagram of the first memory of the invention such as Fig. 6, and the first is stored
Transient waveform schematic diagram under device different operation is as shown in Figure 7.
The circuit unit and array circuit based on ferroelectric transistor design proposed according to embodiments of the present invention, for each
Circuit unit gathers around the nonvolatile storage there are two transistor, and the energy delay product of write operation can be lower, thus sufficiently benefit
With drain-source current-grid voltage hysteretic characteristic of ferroelectric transistor, novel circuit structure and mode of operation are designed, is reached
The more purpose of low-power consumption nonvolatile storage.
Based on a upper embodiment, second embodiment of the invention provides another circuit based on ferroelectric transistor design
Unit, the present embodiment and a upper embodiment emphasize particularly on different fields in description content, can phase for not describing ground between each embodiment
Mutually reference.Second embodiment of the invention will be described in detail below.
This based on ferroelectric transistor design circuit unit, comprising: the first transistor, second transistor, third transistor,
First bit line, the second bit line, the first wordline, the second wordline and third wordline.
Wherein, the grid of the first transistor is connected with the first wordline, the drain electrode of the first transistor and the grid of second transistor
Extremely it is connected, the source electrode of the first transistor is connected with the first bit line, and the drain electrode of second transistor is connected with the source electrode of third transistor,
The source electrode of second transistor is connected with the second wordline, and the grid of third transistor is connected with third wordline, the leakage of third transistor
Pole is connected with the second bit line, wherein at least one transistor in the first transistor, second transistor and third transistor
It is ferroelectric transistor.
In second of specific embodiment, each circuit unit has used three transistors, and has two bit lines, by Fig. 8
(a) shown in, the grid of transistor T1 is connected with wordline WLW, and drain electrode is connected with the grid of ferroelectric transistor T2, source electrode and bit line
BLW is connected；The drain electrode of ferroelectric transistor T2 is connected with the source electrode of transistor T3, and source electrode is connected with wordline WLRW；Transistor T3
Grid be connected with wordline WLR, drain electrode be connected with bit line BLR；
In the case where the injection of no external energy, or there is external energy to inject but memory cell data is not read
When write operation, three wordline and two bit lines are biased in 0 current potential, and ferroelectric transistor work at this time is in drain-source current-grid electricity
Inside the hysteresis section for pressing hysteresis loop, the information of storage will not change.
When being read to storage unit, WLR current potential is biased in VDD, and WLW, BLW, WLRW current potential are biased in
0, T1 is in off state, and T3 is in the conductive state.As shown in Fig. 8 (a), pass through the variation decision circuitry unit of voltage on BLR
The information of storage: being biased in VDD for voltage on BLR, if T2 is in negative polarization, BLR current potential remains at VDD；If place
In positive polarization, BLR current potential can be reduced to 0.Judge that the variation of electric current on BLR also may determine that the information of circuit unit storage,
To realize that the energy delay idealization of large-scale storage array provides a kind of effective mode.
When carrying out write operation to storage unit, WLW current potential is biased in VDD, and WLR current potential is biased in GND, and T1 is in and leads
Logical state, T3 are in off state.As shown in Fig. 8 (c) (d), if being biased in 0 toward write-in ' 1 ', BLW current potential in storage unit,
The upper current potential of WLWR is biased twice: it is first biased to VDD, then is biased to 0, when being biased to VDD for the first time, T2 becomes negative polarization,
' 1 ', when being biased to 0 for the second time is written, there is no variations for ' 1 ' had been written into before；If be written in toward storage unit
' 0 ', BLW current potential are biased in VDD, and WLWR carries out above-mentioned same operation, and T2 polarized state is not sent out when being biased to VDD for the first time
Raw to change, when being biased to 0 for the second time, T2 becomes positive polarization, that is, is written ' 0 '.In addition, current potential on WLWR is first biased again 0, then partially
VDD is set, write operation is also able to achieve.
Secondly the array circuit based on ferroelectric transistor design that description is proposed according to above-described embodiment.
The array circuit based on ferroelectric transistor design includes: at least one circuit unit such as second embodiment, and
Each unit of array circuit is combined into the layout type of multiple lines and multiple rows by way of electrical connection, wherein with the electricity of a line
First wordline of road unit is connected, and the second wordline with the circuit unit of a line is connected, with the third word of the circuit unit of a line
Line is also connected, and the first bit line of the circuit unit of same row is connected, and the second bit line of the circuit unit of same row is also connected.
Further, in one embodiment of the invention, wherein to the data of wherein circuit unit storage into
When row read operation, the third transistor is connected in the voltage of the third wordline, according to the leakage of the second transistor
Resistance value size between source or its influence to differentiate the data of the circuit unit storage.
Further, when carrying out write operation to the data of the wherein circuit unit storage, second wordline is controlled
With the voltage of first bit line, keep the polarization characteristic of the second transistor consistent with the data of required storage.
Further, when carrying out write operation to the data of the wherein circuit unit storage, first bit-line voltage
It is biased in high level or low level, the first transistor is connected in the voltage of first wordline, the third wordline
Voltage the third transistor is ended.
Further, when the data stored to the wherein described circuit unit carry out write operation, second wordline
Voltage restore again after low-voltage and high voltage stay for some time respectively to the voltage of script.
In addition, as shown in figure 9, Fig. 9 is a kind of array structure schematic diagram of second of memory.
The circuit unit and array circuit based on ferroelectric transistor design proposed according to embodiments of the present invention, for each
Circuit unit gathers around the nonvolatile storage there are three transistor, the energy delay product of write operation is effectively reduced, to some electricity
The write operation of road unit will not influence the normal condition of other circuit units, meanwhile, circuit unit only needs single voltage
Operation is maintained, to take full advantage of drain-source current-grid voltage hysteretic characteristic of ferroelectric transistor, designs novel circuit
Structure and mode of operation have achieved the purpose that more low-power consumption nonvolatile storage.
Further, the first bit line in second embodiment of the invention and the second bit line can be merged into the form of short circuit
One bit line, therefore, third embodiment of the invention provide another circuit unit based on ferroelectric transistor design, this reality
It applies example and above-described embodiment emphasizes particularly on different fields in description content, for can mutually refer to not describing between each embodiment.Under
Third embodiment of the invention will be described in detail in face.
This based on ferroelectric transistor design circuit unit include: the first transistor, second transistor, third transistor,
Bit line, the first wordline, the second wordline and third wordline.
Wherein, the grid of the first transistor is connected with the first wordline, the drain electrode of the first transistor and the grid of second transistor
Extremely it is connected, the source electrode of the first transistor is connected with bit line, and the drain electrode of second transistor is connected with the source electrode of third transistor, and second
The source electrode of transistor is connected with the second wordline, and the grid of third transistor is connected with third wordline, the drain electrode of third transistor with
Bit line is connected, wherein at least one transistor is ferroelectricity crystalline substance in the first transistor, second transistor and third transistor
Body pipe.
In the third specific embodiment, each circuit unit has used three transistors, and an only bit line, such as schemes
Shown in 8 (b), the grid of transistor T1 is connected with wordline WLW, and drain electrode is connected with the grid of ferroelectric transistor T2, source electrode and bit line
BL is connected；The drain electrode of transistor T2 is connected with the source electrode of transistor T3, and source electrode is connected with wordline WLRW；The grid of transistor T3 with
Wordline WLR is connected, and drain electrode is connected with bit line BL；
In the case where the injection of no external energy, or there is external energy to inject but memory cell data is not read
When write operation, three wordline and bit line are biased in 0 current potential, and ferroelectric transistor work at this time is stagnant in drain-source current-grid voltage
It returns inside the hysteresis section of curve, the information of storage will not change.
When being read to storage unit, WLR current potential is biased in VDD, and WLW, WLRW current potential are biased in 0, T1
In off state, T3 is in the conductive state.Pass through the information of the variation decision circuitry unit storage of voltage on BL: BL is powered on
Pressure is biased in VDD, if T2 is in negative polarization, BL current potential remains at VDD；If being in positive polarization, BL current potential can reduce
To 0.Judge that the variation of electric current on BL also may determine that the information of circuit unit storage.
When carrying out write operation to storage unit, the write-in of working principle and second of memory circuit unit
It operates identical, it is only necessary to the operation of BLW will be become operating BL, other operations are remained unchanged, be can be realized to the third
The write operation of kind memory circuit unit.For second and the third memory, each pole of circuit unit transistor it is initial
Current potential will not impact the polarization of ferroelectric transistor, that is, will not influence the correctness of circuit unit read-write operation.
Secondly the array circuit based on ferroelectric transistor design that description is proposed according to above-described embodiment.
The array circuit based on ferroelectric transistor design includes: at least one circuit unit such as 3rd embodiment, and
Each unit of array circuit is combined into the layout type of multiple lines and multiple rows by way of electrical connection, wherein with the electricity of a line
First wordline of road unit is connected, and the second wordline with the circuit unit of a line is connected, with the third of the circuit statement of account member of a line
Wordline is also connected, and the bit line of the circuit unit of same row is connected.
Further, in one embodiment of the invention, wherein read in the data stored to the circuit unit
When operation, the third transistor is connected in the voltage of the third wordline, with according to the drain-source of the second transistor it
Between resistance value size or its influence to differentiate the data of circuit unit storage.
Further, when the data stored to the circuit unit carry out write operation, second wordline and institute are controlled
The voltage of rheme line keeps the polarization characteristic of the second transistor consistent with the data of required storage.
Further, when the data stored to the circuit unit carry out write operation, institute's bitline voltage is biased in height
The first transistor is connected in level or low level, the voltage of first wordline, and the voltage of the third wordline makes
Obtain the third transistor cut-off.
Further, when the data stored to the circuit unit carry out write operation, the voltage of second wordline exists
Low-voltage and high voltage restore after staying for some time respectively again to the voltage of script.
In addition, as shown in Figure 10, Figure 10 is a kind of array structure schematic diagram of the third memory.
The circuit unit and array circuit based on ferroelectric transistor design proposed according to embodiments of the present invention, for each
Circuit unit gathers around the nonvolatile storage there are three transistor, the energy delay product of write operation is effectively reduced, to some electricity
The write operation of road unit will not influence the normal condition of other circuit units, meanwhile, circuit unit only needs single voltage
Operation is maintained, to take full advantage of drain-source current-grid voltage hysteretic characteristic of ferroelectric transistor, designs novel circuit
Structure and mode of operation have achieved the purpose that more low-power consumption nonvolatile storage.
Further, on the basis of above three embodiments, as is illustrated by figs. 11 and 12, Figure 11 is based on ferroelectric crystal
Averagely energy is written in the different non-volatile memory write-in delay-of pipe design, read latch-averagely reads energy, write-in delay-
The comparison of three kinds of performances of kinetic energy coefficient, Figure 12 are performance indicators between the different non-volatile memory based on ferroelectric transistor design
Comparison.
In addition, term " first ", " second " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance
Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include at least one this feature.In the description of the present invention, the meaning of " plurality " is at least two, such as two, three
It is a etc., unless otherwise specifically defined.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example
Point is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are not
It must be directed to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be in office
It can be combined in any suitable manner in one or more embodiment or examples.In addition, without conflicting with each other, the skill of this field
Art personnel can tie the feature of different embodiments or examples described in this specification and different embodiments or examples
It closes and combines.
Although the embodiments of the present invention has been shown and described above, it is to be understood that above-described embodiment is example
Property, it is not considered as limiting the invention, those skilled in the art within the scope of the invention can be to above-mentioned
Embodiment is changed, modifies, replacement and variant.
Claims (13)
1. it is a kind of based on ferroelectric transistor design circuit unit characterized by comprising the first transistor, second transistor,
Bit line, the first wordline and the second wordline, wherein
The grid of the first transistor is connected with first wordline, the drain electrode of the first transistor and the bit line phase
Even, the source electrode of the first transistor is connected with the drain electrode of the second transistor, the grid of the second transistor with it is described
Second wordline is connected, and the source electrode of the second transistor is grounded or is biased in preset potential, and the first transistor and the second crystalline substance
At least one transistor is ferroelectric transistor in body pipe.
2. a kind of array circuit based on ferroelectric transistor design characterized by comprising
At least one circuit unit as described in claim 1, and each unit of the array circuit passes through electrical connection
Mode is combined into the layout type of multiple lines and multiple rows, wherein the first wordline with the circuit unit of a line is connected, with the circuit of a line
Second wordline of unit is connected, and the bit line of the circuit unit of same row is connected.
3. array circuit according to claim 2, which is characterized in that wherein,
When the data stored to the wherein described circuit unit carry out read operation, the electricity of the second wordline of the circuit unit
Pressure is so that the second transistor of the circuit unit is connected, according to electric between the drain-source of the first transistor of the circuit unit
Resistance value size or the resistance value size are on described in the variation of voltage or electric current on the bit line of circuit unit influence resolution
The data of circuit unit storage.
4. array circuit according to claim 2, which is characterized in that wherein,
When the data stored to the wherein described circuit unit carry out write operation, the bit line and first wordline are controlled
Voltage, keep the polarization characteristic of the first transistor of the circuit unit consistent with the data of required storage.
5. array circuit according to claim 4, which is characterized in that wherein,
When the data stored to the wherein described circuit unit carry out write operation, bit-line voltage is biased in high level or low
Level, and the voltage of first wordline restores after low-voltage and high voltage stay for some time respectively again to the electricity of script
Pressure, the voltage of second wordline end the second transistor of the circuit unit.
6. it is a kind of based on ferroelectric transistor design circuit unit characterized by comprising the first transistor, second transistor,
Third transistor, the first bit line, the second bit line, the first wordline, the second wordline and third wordline, wherein
The grid of the first transistor is connected with first wordline, the drain electrode of the first transistor and second crystal
The grid of pipe is connected, and the source electrode of the first transistor is connected with first bit line, and the drain electrode of second transistor and third are brilliant
The source electrode of body pipe is connected, and the source electrode of the second transistor is connected with second wordline, the grid of the third transistor and
The third wordline is connected, and the drain electrode of the third transistor is connected with second bit line, wherein the first transistor,
At least one transistor is ferroelectric transistor in second transistor and third transistor.
7. circuit unit according to claim 6, which is characterized in that first bit line and second bit line are to be shorted
Form merge into a bit line.
8. a kind of array circuit based on ferroelectric transistor design characterized by comprising
At least one circuit unit as claimed in claim 6, and each unit of the array circuit passes through electrical connection
Mode is combined into the layout type of multiple lines and multiple rows, wherein the first wordline with the circuit unit of a line is connected, with the circuit of a line
Second wordline of unit is connected, and the third wordline with the circuit unit of a line is also connected, and first of the circuit unit of same row
Line is connected, and the second bit line of the circuit unit of same row is also connected.
9. array circuit according to claim 8, which is characterized in that wherein,
When the data stored to the wherein described circuit unit carry out read operation, the voltage of the third wordline makes described
Third transistor conducting, with according between the drain-source of the second transistor resistance value size or its influence to differentiate the electricity
The data of road unit storage.
10. array circuit according to claim 8, which is characterized in that wherein,
When the data stored to the wherein described circuit unit carry out write operation, second wordline and described first are controlled
The voltage of bit line keeps the polarization characteristic of the second transistor of the circuit unit consistent with the data of required storage.
11. array circuit according to claim 10, which is characterized in that wherein,
When the data stored to the wherein described circuit unit carry out write operation, first bit-line voltage is biased in high electricity
The first transistor is connected in flat or low level, the voltage of first wordline, and the voltage of the third wordline makes
The third transistor cut-off.
12. array circuit according to claim 11, which is characterized in that wherein,
When the data stored to the wherein described circuit unit carry out write operation, the voltage of second wordline is in low-voltage
Restore again after staying for some time respectively with high voltage to the voltage of script.
13. the array circuit as described in claim 8-12 any one, which is characterized in that first bit line and described second
Bit line merges into a bit line in the form being shorted.
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