CN112967743A - Ferroelectric memory and method of operating the same - Google Patents
Ferroelectric memory and method of operating the same Download PDFInfo
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- CN112967743A CN112967743A CN202110371162.6A CN202110371162A CN112967743A CN 112967743 A CN112967743 A CN 112967743A CN 202110371162 A CN202110371162 A CN 202110371162A CN 112967743 A CN112967743 A CN 112967743A
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- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/221—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using ferroelectric capacitors
Abstract
The invention provides a ferroelectric memory and an operation method thereof, comprising the following steps: a memory array configured to arrange a plurality of memory cells in rows and columns; a voltage generation circuit configured to provide a supply voltage to the memory array; control circuitry configured to perform read and write operations on the memory array; a voltage detection circuit configured to detect a power supply voltage, wherein: if the power supply voltage is less than the threshold voltage, the voltage detection circuit sends a first signal to the control circuit to prohibit the control circuit from performing read-write operation on the next storage unit.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and in particular, to a ferroelectric memory and an operating method thereof.
Background
Currently, ferroelectric technology has been applied in non-volatile solid state read/write memory devices. These memory devices, commonly referred to as "ferroelectric RAM" or "FeRAM" or "FRAM" devices, are now found in many electronic systems, particularly portable electronic devices and systems.
The reading operation of the FRAM is destructive, the read data is stored in an internal register, but the reading operation causes the data in the storage unit to be lost or destroyed, a 'write back' action is needed to rewrite the original data into the storage unit, otherwise, an error is caused in the next reading; when data is read and written, certain voltage/time requirements need to be met, if the voltage is too low or the time is too short, reading and writing failure can be caused, and data is permanently lost; power dissipation itself or improper system design may result in insufficient voltage/timing margin for full operation of the ferroelectric memory.
Disclosure of Invention
The invention aims to provide a ferroelectric memory and an operation method thereof, which aim to solve the problem that data is permanently lost due to insufficient voltage/time sequence allowance when the conventional ferroelectric memory reads and writes data.
To solve the above technical problem, the present invention provides a ferroelectric memory, comprising:
a memory array configured to arrange a plurality of memory cells in rows and columns;
a voltage generation circuit configured to provide a supply voltage to the memory array;
control circuitry configured to perform read and write operations on the memory array;
a voltage detection circuit configured to detect a power supply voltage, wherein:
if the power supply voltage is less than the threshold voltage, the voltage detection circuit sends a first signal to the control circuit to prohibit the control circuit from performing read-write operation on the next storage unit.
Optionally, in the ferroelectric memory, if the power supply voltage is greater than the threshold voltage, the voltage detection circuit sends a second signal to the control circuit, so that the control circuit can perform read-write operation on the memory array.
Optionally, in the ferroelectric memory, the read and write operations include:
the word line and the plate line are electrified, the sensing circuit reads the storage data of one storage unit, and the plate line is powered off after reading;
applying corresponding voltage to the plate line and/or the bit line to rewrite the storage data of the storage unit;
when a memory cell of the memory array performs read-write operation, if the control circuit receives the first signal, the read-write operation of the memory cell is completed, and the read-write operation of the next memory cell is stopped.
Optionally, in the ferroelectric memory, the memory array includes a parameter configuration storage area and a normal data storage area, where:
if the power supply voltage is greater than the threshold voltage, the voltage detection circuit sends a second signal to the control circuit so as to enable the control circuit to carry out read-write operation on the memory array;
when the ferroelectric memory is electrified, the electrifying time of the voltage detection circuit is earlier than that of the control circuit, if the power supply voltage is less than the threshold voltage, the voltage detection circuit sends a first signal to the control circuit to forbid the control circuit from carrying out read-write operation on the storage unit of the parameter configuration storage area, and when the control circuit receives a second signal, the control circuit is started to carry out read-write operation on the storage unit of the parameter configuration storage area to obtain configuration parameters, and the configuration parameter configuration register is used;
and after the operation is finished, performing read-write operation on the storage unit of the common data storage area.
Optionally, in the ferroelectric memory, the control circuit includes a read/write logic control circuit, an input/output latch circuit, a row address latch circuit, a column address latch circuit, a sensing circuit, a row decoder, a column decoder, and a memory cell driving circuit, where:
after the first signal or the second signal is provided to the read-write logic control circuit, the read-write logic control circuit forms logic instruction data and provides the logic instruction data to the input-output latch circuit, the row address latch circuit, the column address latch circuit, the sensing circuit, the row decoder, the column decoder and the storage unit driving circuit;
the input-output latch circuit, the row address latch circuit, the column address latch circuit, the sensing circuit, the row decoder, the column decoder, and the memory cell drive circuit are operated according to logic instruction data.
Optionally, in the ferroelectric memory, after the first signal is provided to the read/write logic control circuit, the read/write logic control circuit controls to stop the operation of the memory cell driving circuit, and does not stop the configuration operation of the input/output latch circuit, the row address latch circuit, the column address latch circuit, the sensing circuit, the row decoder, and the column decoder.
Optionally, in the ferroelectric memory, the control circuit further includes a row address latch circuit, a column address latch circuit, a sensing circuit, a row decoder, a column decoder, and a line driver, wherein:
when the second signal is supplied to the row address latch circuit, the column address latch circuit, the sensing circuit, the row decoder, the column decoder, and the line driver, the row address latch circuit, the column address latch circuit, the sensing circuit, the row decoder, the column decoder, and the line driver continue their operations.
Optionally, in the ferroelectric memory, the memory cell includes:
a capacitor having a first plate coupled to a plate line associated with a row containing the memory cells, a second plate, and a ferroelectric material disposed between the first plate and the second plate, wherein the capacitor is polarized to a first data state by applying a positive voltage between the first plate and the second plate that is greater than a first coercive voltage, and wherein the capacitor is polarized to a second data state by applying a negative voltage between the first plate and the second plate that is greater in magnitude than a second coercive voltage;
a pass transistor having a source/drain path connected between the second plate of the capacitor and a bit line associated with a column including the memory cell and a gate coupled to a word line associated with a row including the memory cell.
The present invention also provides an operating method of a ferroelectric memory, comprising:
arranging a plurality of memory cells in rows and columns to form a memory array, a voltage generating circuit supplying a power supply voltage to the memory array;
before or during the read-write operation of the control circuit on the memory array, the voltage detection circuit detects the power supply voltage, wherein:
if the power supply voltage is less than the threshold voltage, the voltage detection circuit sends a first signal to the control circuit to prohibit the control circuit from performing read-write operation on the next storage unit.
Optionally, in the operation method of the ferroelectric memory, the voltage detection is performed during power-on detection, and if the power supply voltage is smaller than the threshold voltage, only the read-write operation on the memory cell is stopped, and the configuration operation on the ferroelectric memory is not stopped.
Optionally, in the operating method of the ferroelectric memory, the ferroelectric memory array includes a parameter configuration storage area and a normal data storage area, where:
when the ferroelectric memory is electrified, the electrifying time of the voltage detection circuit is earlier than that of the control circuit, if the power supply voltage is less than the threshold voltage, the voltage detection circuit sends a first signal to the control circuit to forbid the control circuit from carrying out read-write operation on the storage unit of the parameter configuration storage area, and when the control circuit receives a second signal, the control circuit is started to carry out read-write operation on the storage unit of the parameter configuration storage area to obtain configuration parameters, and the configuration parameter configuration register is used;
and after the operation is finished, performing read-write operation on the storage unit of the common data storage area.
In the ferroelectric memory and the operation method thereof provided by the invention, when the control circuit performs read-write operation on the memory array, the voltage detection circuit detects the power supply voltage, if the power supply voltage is less than the threshold voltage, the control circuit is prohibited from performing read-write operation on the next storage unit, the read-write operation can be protected, and the risk of permanent data loss caused by insufficient voltage allowance when the ferroelectric memory reads and writes data is prevented.
Drawings
FIG. 1 is a schematic diagram of a ferroelectric memory according to one embodiment of the present invention;
FIG. 2 is a schematic diagram of a memory cell of a ferroelectric memory according to one embodiment of the present invention;
FIG. 3 is a schematic diagram of a method for operating a memory cell of a ferroelectric memory according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a method for operating a ferroelectric memory according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a method for operating a ferroelectric memory according to another embodiment of the present invention;
shown in the figure: 10-a voltage generation circuit; 20-a control circuit; 30-a voltage detection circuit; 100-memory array/memory cell.
Detailed Description
The invention is further elucidated with reference to the drawings in conjunction with the detailed description.
It should be noted that the components in the figures may be exaggerated and not necessarily to scale for illustrative purposes. In the figures, identical or functionally identical components are provided with the same reference symbols.
In the present invention, the embodiments are only intended to illustrate the aspects of the present invention, and should not be construed as limiting.
In the present invention, the terms "a" and "an" do not exclude the presence of a plurality of elements, unless otherwise specified.
It is further noted herein that in embodiments of the present invention, only a portion of the components or assemblies may be shown for clarity and simplicity, but those of ordinary skill in the art will appreciate that, given the teachings of the present invention, required components or assemblies may be added as needed in a particular scenario. Furthermore, features from different embodiments of the invention may be combined with each other, unless otherwise indicated. For example, a feature of the second embodiment may be substituted for a corresponding or functionally equivalent or similar feature of the first embodiment, and the resulting embodiments are likewise within the scope of the disclosure or recitation of the present application.
The numbering of the steps of the methods of the present invention does not limit the order of execution of the steps of the methods. Unless specifically stated, the method steps may be performed in a different order.
The ferroelectric memory and the operation method thereof according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The core idea of the invention is to provide a ferroelectric memory and an operation method thereof, so as to solve the problem that data is permanently lost due to insufficient voltage/time sequence allowance when the existing ferroelectric memory reads and writes data.
To achieve the above idea, the present invention provides a ferroelectric memory and an operating method thereof, including: a memory array configured to arrange a plurality of memory cells in rows and columns; a voltage generation circuit configured to provide a supply voltage to the memory array; control circuitry configured to perform read and write operations on the memory array; a voltage detection circuit configured to detect a power supply voltage, wherein: if the power supply voltage is less than the threshold voltage, the voltage detection circuit sends a first signal to the control circuit to prohibit the control circuit from performing read-write operation on the next storage unit.
The present embodiment provides a ferroelectric memory, as shown in fig. 1, including: a memory array 100 configured to arrange a plurality of memory cells in rows and columns; a voltage generation circuit 10 configured to supply a power supply voltage to the memory array 100; control circuitry 20 configured to perform read and write operations on the memory array 100; a voltage detection circuit 30 configured to detect a power supply voltage, wherein: if the power supply voltage is less than the threshold voltage, the voltage detection circuit 30 sends a first signal to the control circuit 20 to prohibit the control circuit 20 from performing the read/write operation on the next memory cell 100.
In one embodiment of the present invention, in the ferroelectric memory, the control circuit includes a read/write logic control circuit, an input/output latch circuit, a row address latch circuit, a column address latch circuit, a sensing circuit, a row decoder, a column decoder, and a memory cell driving circuit, wherein the read/write logic control circuit forms logic instruction data after a first signal or a second signal output from the voltage detection circuit is supplied to the read/write logic control circuit, and the logic instruction data output from the read/write logic control circuit is supplied to the input/output latch circuit, the row address latch circuit, the column address latch circuit, the sensing circuit, the row decoder, the column decoder, and the memory cell driving circuit; the input-output latch circuit, the row address latch circuit, the column address latch circuit, the sensing circuit, the row decoder, the column decoder, and the memory cell drive circuit are operated according to logic instruction data. When the voltage detection circuit detects that the power supply voltage is lower than the threshold voltage, the detection circuit outputs a first signal to the logic control circuit, and at the moment, the logic control circuit outputs a control signal to control the ferroelectric memory cell driving circuit and the like to stop the read-write operation of the memory cell. At this time, the logic control circuit does not stop the operation of configuring the other circuits of the memory such as the latch circuit, the address decoding circuit, and the register circuit. When the voltage detection circuit detects that the power supply voltage is higher than the threshold voltage, the detection circuit outputs a second signal to the logic control circuit, and the logic control circuit outputs a control signal at the moment, so that the ferroelectric memory cell driving circuit and the like can be controlled to carry out read-write operation on the memory cell.
In an embodiment of the present invention, in the ferroelectric memory, the memory array includes a parameter configuration storage area and a normal data storage area, the normal data storage area is used for storing its own data for a user, and can be changed, and the parameter configuration storage area stores some factory parameters or fixed parameters, which are not changed, and the importance of the parameter configuration storage area is greater than that of the normal data storage area, and when the ferroelectric memory is powered on, the data in the parameter configuration storage area is read first, and if the power voltage is unstable at this time, the data in the parameter configuration storage area may be permanently lost, therefore, this embodiment proposes to perform voltage protection on the reading operation of the parameter configuration storage area of the memory array when the ferroelectric memory is powered on, wherein the power-on time of the voltage detection circuit is earlier than the power-on time of the control circuit, and if the power voltage is less than the threshold voltage, the voltage detection circuit, the control circuit is prohibited from performing read-write operation on the storage unit of the parameter configuration storage area, the control circuit can be started after receiving the second signal, the storage unit of the parameter configuration storage area is subjected to read-write operation to obtain configuration parameters, and the configuration parameter configuration register is used; after the read-write operation is completed, the read-write operation is performed on the storage unit of the common data storage area, the data damage of the parameter configuration storage area, which is easily caused by the unstable power supply voltage when the ferroelectric memory is just powered on, is avoided, and the reliability of the ferroelectric memory is improved.
Fig. 2 shows a circuit diagram of a memory cell 100 in a memory array of a ferroelectric memory. As shown in fig. 2, a ferroelectric memory cell 100 of a ferroelectric memory according to the present invention has a ferroelectric capacitor 101 (i.e., a capacitor) and a transistor 102. The ferroelectric capacitor 101 has a first plate, a second plate, and a ferroelectric material (not shown). The first plate is coupled to a plate line PL associated with the row containing the memory cell and the other end is connected to one of the drain and source of transistor 102. The gate of the transistor 102 is connected to the word line WL, and the other of the drain and the source thereof is connected to the bit line BL. The ferroelectric material is disposed between the first plate and the second plate, wherein the capacitor is polarized to a first data state by applying a positive voltage between the first plate and the second plate that is greater than a first coercive voltage, and wherein the capacitor is polarized to a second data state by applying a negative voltage between the first plate and the second plate that is greater than a second coercive voltage; a pass transistor having a source/drain path connected between the second plate of the capacitor and a bit line associated with a column including the memory cell and a gate coupled to a word line associated with a row including the memory cell.
The operation method of the ferroelectric memory of the present invention is explained below.
First, a read/write operation of a memory cell of a ferroelectric memory is described, with reference to fig. 3, when performing the read/write operation on the memory cell, the method includes: a write operation, specifically, a word line driver of a memory cell driving circuit applies a voltage to a word line WL of a memory cell to be written, as shown in fig. 3, the word line WLj is a high voltage to turn on a transistor of the memory cell, then a bit line driver of the memory cell driving circuit applies a voltage to a bit line BL of the memory cell, and then a plate line driver applies a voltage to a plate line PL of the memory cell; when a low voltage is applied to bit line BL and a high voltage is applied to plate line PL, data 0 is written to the memory cell, see write 0 operation of fig. 3, when plate line PLk is high; when a high voltage is applied to the bit line BL and a low voltage is applied to the plate line PL, data 1 is written to the memory cell, see write 1 operation of fig. 3, while the bit line BLk is at a high voltage.
When a read operation is performed on a memory cell, a word line driver, specifically a memory cell driving circuit, applies a voltage to a word line WL of a memory cell to be written to turn on a transistor of the memory cell, and then a plate line driver of the memory cell driving circuit applies a high voltage to a plate line PL of the memory cell, and at this time, whether data stored in the memory cell is 0 or 1 is determined by sensing a voltage on a bit line BL of the memory cell. Because ferroelectric memories are read destructively, the polarization of the ferroelectric material in the memory cell changes after the data is read because a write back operation is required. The specific write-back step is the same as the write operation, and a description thereof is not repeated.
In the ferroelectric memory provided in this embodiment, when the control circuit performs a read/write operation on the memory array, the voltage detection circuit detects the power supply voltage, and if the power supply voltage is smaller than the threshold voltage, the control circuit is prohibited from performing the read/write operation on the next memory cell, so that the read/write operation can be protected, and the risk of permanent data loss due to insufficient voltage margin when the ferroelectric memory reads and writes data is prevented.
In an embodiment of the present invention, if the power supply voltage is greater than the threshold voltage, the voltage detection circuit sends a second signal to the control circuit to enable the control circuit to perform the read/write operation on the memory array, which enables the subsequent read/write operation to be recovered at any time, thereby increasing convenience.
As mentioned above, the memory array of the ferroelectric memory of the present invention includes the parameter configuration storage area and the normal storage area, and when the ferroelectric memory is powered on, the memory cells in the parameter configuration storage area are read and written to obtain the relevant configuration parameters of the ferroelectric memory. Referring to FIG. 4 and FIG. 5, in some embodiments of the present invention, the read/write operations for the parameter configuration storage area of the memory array include 5 read/write operations of 111-115. In the embodiment shown in fig. 4, in the power-on stage of the memory, the power supply voltage is unstable, a voltage drop occurs, the voltage drop speed is slow, when 5 operations of reading and writing the parameter configuration storage area of the memory array are all finished, the power supply voltage has not dropped below the threshold voltage, and because there is enough voltage for reading the parameter configuration storage area of the memory array, there is no read and write error caused by insufficient power supply voltage. And performing the voltage detection during power-on detection, and if the power supply voltage is less than the threshold voltage, only stopping the read-write operation of the memory unit and not stopping the configuration operation of the ferroelectric memory.
In the embodiment shown in fig. 5, in the power-up stage of the ferroelectric memory, the voltage of the power supply voltage drops, and the voltage drop speed is relatively fast, originally, 5 read/write operations of 111 to 115 need to be completed for the read/write operation on the parameter configuration area of the memory array in the power-up stage, when the read operation 114 is performed, the power supply voltage has already dropped below the threshold voltage, and if the operation 115 is continuously performed, because the power supply voltage is relatively low, during the read write-back operation, polarization inversion of the ferroelectric material may not occur, so that a write-back error may cause an error in data stored in the parameter configuration area of the memory array. Therefore, when the voltage detection circuit detects that the power supply voltage is lower than the threshold, it sends a first signal to the memory read/write logic control circuit to stop the read/write operation 115 on the parameter configuration area of the memory array. In some embodiments, if the read/write operation has occurred and the voltage detection circuit detects that the power supply voltage is lower than the threshold voltage, the current read/write operation is continuously completed and the operation is stopped from the next read/write operation.
In an embodiment of the present invention, in the ferroelectric memory, the voltage detection circuit further detects a voltage drop speed, calculates a time margin according to the voltage drop speed, and determines whether the time margin is less than a time of a read-write operation of one memory cell, if so, sends a first signal, otherwise, sends a second signal; or setting a time margin redundancy value, wherein the time margin redundancy value is a multiple of the time of the read-write operation of one memory cell, and when the time margin is less than the time margin redundancy value, sending the first signal, otherwise sending the second signal. As shown in FIG. 4, when the voltage detection circuit senses that the power voltage starts to drop, the voltage drop starting signal jumps to a falling edge, the time margin is calculated by dividing the voltage drop speed according to the difference between the power voltage and the threshold voltage, and as shown in FIG. 5, the time of the read-write operation of five memory cells arranged in sequence is 111-115.
In the ferroelectric memory and the operation method thereof provided by the invention, when the control circuit performs read-write operation on the memory array, the voltage detection circuit detects the power supply voltage, if the power supply voltage is less than the threshold voltage, the control circuit is prohibited from performing read-write operation on the next storage unit, the read-write operation can be protected, and the risk of permanent data loss caused by insufficient voltage allowance when the ferroelectric memory reads and writes data is prevented.
In summary, the above embodiments have described the ferroelectric memory and the operation method thereof in detail, and it is needless to say that the present invention includes but is not limited to the configurations listed in the above embodiments, and any changes based on the configurations provided by the above embodiments are within the protection scope of the present invention. One skilled in the art can take the contents of the above embodiments to take a counter-measure.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A ferroelectric memory, comprising:
a memory array configured to arrange a plurality of memory cells in rows and columns;
a voltage generation circuit configured to provide a supply voltage to the memory array;
control circuitry configured to perform read and write operations on the memory array;
a voltage detection circuit configured to detect a power supply voltage, wherein:
if the power supply voltage is less than the threshold voltage, the voltage detection circuit sends a first signal to the control circuit to prohibit the control circuit from performing read-write operation on the next storage unit.
2. The ferroelectric memory of claim 1, wherein the voltage detection circuit sends a second signal to the control circuit to enable the control circuit to perform read and write operations on the memory array if the supply voltage is greater than the threshold voltage.
3. The ferroelectric memory of claim 2, wherein the read and write operations comprise:
the word line and the plate line are electrified, the sensing circuit reads the storage data of one storage unit, and the plate line is powered off after reading;
applying corresponding voltage to the plate line and/or the bit line to rewrite the storage data of the storage unit;
when a memory cell of the memory array performs read-write operation, if the control circuit receives the first signal, the read-write operation of the memory cell is completed, and the read-write operation of the next memory cell is stopped.
4. A ferroelectric memory as in claim 3, wherein said memory array comprises a parameter configuration memory region and a normal data memory region, wherein:
when the ferroelectric memory is electrified, the electrifying time of the voltage detection circuit is earlier than that of the control circuit, if the power supply voltage is less than the threshold voltage, the voltage detection circuit sends a first signal to the control circuit to forbid the control circuit from carrying out read-write operation on the storage unit of the parameter configuration storage area, and when the control circuit receives a second signal, the control circuit is started to carry out read-write operation on the storage unit of the parameter configuration storage area to obtain configuration parameters, and the configuration parameter configuration register is used;
and after the operation is finished, performing read-write operation on the storage unit of the common data storage area.
5. The ferroelectric memory according to claim 4, wherein the control circuit comprises a read-write logic control circuit, an input-output latch circuit, a row address latch circuit, a column address latch circuit, a sensing circuit, a row decoder, a column decoder, and a memory cell drive circuit, wherein:
after the first signal or the second signal is provided to the read-write logic control circuit, the read-write logic control circuit forms logic instruction data and provides the logic instruction data to the input-output latch circuit, the row address latch circuit, the column address latch circuit, the sensing circuit, the row decoder, the column decoder and the storage unit driving circuit;
the input-output latch circuit, the row address latch circuit, the column address latch circuit, the sensing circuit, the row decoder, the column decoder, and the memory cell drive circuit are operated according to logic instruction data.
6. The ferroelectric memory according to claim 5, wherein the read/write logic control circuit controls to stop the operation of the memory cell driving circuit without stopping the operation of the arrangement of the input-output latch circuit, the row address latch circuit, the column address latch circuit, the sensing circuit, the row decoder, and the column decoder, after the first signal is supplied to the read/write logic control circuit.
7. The ferroelectric memory of claim 1, wherein the memory cell comprises:
a capacitor having a first plate coupled to a plate line associated with a row containing the memory cells, a second plate, and a ferroelectric material disposed between the first plate and the second plate, wherein the capacitor is polarized to a first data state by applying a positive voltage between the first plate and the second plate that is greater than a first coercive voltage, and wherein the capacitor is polarized to a second data state by applying a negative voltage between the first plate and the second plate that is greater in magnitude than a second coercive voltage;
a pass transistor having a source/drain path connected between the second plate of the capacitor and a bit line associated with a column including the memory cell and a gate coupled to a word line associated with a row including the memory cell.
8. A method of operating a ferroelectric memory, comprising:
arranging a plurality of memory cells in rows and columns to form a memory array, a voltage generating circuit supplying a power supply voltage to the memory array;
before or during the read-write operation of the control circuit on the memory array, the voltage detection circuit detects the power supply voltage, wherein:
if the power supply voltage is less than the threshold voltage, the voltage detection circuit sends a first signal to the control circuit to prohibit the control circuit from performing read-write operation on the next storage unit.
9. The operating method of a ferroelectric memory according to claim 10, wherein said voltage detection is performed at the time of power-on detection, and if the power supply voltage is less than the threshold voltage, only the read/write operation to the memory cell is stopped, and the configuration operation to the ferroelectric memory is not stopped.
10. The operating method of a ferroelectric memory according to claim 9, wherein said ferroelectric memory array comprises a parameter configuration memory area and a normal data memory area, wherein:
when the ferroelectric memory is electrified, the electrifying time of the voltage detection circuit is earlier than that of the control circuit, if the power supply voltage is less than the threshold voltage, the voltage detection circuit sends a first signal to the control circuit to forbid the control circuit from carrying out read-write operation on the storage unit of the parameter configuration storage area, and when the control circuit receives a second signal, the control circuit is started to carry out read-write operation on the storage unit of the parameter configuration storage area to obtain configuration parameters, and the configuration parameter configuration register is used;
and after the operation is finished, performing read-write operation on the storage unit of the common data storage area.
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