CN102081962B - EDRAM (Enhanced Dynamic Random Access Memory) unit of gain unit, memory and operating method - Google Patents

Abstract

The invention belongs to the technical field of dynamic random access memories and in particular relates to an EDRAM (Enhanced Dynamic Random Access Memory) unit of a gain unit, a memory and an operating method thereof. Based on a writing MOS (Metal Oxide Semiconductor) transistor, a reading MOS transistor, a writing word line, a writing bit line, a reading word line, a reading bit line and an equivalent parasitic capacitor, the EDRAM unit of the gain unit provided by the invention is obtained by increasing a coupling complementary MOS transistor and a shared bit line which is connected to a fixed voltage such that the EDRAM unit of the gain unit has the characteristics of long data retention time and low refreshing frequency; and the memory formed by the EDRAM unit of the gain unit has the characteristics of high reading speed and low power consumption.

Description

A kind of gain cell eDRAM unit, storer and method of operating

Technical field

The invention belongs to dynamic RAM (DRAM) technical field, be specifically related to a kind of embedded DRAM (eDRAM) technology, relate in particular to a kind of by writing MOS transistor, reading gain cell eDRAM (Gain Cell eDRAM) unit, storer and method of operating that MOS transistor and coupling and complementing MOS transistor form.

Background technology

Storer can be divided into chip external memory and in-line memory, in-line memory be a kind of be integrated in chip with chip system in the element of the common compositing chips of IP module such as each logic, mixed signal.In-line memory comprises embedded static RAM (eSRAM) and embedded DRAM (eDRAM), wherein, eDRAM is because its unit includes only a transistor and an electric capacity, and six transistors of eSRAM unit, have the little characteristics of cellar area relatively.

But, the manufacturing that the difficult point of traditional eDRAM is its electric capacity generally not with standard MOS process compatible, thereby DRAM technique and conventional logic process are widely different, the integration difficult of technique.Therefore industry has proposed to come with the stray capacitance of metal-oxide-semiconductor self thought of electric capacity in equivalent substitute DRAM.

See also Fig. 1, Figure 1 shows that the gain cell eDRAM cellular construction schematic diagram with two metal-oxide-semiconductors of prior art.This eDRAM is proposed in US Patent No. 7120072 by Intel Company, as shown in Figure 1, this Gain Cell eDRAM 100 comprise write MOS transistor 101, read MOS transistor 102, write word line (Write Word Line, WWL) 105, readout word line (Read Word Line, RWL) 106, write bit line (Write Bit Line, WBL) 107, sense bit line (Read BitLine, RBL) 108 and equivalent parasitic capacitances 104.Wherein, the source region of writing MOS transistor 101 is connected in the grid of reading MOS transistor 102, and MN point 103 is memory node, equivalent parasitic capacitances 104 1 ends are connected with 103, other end ground connection, therefore, the high low energy of the current potential that MN is ordered is controlled conducting and the shutoff of reading MOS transistor 102; For example, during electric capacity 104 stored charge, representative storage " 1 ", MN point 103 is noble potential, can control and read MOS transistor 102 shutoffs.Read a termination RBL of MOS transistor 102, another termination RWL; Write a termination WBL of MOS transistor 101, another termination is read the grid of MOS transistor 102.In this embodiment, equivalent parasitic capacitances 104 is for writing the active area stray capacitance of MOS transistor 101 or reading the gate capacitance of MOS transistor 102, also or both combinations.Illustrate its operating process below in conjunction with operating list:

Write operation (Write): when writing " 0 ", RWL, RBL set to 0 current potential, read MOS transistor 102 and do not work; WWL puts-400mV, writes MOS transistor 101 conductings, and WBL sets to 0 V, thus equivalent parasitic capacitances 104 discharges, and memory node 103 current potentials are 0.During one writing, RWL, RBL set to 0 current potential, read MOS transistor 102 and do not work; WWL puts-400mV, writes MOS transistor 101 conductings, and WBL puts 1V, thus equivalent parasitic capacitances 104 chargings, and memory node 103 current potentials are noble potential.

When (1) data keep, (Hold): RWL, RBL set to 0 current potential, read MOS transistor 102 and do not work, and WWL puts 1V, write MOS transistor 101 and turn-off, and the current potential of memory node 103 is not subjected to ectocine.

(2) read operation (Read): when reading " 0 ", WWL puts 1V, and WBL sets to 0 V, writes MOS transistor 101 and turn-offs; The RWL biasing is less than 1V, and RBL sets to 0 V, and read MOS transistor 102 conductings this moment, and RWL charges to RBL by reading MOS transistor, and because sensing circuit has clamping action, the electrical potential energy of RBL reaches 200mV, thereby can sense data " 0 ".When reading " 1 ", WWL puts 1V, and WBL sets to 0 V, writes MOS transistor 101 and turn-offs; The RWL biasing is read MOS transistor 102 this moment and is turn-offed less than 1V, and RWL can not charge to RBL by reading MOS transistor, and RBL keeps the 0V current potential, thereby can sense data " 1 ".

Gain Cell eDRAM shown in Figure 1 unit does not need to make in addition electric capacity, adopt standard CMOS process, and the relative eSRAM of its structure is simpler, can realize highdensity embedded storage.But, due to equivalent parasitic capacitances 104 for writing the active area stray capacitance of MOS transistor 101 or reading the gate capacitance of MOS transistor 102 or for writing the active area stray capacitance of MOS transistor 101 and the combination of reading the gate capacitance of MOS transistor 102, the capacitance less of equivalent parasitic capacitances 104, and the Sub-Threshold Characteristic that memory node 103 is write MOS transistor 101 affects, might leak electricity serious (direction of arrow as shown in fig. 1 produces electric leakage), thereby make the charge leakage of memory node very fast, the data hold time of considerable influence storage unit.

Figure 2 shows that the gain cell eDRAM cellular construction schematic diagram with three metal-oxide-semiconductors of prior art.Although cellular construction shown in Fig. 2 has solved the problem of being crosstalked by element coupling in same column selection with the gain cell eDRAM unit of two metal-oxide-semiconductors to a certain extent, make data hold time extend to some extent, but be still the gate capacitance sum of active area electric capacity He another metal-oxide-semiconductor of a metal-oxide-semiconductor due to stray capacitance, relative value is still very little, and it is serious that memory node is subject to writing the impact of metal-oxide-semiconductor subthreshold value electric leakage, make the charge leakage of memory node very fast, affect the data hold time of storage unit.

Summary of the invention

The technical problem to be solved in the present invention is, the stored charge that solves the gain cell eDRAM unit leaks very fast, the short problem of data hold time.

for solving above technical matters, the invention provides a kind of gain cell eDRAM unit, comprise and write MOS transistor, read MOS transistor, write word line, write bit line, readout word line, sense bit line, coupling and complementing MOS transistor and the common bit lines that connects fixed voltage, the source of described coupling and complementing MOS transistor/drain terminal connects the described common bit lines that connects fixed voltage, the grid of described coupling and complementing MOS transistor connects described sense bit line, the drain terminal of described coupling and complementing MOS transistor/source connects described drain terminal/source and the described grid of reading MOS transistor of writing MOS transistor, equivalent parasitic capacitances is formed at the described grid of reading MOS transistor.

According to one embodiment of the invention, wherein, the described MOS transistor of writing is the PMOS transistor with reading MOS transistor, and described coupling and complementing MOS transistor is nmos pass transistor.

According to still another embodiment of the invention, wherein, the described MOS transistor of writing is nmos pass transistor with reading MOS transistor, and described coupling and complementing MOS transistor is the PMOS transistor.

According to gain cell eDRAM provided by the present invention unit, wherein, described equivalent parasitic capacitances is to write the active area stray capacitance three's of the active area stray capacitance of MOS transistor, the gate capacitance of reading MOS transistor, coupling and complementing MOS transistor parallel combination.Described coupling and complementing MOS transistor with write MOS transistor and have essentially identical structural parameters.Described writing on MOS transistor, coupling and complementing MOS transistor put respectively substrate bias, to reduce simultaneously the subthreshold value electric leakage of writing MOS transistor and coupling and complementing MOS transistor.

The present invention provides the method for operating of the above gain cell eDRAM unit simultaneously, when data keep operation, write word line is set to make writes the first current potential that MOS transistor is closed, write bit line sets to 0 current potential, sense bit line is set to the second current potential that the coupling and complementing MOS transistor is closed, readout word line sets to 0 current potential or the second current potential, and the common bit lines that connects fixed voltage is set to set potential; With respect to equivalent parasitic capacitances, by the opposite direction of the sub-threshold current leakage of writing metal-oxide-semiconductor and the sub-threshold current leakage of passing through the coupling and complementing MOS transistor.

According to method of operating provided by the present invention, wherein, write operation: during one writing, write word line is set to and makes the 3rd current potential of writing the MOS transistor conducting, sense bit line is set to the second current potential that the coupling and complementing MOS transistor is closed, readout word line sets to 0 current potential or the second current potential, and write bit line is set to the first current potential, and equivalent parasitic capacitances is charged to the first current potential by writing MOS transistor; When writing " 0 ", write word line is set to and makes the 3rd current potential of writing the MOS transistor conducting, and sense bit line is set to the second current potential that the coupling and complementing MOS transistor is closed, and readout word line sets to 0 current potential or the second current potential, write bit line is set to 0 current potential, and equivalent parasitic capacitances is discharged to 0 current potential by writing MOS transistor.Described set potential is close to the first current potential.

According to method of operating provided by the present invention, wherein, read operation: when reading " 1 ", write word line is set to make writes the first current potential that MOS transistor is closed, write bit line sets to 0 current potential, and readout word line is put the first current potential, and sense bit line is charged in advance 0 current potential and keeps 0 current potential when read operation before read operation; When reading " 0 ", write word line is set to make writes the first current potential that MOS transistor is closed, and write bit line sets to 0 current potential, and readout word line is put the first current potential, and the current potential of sense bit line rises to from 0 current potential the current potential that amplifying circuit institute clamper is read in the periphery.

According to method of operating provided by the present invention, wherein, during refresh operation, adopt the pattern of write-after-read.

The present invention provides a kind of gain cell eDRAM simultaneously, and it comprises:

Gain cell eDRAM array, its aforesaid gain cell eDRAM unit are arranged by the form of row and column and are formed;

Line decoder;

Column decoder;

Sense amplifier;

Word line driver module;

The bit-line drive module;

The common bit lines driver module is for generation of the fixed voltage on all unit common bit lines; And

Logic control module is used for controlling described word line driver module and described bit-line drive module and keeps the sequential of operation and refresh operation in read operation, write operation, data.

Technique effect of the present invention is by increasing coupling and complementing MOS transistor and the common bit lines of receiving fixed voltage, to increase the equivalent parasitic capacitances that is used for the storage data; And when data keep, compensate the charge leakage of the memory node that the subthreshold value electric leakage of writing metal-oxide-semiconductor causes by the subthreshold current with the coupling and complementing MOS transistor of the subthreshold value electric leakage opposite direction of writing metal-oxide-semiconductor.Therefore, this gain cell eDRAM unit has the advantages that data hold time is long, refreshing frequency is low, and the storer that is formed by this gain cell eDRAM unit has characteristics low in energy consumption.And due to after storage unit maintenance data same time, the grid of reading transistor, it is the more approaching level that initially writes of level of memory node, like this can be faster whether conducting is coupled to the voltage on readout word line on sense bit line or continues to keep 0 level of precharge according to reading metal-oxide-semiconductor, improved data reading speed.

Description of drawings

Fig. 1 is the gain cell eDRAM cellular construction schematic diagram with two metal-oxide-semiconductors of prior art;

Fig. 2 is the gain cell eDRAM cellular construction schematic diagram with three metal-oxide-semiconductors of prior art;

Fig. 3 is the gain cell eDRAM cellular construction schematic diagram of first embodiment of the invention;

Fig. 4 is the operating list schematic diagram of gain cell eDRAM embodiment illustrated in fig. 3 unit 400;

Fig. 5 is the gain cell eDRAM cellular construction schematic diagram of second embodiment of the invention.

Fig. 6 is gain cell eDRAM memory construction schematic diagram provided by the invention, that rearranged by gain cell eDRAM embodiment illustrated in fig. 3 unit.

Embodiment

For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.

Figure 3 shows that the gain cell eDRAM cellular construction schematic diagram of first embodiment of the invention.As shown in Figure 3, this gain cell eDRAM unit 400 comprise write MOS transistor 401, read MOS transistor 402, coupling and complementing MOS transistor 403, write word line (Write Word Line, WWL) 406, write bit line (Write Bit Line, WBL) 407, readout word line (Read Word Line, RWL) 408, sense bit line (Read Bit Line, RBL) 409, connect the common bit lines (Common Bit Line, CBL) 410 of fixed voltage.Wherein, the grid of writing MOS transistor 401 is connected to WWL, controlled by WWL thereby write MOS transistor 401; The source of MOS transistor 401 (perhaps drain terminal) meets WBL, and the drain terminal of MOS transistor 401 (perhaps source) connects the grid of reading MOS transistor 402; The source (perhaps drain terminal) of reading MOS transistor 402 meets RWL, the drain terminal (perhaps source) of reading MOS transistor 402 connects RBL, and the grid of butt coupling complementary MOS transistor 403 simultaneously, the source of coupling and complementing transistor 403 (perhaps drain terminal) meets CBL, and the drain terminal of coupling and complementing transistor 403 (perhaps source) is connected to the grid of reading MOS transistor 402 or writes the drain terminal (perhaps source) of metal-oxide-semiconductor 401.Therefore, according to the stray capacitance of MOS crystal as can be known, can the grid of reading MOS transistor 402 or write the drain terminal (perhaps source) of metal-oxide-semiconductor 401 or the drain terminal (perhaps source) of coupling and complementing MOS transistor 403 and ground between have an equivalent parasitic capacitances, i.e. equivalent parasitic capacitances shown in Fig. 3 405.This equivalence stray capacitance 405 dots, be because this electric capacity is not self-existent capacitor element, but write the active area stray capacitance three's of the active area stray capacitance of MOS transistor 401, the gate capacitance of reading MOS transistor 402, coupling and complementing MOS transistor 403 parallel combination.Due to adding of coupling and complementing MOS transistor 403, the capacitance of equivalent parasitic capacitances 405 is greater than the capacitance of equivalent parasitic capacitances 104 of the prior art shown in Figure 1.This equivalence stray capacitance 405 can stored charge, is equal to the function that realizes the capacitor element in DRAM (dynamic RAM) unit, and therefore, position 404 can be defined as memory node.In one example, when equivalent parasitic capacitances 405 stored charge, memory node 404 is noble potentials, represent this eDRAM unit storage data " 1 ", when equivalent parasitic capacitances 405 discharged electric charge, memory node 404 was electronegative potentials, represented this eDRAM unit storage data " 0 ".Certainly, also can select opposite form to define store status.In this was embodiment illustrated in fig. 3, writing MOS transistor 401, reading MOS transistor 402 was the PMOS transistor, when its gate voltage is negative voltage signal, can make transistor 401 and 402 conductings.And coupling and complementing MOS transistor 403 is nmos pass transistor, when its gate voltage is positive voltage signal, can make transistor 403 conductings.Identical with traditional eDRAM unit, this unit 400 does not need special capacitor element preparation technology, is easy to the standard CMOS process compatibility.

Describe below in conjunction with operating list shown in Figure 4 method of operating to the gain cell eDRAM unit of Fig. 3 embodiment.

Figure 4 shows that the operating list schematic diagram of gain cell eDRAM embodiment illustrated in fig. 3 unit 400.Illustrate its write operation, read operation, data maintenance operation and refresh operation process below in conjunction with operating list:

(1) write operation (Write): during one writing, WWL is set to (V1) volt (V), for example,-V1 is set to-400 millivolts, write MOS transistor 400 conductings, RWL and RBL are set to respectively 0V, and WBL is set to VDD, thereby equivalent parasitic capacitances 405 is charged by WBL by writing MOS transistor 401, and memory node 404 current potentials are near high level VDD.When writing " 0 ", WWL be set to (V1) V writes MOS transistor 400 conductings, and RWL and RBL are set to respectively 0V, and WBL also is set to 0V, thus equivalent parasitic capacitances 405 by writing the 401 couples of WBL of MOS transistor discharge, memory node 404 current potentials are near low level 0.

(2) data keep operation (Hold): WWL puts VDD, and WBL sets to 0, and RWL and RBL also set to 0 respectively, writes MOS transistor 401 and 403 shutoffs of coupling and complementing MOS transistor, reads MOS transistor and does not work, and the current potential of memory node 404 is almost constant.Need to prove, introducing due to coupling and complementing MOS transistor 403, the fixed voltage that CBL410 puts is high voltage, and it is enough to leak electricity to compensate by the subthreshold value of coupling and complementing MOS transistor 403 the memory node current potential that causes by the subthreshold value electric leakage of writing MOS transistor 401 and reduces.Preferably, the fixed voltage of CBL410 is selected approximately to equate with Vdd (being the current potential of memory node 404).At this embodiment, can form the subthreshold value electric leakage of writing MOS transistor 401 of direction as shown in the figure and the subthreshold value electric leakage of coupling and complementing MOS transistor 403, especially when storage " 1 ", (this is because the data hold time of gain cell eDRAM is mainly determined by the unit of storage " 1 ", and it is much slow that the fall off rate of data 1 is compared in the rising of data " 0 "; For example, MOS transistor is read in observation, given threshold voltage is-0.3V, as long as the memory node of the unit of storage " 1 " drops to 0.9V from 1.2V, will make a mistake, rise to 0.9V from about 0V (in better situation, in the time of can complete due to write operation, write word line be drawn high and is coupled to the 200mV left and right) and just can make a mistake and the cell storage node of storage " 0 " is only had, thus can clearly see storage " 1 " weaken speed deciding factor especially).As from the foregoing, storage current potential in eDRAM unit compared to existing technology descends because of the current potential that the subthreshold value electric leakage of writing MOS transistor in keeping operating process causes, the current potential of the memory node 404 of this embodiment keeps the current potential of operating process to descend relatively slower in data, the data hold time of eDRAM unit 400 increases, thereby can greatly reduce the number of times of refresh operation.

(3) read operation (Read): when reading " 1 ", WWL meets VDD, and WBL meets 0, RWL and meets VDD, and RBL first is charged to 0 in advance, writes MOS transistor 401 this moment and turn-offs, if memory node 404 is " 1 ", reads MOS transistor 402 and turn-offs, and sense bit line RBL keeps 0 level.When reading " 0 ", WWL meets VDD, WBL meets 0, RWL and meets VDD, and RBL is charged to 0 current potential in advance before read operation, writing MOS transistor 401 this moment turn-offs, if memory node 404 is " 0 ", read MOS transistor 402 conductings, sense bit line RBL voltage rises from 0, read the clamping action of amplifying circuit due to the periphery of eDRAM storage unit 400, the current potential of RBL can reach V2 (voltage of amplifying circuit institute clamper is read in the periphery).Need to prove, V2 can be set to be slightly less than the threshold voltage of coupling and complementing MOS transistor 403 conductings, for example, when Vdd is 1.2V, the threshold voltage vt h of coupling and complementing MOS transistor 403 is 0.3 ~ 0.4V, and V2 is set to 0.3V, even the RBL current potential is V2, when completing due to write operation, write word line is drawn high storage node voltage and can be coupled to the 200mV left and right, therefore coupling and complementing MOS transistor 403 can conducting yet.Therefore also can not affect the current potential of memory node 404.As from the foregoing, can differentiate according to the different voltages on RBL the data mode that gain cell eDRAM unit 400 is stored.

(4) refresh operation: as from the foregoing, although, the data retention characteristics of this gain cell eDRAM unit 400 improves relatively greatly, but there is the grid leak electricity of writing MOS transistor 401 pipes and reading the subthreshold value electric leakage of MOS crystal 4 02 pipe and read MOS transistor 402 pipes due to memory node 404, even opposite direction, the sizableness of the relative memory node of subthreshold value electric leakage direction of 401 pipes, 403 pipes, but on the whole, a small amount of electric leakage is arranged unavoidably still.Therefore also need gain cell eDRAM unit 400 is regularly carried out refresh operation.But this refreshing frequency is lower, when refresh operation, adopts the pattern of write-after-read.

In above operating process, CBL410 all puts fixed voltage.

Therefore, as known from the above, on the one hand, the increase due to the capacitance of equivalent parasitic capacitances 404 makes the initial charge amount of memory node higher to a certain extent, in the situation that charge leakage speed is identical, data hold time can be longer.On the one hand, the leakage current path of the storage organization of gain cell eDRAM mainly comprises three parts in addition: subthreshold value electric leakage, PN junction electric leakage and electric leakage of the grid, and wherein, the subthreshold value electric leakage accounts for the overwhelming majority, and the PN junction electric leakage accounts for smaller portions, and electric leakage of the grid is almost ignored.EDRAM provided by the invention unit 400, due to the coupling and complementing metal-oxide-semiconductor and write the subthreshold value electric leakage opposite direction of metal-oxide-semiconductor, the big or small order of magnitude is identical, therefore can part mutually compensate for, thereby eDRAM elementary charge leakage provided by the invention is slower, make in the situation that memory node initial charge amount is identical, data hold time can be longer.

Further, because electric capacity increase and the subthreshold value electric leakage of memory node are offset, make and compare existing structure illustrated in figures 1 and 2, after storage unit keeps the data same time, the grid of reading transistor, be the more approaching level that initially writes of level of memory node, so just can be faster whether conducting is coupled to the voltage on readout word line on sense bit line or continues to keep 0 level of precharge according to reading metal-oxide-semiconductor, improved data reading speed.

Further again, the RWL of eDRAM provided by the invention unit and RBL connect low level when keeping, add data hold time long, make and refresh power consumption and significantly reduce, thereby on the operation total power consumption of eDRAM array, significant advantage is arranged.

Figure 5 shows that the gain cell eDRAM cellular construction schematic diagram of second embodiment of the invention.Contrast gain cell eDRAM cellular construction embodiment illustrated in fig. 3, this gain cell eDRAM unit 500 comprises equally: write MOS transistor 501, read MOS transistor 502, coupling and complementing MOS transistor 503, write word line (Write Word Line, WWL) 506, write bit line (Write Bit Line, WBL) 507, readout word line (Read Word Line, RWL) 508, sense bit line (ReadBit Line, RBL) 509, connect the common bit lines (Common Bit Line, CBL) 510 of fixed voltage.Equivalent parasitic capacitances 505 is write the active area stray capacitance three's of the active area stray capacitance of MOS transistor 501, the gate capacitance of reading MOS transistor 502, coupling and complementing MOS transistor 503 parallel combination equally, the state data memory of the current potential of memory node 504 reflection gain cell eDRAM unit 500.With difference embodiment illustrated in fig. 3 be: writing MOS transistor 501, reading MOS transistor 502 is nmos pass transistor, when its gate voltage is positive voltage signal, can make transistor 501 and 502 conductings.And coupling and complementing MOS transistor 503 is the PMOS transistor, when its gate voltage is negative voltage signal, can make transistor 503 conductings.This gain cell eDRAM embodiment illustrated in fig. 5 unit 500 is basic identical with the principle of work of gain cell eDRAM embodiment illustrated in fig. 3 unit 400, does not remake one by one at this and describes in detail.

What need to further illustrate is, for further improving the data hold time of gain cell eDRAM of the present invention unit, can design the coupling and complementing MOS transistor and write MOS transistor and have essentially identical structural parameters (such as the metal-oxide-semiconductor breadth length ratio etc.), thereby make the subthreshold value electric leakage of flowing through respectively the subthreshold value electric leakage of writing MOS transistor and the coupling and complementing MOS transistor that flows through more approaching in size.In addition, all right, put respectively substrate bias writing on MOS transistor, coupling and complementing MOS transistor, to reduce simultaneously the subthreshold value electric leakage of writing MOS transistor and coupling and complementing MOS transistor.

Figure 6 shows that gain cell eDRAM memory construction schematic diagram provided by the invention, that rearranged by gain cell eDRAM embodiment illustrated in fig. 3 unit.The single eDRAM storer of this gain comprises the gain unit array, and the gain unit array is to be arranged by the form of row and column by gain unit to form.Word line and bit line cross arrangement, gain unit are placed in the cross arrangement point.This gain cell eDRAM storer also comprises line decoder, column decoder, sense amplifier, word line driver module, bit-line drive module, common bit lines driver module and Logic control module.The function of Logic control module is to control word line driver module and the sequential of bit-line drive module in read operation, write operation, data keep operation and refresh operation.Wherein selected line chooses the bit-line voltage of row to change and can differentiate by sense amplifier, and compares with Vref (reference voltage), obtains sense data.Row address is counted the line of input code translator, is used for choosing WWL and the RWL of array, column address input column decoder, and the common bit lines driver module is for generation of the fixed voltage on all unit common bit lines, and this fixed voltage is higher level.

Without departing from the spirit and scope of the present invention, those skilled in the art can make the replacement to the identical functions of the concrete device in the gain cell eDRAM unit, replace with triode for coupling and complementing etc. such as the coupling and complementing MOS transistor.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the specific embodiment described in instructions.

Although the description of this invention is to make in the mode of reference example and preferred embodiment, those skilled in the art arrives cognition, under the prerequisite that does not depart from the scope of the present invention with spirit, can make a change on form or details.

Claims (8)

1. gain cell eDRAM unit, comprise and write MOS transistor, read MOS transistor, write word line, write bit line, readout word line, sense bit line, wherein, the grid of described MOS transistor is connected to described write word line, the described source of writing MOS transistor/drain terminal connects described write bit line, the described drain terminal of writing MOS transistor/source connects the described grid of reading MOS transistor, the described source of reading MOS transistor/drain terminal connects described write word line, the described drain terminal of reading MOS transistor/source connects described sense bit line, it is characterized in that, also comprise coupling and complementing MOS transistor and the common bit lines that connects fixed voltage, the source of described coupling and complementing MOS transistor/drain terminal connects the described common bit lines that connects fixed voltage, the grid of described coupling and complementing MOS transistor connects described sense bit line, the drain terminal of described coupling and complementing MOS transistor/source connects described drain terminal/source and the described grid of reading MOS transistor of writing MOS transistor,

Wherein, the parallel combination of writing the active area stray capacitance three of the active area stray capacitance of MOS transistor, the gate capacitance of reading MOS transistor, coupling and complementing MOS transistor is formed for storing the equivalent parasitic capacitances of data.

2. gain cell eDRAM according to claim 1 unit, is characterized in that, described to write MOS transistor and read MOS transistor be the PMOS transistor, and described coupling and complementing MOS transistor is nmos pass transistor; Perhaps the described MOS transistor of writing is nmos pass transistor with reading MOS transistor, and described coupling and complementing MOS transistor is the PMOS transistor.

3. gain cell eDRAM according to claim 1 unit, is characterized in that, described coupling and complementing MOS transistor with write MOS transistor and have essentially identical structural parameters.

4. gain cell eDRAM according to claim 1 unit, is characterized in that, described writing on MOS transistor, coupling and complementing MOS transistor put respectively substrate bias, to reduce simultaneously the subthreshold value electric leakage of writing MOS transistor and coupling and complementing MOS transistor.

5. the method for operating of a gain cell eDRAM as claimed in claim 1 unit, it is characterized in that, when data keep operation, write word line is set to make writes the first current potential that MOS transistor is closed, write bit line sets to 0 current potential, sense bit line is set to the second current potential that the coupling and complementing MOS transistor is closed, and readout word line sets to 0 current potential or the second current potential, and the common bit lines that connects fixed voltage is set to set potential; The opposite direction of the direction of the relatively described equivalent parasitic capacitances of sub-threshold current leakage by writing metal-oxide-semiconductor and the relative described equivalent parasitic capacitances of sub-threshold current leakage by the coupling and complementing MOS transistor.

6. method of operating according to claim 5, it is characterized in that, write operation: during one writing, write word line is set to and makes the 3rd current potential of writing the MOS transistor conducting, sense bit line is set to the second current potential that the coupling and complementing MOS transistor is closed, readout word line sets to 0 current potential or the second current potential, and write bit line is set to the first current potential, and equivalent parasitic capacitances is charged to the first current potential by writing MOS transistor; When writing " 0 ", write word line is set to and makes the 3rd current potential of writing the MOS transistor conducting, and sense bit line is set to the second current potential that the coupling and complementing MOS transistor is closed, and readout word line sets to 0 current potential or the second current potential, write bit line is set to 0 current potential, and equivalent parasitic capacitances is discharged to 0 current potential by writing MOS transistor;

Described set potential is close to the first current potential.

7. method of operating according to claim 5, it is characterized in that, read operation: when reading " 1 ", write word line is set to make writes the first current potential that MOS transistor is closed, write bit line sets to 0 current potential, readout word line is put the first current potential, and sense bit line is charged in advance 0 current potential and keeps 0 current potential when read operation before read operation; When reading " 0 ", write word line is set to make writes the first current potential that MOS transistor is closed, and write bit line sets to 0 current potential, and readout word line is put the first current potential, and the current potential of sense bit line rises to from 0 current potential the current potential that amplifying circuit institute clamper is read in the periphery.

8. method of operating according to claim 5, is characterized in that, during refresh operation, adopts the pattern of write-after-read.

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