CN102081962B - EDRAM (Enhanced Dynamic Random Access Memory) unit of gain unit, memory and operating method - Google Patents

Abstract

The invention belongs to the technical field of dynamic random access memories and in particular relates to an EDRAM (Enhanced Dynamic Random Access Memory) unit of a gain unit, a memory and an operating method thereof. Based on a writing MOS (Metal Oxide Semiconductor) transistor, a reading MOS transistor, a writing word line, a writing bit line, a reading word line, a reading bit line and an equivalent parasitic capacitor, the EDRAM unit of the gain unit provided by the invention is obtained by increasing a coupling complementary MOS transistor and a shared bit line which is connected to a fixed voltage such that the EDRAM unit of the gain unit has the characteristics of long data retention time and low refreshing frequency; and the memory formed by the EDRAM unit of the gain unit has the characteristics of high reading speed and low power consumption.

Description

Gain unit eDRAM unit, memory and operation method

technical field

The invention belongs to the technical field of dynamic random access memory (DRAM), in particular to an embedded dynamic random access memory (eDRAM) technology, in particular to a gain unit eDRAM (Gain Cell eDRAM) unit, memory and operation method.

Background technique

Memory can be divided into off-chip memory and embedded memory. Embedded memory is a basic part of the chip that is integrated in the chip with various logic and mixed signal IP modules in the chip system. Embedded memory includes embedded static random access memory (eSRAM) and embedded dynamic random access memory (eDRAM). Among them, eDRAM has the characteristics of small cell area because its unit only includes one transistor and one capacitor, compared with the six transistors of eSRAM unit .

However, the difficulty of traditional eDRAM is that the manufacture of its capacitors is generally not compatible with the standard MOS process, so the DRAM process is very different from the conventional logic process, and the integration of the process is quite difficult. Therefore, the industry has proposed the idea of using the parasitic capacitance of the MOS transistor itself to equivalently replace the capacitance in the DRAM.

Please refer to FIG. 1 . FIG. 1 is a schematic structural diagram of a gain unit eDRAM unit with two MOS transistors in the prior art. The eDRAM is proposed by Intel Corporation in U.S. Patent US7120072. As shown in FIG. (Read Word Line, RWL) 106, write bit line (Write Bit Line, WBL) 107, read bit line (Read BitLine, RBL) 108 and equivalent parasitic capacitance 104. Wherein, the source region of the write MOS transistor 101 is connected to the gate of the read MOS transistor 102, the MN point 103 is a storage node, one end of the equivalent parasitic capacitance 104 is connected to 103, and the other end is grounded, therefore, the potential level of the MN point can be controlled On and off of the read MOS transistor 102; for example, when the capacitor 104 stores charges, it means storing “1”, and the MN point 103 is at a high potential, which can control the read MOS transistor 102 to be turned off. One end of the read MOS transistor 102 is connected to RBL, and the other end is connected to RWL; one end of the write MOS transistor 101 is connected to WBL, and the other end is connected to the gate of the read MOS transistor 102 . In this embodiment, the equivalent parasitic capacitance 104 is the parasitic capacitance of the active region of the write MOS transistor 101 or the gate capacitance of the read MOS transistor 102 , or a combination of both. The operation process is described in detail below in conjunction with the operation list:

Write operation (Write): When writing "0", RWL and RBL are set to 0 potential, and the read MOS transistor 102 does not work; WWL is set to -400mV, the write MOS transistor 101 is turned on, and WBL is set to 0V, so that the equivalent parasitic capacitance 104 is discharged. The potential of the storage node 103 is 0. When writing "1", RWL and RBL are set to 0 potential, and the read MOS transistor 102 does not work; when WWL is set to -400mV, the write MOS transistor 101 is turned on, and WBL is set to 1V, so that the equivalent parasitic capacitor 104 is charged, and the potential of the storage node 103 is high potential.

(1) When data is held (Hold): RWL and RBL are set to 0 potential, the read MOS transistor 102 does not work, WWL is set to 1V, the write MOS transistor 101 is turned off, and the potential of the storage node 103 is not affected by the outside world.

(2) Read operation (Read): When reading "0", WWL is set to 1V, WBL is set to 0V, and the write MOS transistor 101 is turned off; RWL bias is less than 1V, and RBL is set to 0V. At this time, the read MOS transistor 102 is turned on, and RWL By reading the MOS transistor to charge RBL, because the readout circuit has a clamping effect, the potential of RBL can reach 200mV, so that the data "0" can be read out. When reading "1", WWL is set to 1V, WBL is set to 0V, and the write MOS transistor 101 is turned off; RWL bias is less than 1V, and the read MOS transistor 102 is turned off at this time, RWL will not charge RBL through the read MOS transistor, and RBL maintains 0V Potential, so that the data "1" can be read.

The Gain Cell eDRAM unit shown in Figure 1 does not require additional capacitors, uses a standard CMOS process, and has a simpler structure than eSRAM, enabling high-density embedded storage. However, since the equivalent parasitic capacitance 104 is the active region parasitic capacitance of the write MOS transistor 101 or the gate capacitance of the read MOS transistor 102, or the combination of the active region parasitic capacitance of the write MOS transistor 101 and the gate capacitance of the read MOS transistor 102 , the capacitance value of the equivalent parasitic capacitance 104 is relatively small, and the storage node 103 is affected by the sub-threshold characteristics of the write MOS transistor 101, and the leakage may be serious (leakage occurs in the direction of the arrow as shown in Figure 1), so that the storage node The charge leakage of the battery is very fast, which greatly affects the data retention time of the memory cell.

FIG. 2 is a schematic structural diagram of a gain unit eDRAM unit with three MOS transistors in the prior art. Although the unit structure shown in Figure 2 solves to some extent the problem of the gain unit eDRAM unit with two MOS transistors being coupled and crosstalked by the selected unit in the same column, which prolongs the data retention time, but the parasitic capacitance is still one MOS transistor The relative value of the sum of the active area capacitance and the gate capacitance of another MOS transistor is still very small, and the storage node is seriously affected by the subthreshold leakage of the write MOS transistor, which makes the charge leakage of the storage node very fast, affecting the data of the storage unit. keep time.

Contents of the invention

The technical problem to be solved by the present invention is to solve the problem that the storage charge of the gain unit eDRAM unit leaks quickly and the data retention time is short.

In order to solve the above technical problems, the present invention provides a gain unit eDRAM unit, including a write MOS transistor, a read MOS transistor, a write word line, a write bit line, a read word line, a read bit line, a coupled complementary MOS transistor, and a common A bit line, the source terminal/drain terminal of the coupled complementary MOS transistor is connected to the common bit line connected to a fixed voltage, the gate of the coupled complementary MOS transistor is connected to the read bit line, and the drain of the coupled complementary MOS transistor The terminal/source terminal is connected to the drain terminal/source terminal of the write MOS transistor and the gate of the read MOS transistor, and an equivalent parasitic capacitance is formed on the gate of the read MOS transistor.

According to an embodiment of the present invention, wherein the write MOS transistor and the read MOS transistor are PMOS transistors, and the coupled complementary MOS transistors are NMOS transistors.

According to yet another embodiment of the present invention, wherein the write MOS transistor and the read MOS transistor are NMOS transistors, and the coupled complementary MOS transistors are PMOS transistors.

According to the gain unit eDRAM unit provided by the present invention, the equivalent parasitic capacitance is the parasitic capacitance of the active region of the writing MOS transistor, the gate capacitance of the reading MOS transistor, and the parasitic capacitance of the active region of the coupling complementary MOS transistor Parallel combination. The coupling complementary MOS transistor has substantially the same structural parameters as the writing MOS transistor. The writing MOS transistor and the coupling complementary MOS transistor are respectively provided with substrate bias to simultaneously reduce the subthreshold leakage of the writing MOS transistor and the coupling complementary MOS transistor.

The present invention also provides the operation method of the above-mentioned gain unit eDRAM unit. During the data retention operation, the write word line is set to the first potential that closes the write MOS transistor, the write bit line is set to 0 potential, and the read bit line is set to make the coupling complementary The second potential where the MOS transistor is turned off, the read word line is set to 0 potential or the second potential, and the common bit line connected to a fixed voltage is set to a fixed potential; relative to the equivalent parasitic capacitance, the subthreshold leakage current through the write MOS transistor is coupled with the through coupling The direction of the subthreshold leakage current of complementary MOS transistors is opposite.

According to the operation method provided by the present invention, wherein, write operation: when writing "1", the write word line is set to the third potential that enables the write MOS transistor to be turned on, and the read bit line is set to the second potential that causes the coupled complementary MOS transistor to be turned off , the read word line is set to 0 potential or the second potential, the write bit line is set to the first potential, and the equivalent parasitic capacitance is charged to the first potential through the write MOS transistor; when writing "0", the write word line is set to make the write MOS transistor The third potential that is turned on, the read bit line is set to the second potential that makes the coupling complementary MOS transistor off, the read word line is set to 0 potential or the second potential, the write bit line is set to 0 potential, and the equivalent parasitic capacitance passes through the write MOS transistor is discharged to 0 potential. The fixed potential is close to the first potential.

According to the operation method provided by the present invention, wherein, the read operation: when reading "1", the write word line is set to the first potential that closes the write MOS transistor, the write bit line is set to 0 potential, the read word line is set to the first potential, and the read word line is set to the first potential. The bit line is precharged to 0 potential before the read operation and maintains 0 potential during the read operation; when reading "0", the write word line is set to the first potential that makes the write MOS transistor off, the write bit line is set to 0 potential, and the read word line is set to The first potential, the potential of the read bit line rises from 0 potential to the potential clamped by the peripheral sense amplifier circuit.

According to the operation method provided by the present invention, in the refresh operation, the mode of reading first and then writing is adopted.

The present invention also provides a gain unit eDRAM, which includes:

Gain unit eDRAM array, the aforementioned gain unit eDRAM units are arranged in the form of rows and columns;

row decoder;

column decoder;

Sensitive amplifier;

word line drive module;

bit line driver module;

a common bit line driver module for generating a fixed voltage on the common bit line of all cells; and

The logic control module is used to control the timing of the word line driving module and the bit line driving module in read operation, write operation, data hold operation and refresh operation.

The technical effect of the present invention is to increase the equivalent parasitic capacitance for storing data by increasing the coupling complementary MOS transistor and the common bit line connected to the fixed voltage; The subthreshold current of the complementary MOS transistor is coupled in the opposite direction to compensate the charge leakage of the storage node caused by the subthreshold leakage of the write MOS transistor. Therefore, the gain unit eDRAM unit has the characteristics of long data retention time and low refresh frequency, and the memory formed by the gain unit eDRAM unit has the characteristic of low power consumption. Moreover, after the memory cell keeps the data for the same time, the gate of the read transistor, that is, the level of the storage node is closer to the initial write level, so that the voltage on the read word line can be coupled faster according to whether the read MOS transistor is turned on. To the read bit line or continue to maintain the precharged 0 level, which improves the data read speed.

Description of drawings

FIG. 1 is a schematic structural diagram of a gain unit eDRAM unit with two MOS transistors in the prior art;

FIG. 2 is a schematic structural diagram of a gain unit eDRAM unit with three MOS transistors in the prior art;

3 is a schematic structural diagram of a gain unit eDRAM unit according to the first embodiment of the present invention;

FIG. 4 is a schematic diagram of an operation list of the gain unit eDRAM unit 400 of the embodiment shown in FIG. 3;

FIG. 5 is a schematic structural diagram of a gain unit eDRAM unit according to a second embodiment of the present invention.

FIG. 6 is a schematic structural diagram of a gain unit eDRAM memory provided by the present invention, which is composed of the arrangement of gain unit eDRAM units shown in FIG. 3 .

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings.

FIG. 3 is a schematic structural diagram of a gain unit eDRAM unit according to the first embodiment of the present invention. As shown in Figure 3, the gain unit eDRAM unit 400 includes a write MOS transistor 401, a read MOS transistor 402, a coupled complementary MOS transistor 403, a write word line (Write Word Line, WWL) 406, a write bit line (Write Bit Line, WBL) 407. Read Word Line (Read Word Line, RWL) 408. Read Bit Line (Read Bit Line, RBL) 409. Common Bit Line (Common Bit Line, CBL) 410 connected to a fixed voltage. Wherein, the gate of the write MOS transistor 401 is connected to WWL, so that the write MOS transistor 401 is controlled by WWL; the source (or drain) of the MOS transistor 401 is connected to WBL, and the drain (or source) of the MOS transistor 401 is connected to the read MOS The gate of the transistor 402; the source terminal (or drain terminal) of the read MOS transistor 402 is connected to RWL, the drain terminal (or source terminal) of the read MOS transistor 402 is connected to RBL, and is connected to the gate of the coupled complementary MOS transistor 403 at the same time, and the coupled complementary The source terminal (or drain terminal) of transistor 403 is connected to CBL, and the drain terminal (or source terminal) of coupled complementary transistor 403 is connected to the gate of read MOS transistor 402 or the drain terminal (or source terminal) of write MOS transistor 401 . Therefore, according to the parasitic capacitance of the MOS crystal, it can be known that there will be between the gate of the read MOS transistor 402 or the drain (or source) of the write MOS transistor 401 or the drain (or source) of the complementary MOS transistor 403 and the ground. An equivalent parasitic capacitance, that is, the equivalent parasitic capacitance 405 shown in FIG. 3 . The equivalent parasitic capacitance 405 is represented by a dotted line, because the capacitance is not an independent capacitive device, but the parasitic capacitance of the active region of the write MOS transistor 401, the gate capacitance of the read MOS transistor 402, and the active region of the coupled complementary MOS transistor 403. The parallel combination of the parasitic capacitance of the source region. Due to the addition of the coupling complementary MOS transistor 403 , the capacitance value of the equivalent parasitic capacitance 405 is greater than the capacitance value of the equivalent parasitic capacitance 104 in the prior art shown in FIG. 1 . The equivalent parasitic capacitance 405 can store charges, which is equivalent to realizing the function of a capacitive device in a DRAM (Dynamic Random Access Memory) unit. Therefore, the position 404 can be defined as a storage node. In one example, when the equivalent parasitic capacitance 405 stores charges, the storage node 404 is at a high potential, representing that the eDRAM cell stores data “1”, and when the equivalent parasitic capacitance 405 releases charges, the storage node 404 is at a low potential, representing The eDRAM cell stores data "0". Of course, the opposite form can also be chosen to define the storage state. In the embodiment shown in FIG. 3 , the write MOS transistor 401 and the read MOS transistor 402 are PMOS transistors, and when the gate voltage thereof is a negative voltage signal, the transistors 401 and 402 can be turned on. The coupled complementary MOS transistor 403 is an NMOS transistor, and when its gate voltage is a positive voltage signal, the transistor 403 can be turned on. Same as the traditional eDRAM cell, the cell 400 does not require special fabrication process of capacitor device, and is easy to be compatible with standard CMOS process.

The operation method of the gain unit eDRAM unit in the embodiment of FIG. 3 will be described below in conjunction with the operation list shown in FIG. 4 .

FIG. 4 is a schematic diagram of an operation list of the gain unit eDRAM unit 400 of the embodiment shown in FIG. 3 . The following combined operation list specifically describes its write operation, read operation, data retention operation and refresh operation process:

(1) Write operation (Write): When writing "1", WWL is set to (-V1) volts (V), for example, -V1 is set to -400 millivolts, the write MOS transistor 400 is turned on, and RWL and RBL are respectively set to is 0V, WBL is set to VDD, so that the equivalent parasitic capacitance 405 is charged by WBL through the write MOS transistor 401, and the potential of the storage node 404 is close to the high level VDD. When writing "0", WWL is set to (-V1)V, the write MOS transistor 400 is turned on, RWL and RBL are respectively set to 0V, and WBL is also set to 0V, so that the equivalent parasitic capacitance 405 discharges WBL through the write MOS transistor 401 , the potential of the storage node 404 is close to low level 0.

(2) Data holding operation (Hold): WWL is set to VDD, WBL is set to 0, RWL and RBL are also set to 0 respectively, the write MOS transistor 401 and the coupled complementary MOS transistor 403 are turned off, the read MOS transistor does not work, and the potential of the storage node 404 Almost unchanged. It should be noted that due to the introduction of the coupling complementary MOS transistor 403, the fixed voltage set by the CBL410 is a relatively high voltage, which is sufficient to compensate for the subthreshold leakage caused by the write MOS transistor 401 through the subthreshold leakage of the coupling complementary MOS transistor 403. The potential of the storage node decreases. Preferably, the fixed voltage selection of CBL 410 is approximately equal to Vdd (ie, the potential of storage node 404 ). In this embodiment, the subthreshold leakage of the write MOS transistor 401 and the subthreshold leakage of the coupling complementary MOS transistor 403 can be formed in the direction shown in the figure, especially when storing "1", (this is because the data of the gain unit eDRAM The hold time is mainly determined by the cell storing "1", and the rising rate of data "0" is much slower than the falling rate of data 1; When the storage node of the cell drops from 1.2V to 0.9V, an error will occur, and the storage node of the cell storing "0" will only go from about 0V (in a better case, it will be blocked by the write word line when the write operation is completed). Coupled to about 200mV) rises to 0.9V to make an error, so it can be clearly seen that the weakening rate of the stored "1" is even more decisive). It can be seen from the above that, compared with the storage potential in the eDRAM cell of the prior art due to the potential drop caused by the subthreshold leakage of the write MOS transistor during the hold operation, the potential of the storage node 404 in this embodiment is lower during the data hold operation. The potential drop of the eDRAM unit 400 is relatively slower, and the data retention time of the eDRAM unit 400 is increased, so that the number of refresh operations can be greatly reduced.

(3) Read operation (Read): When reading "1", WWL is connected to VDD, WBL is connected to 0, RWL is connected to VDD, RBL is precharged to 0 first, and the write MOS transistor 401 is turned off at this time. If the storage node 404 is "1" ”, the read MOS transistor 402 is turned off, and the read bit line RBL maintains 0 level. When reading "0", WWL is connected to VDD, WBL is connected to 0, RWL is connected to VDD, and RBL is precharged to 0 potential before the read operation. At this time, the write MOS transistor 401 is turned off. If the storage node 404 is "0", the read MOS transistor 402 is turned on, the voltage of the read bit line RBL rises from 0, and due to the clamping effect of the peripheral sense amplifier circuit of the eDRAM storage unit 400, the potential of RBL can reach V2 (the voltage clamped by the peripheral sense amplifier circuit). It should be noted that V2 can be set to be slightly lower than the threshold voltage at which the coupled complementary MOS transistor 403 is turned on. For example, when Vdd is 1.2V, the threshold voltage Vth of the coupled complementary MOS transistor 403 is 0.3~0.4V, and V2 is set to 0.3 V, even if the potential of RBL is V2, the voltage of the storage node will be coupled to about 200mV when the writing word line is pulled up when the writing operation is completed, so the coupled complementary MOS transistor 403 will not be turned on. Therefore, the potential of the storage node 404 is not affected. It can be known from the above that the data state stored in the gain unit eDRAM unit 400 can be distinguished according to different voltages on the RBL.

(4) Refresh operation: As can be seen from the above, although the data retention characteristics of the gain unit eDRAM unit 400 are relatively greatly improved, due to the subthreshold leakage of the write MOS transistor 401 and the read MOS transistor 402 in the storage node 404 and the read MOS The gate leakage of the transistor 402, even though the direction of the subthreshold leakage of the transistor 401 and 403 is opposite to that of the storage node, and the magnitude is the same, but overall, there is still a small amount of leakage unavoidable. Therefore, it is also necessary to periodically refresh the gain cell eDRAM unit 400 . However, the refresh frequency is low, and the mode of reading first and then writing is adopted during the refresh operation.

During the above operations, CBL410 is set to a fixed voltage.

Therefore, it can be seen from the above that, on the one hand, due to the increase of the capacitance value of the equivalent parasitic capacitance 404, the initial charge amount of the storage node is higher to some extent, and the data retention time can be longer under the condition of the same charge leakage rate. On the other hand, the leakage path of the storage structure of the gain unit eDRAM mainly includes three parts: subthreshold leakage, PN junction leakage and gate leakage. Leakage is almost negligible. In the eDRAM unit 400 provided by the present invention, since the subthreshold leakage directions of the coupled complementary MOS transistor and the write MOS transistor are opposite and the order of magnitude is the same, they will partially offset each other. Therefore, the charge leakage of the eDRAM unit provided by the present invention is slower. When the initial charge of the node is the same, the data retention time can be longer.

Further, due to the increase in the capacitance of the storage node and the offset of subthreshold leakage, compared with the existing structures shown in Figures 1 and 2, after the storage unit retains data for the same time, the gate of the read transistor, that is, the level of the storage node It is closer to the initial write level, so that the voltage on the read word line can be coupled to the read bit line according to whether the read MOS tube is turned on faster or continue to maintain the precharged 0 level, which improves the data read speed .

Furthermore, the RWL and RBL of the eDRAM unit provided by the present invention are connected to a low level when maintaining, and the data retention time is longer, so that the refresh power consumption is greatly reduced, so there is a significant difference in the total power consumption of the operation of the eDRAM array. Advantage.

FIG. 5 is a schematic structural diagram of a gain unit eDRAM unit according to a second embodiment of the present invention. Compared with the gain unit eDRAM unit structure of the embodiment shown in FIG. 3, the gain unit eDRAM unit 500 also includes: a write MOS transistor 501, a read MOS transistor 502, a coupled complementary MOS transistor 503, a write word line (Write Word Line, WWL) 506, Write Bit Line (WBL) 507, Read Word Line (RWL) 508, Read Bit Line (RBL) 509, Common Bit Line (CBL) 510 connected to a fixed voltage . The equivalent parasitic capacitance 505 is also the parallel combination of the parasitic capacitance of the active area of the write MOS transistor 501, the gate capacitance of the read MOS transistor 502, and the parasitic capacitance of the active area of the coupling complementary MOS transistor 503, and the potential of the storage node 504 reflects the gain unit The data storage state of the eDRAM cell 500 . The difference from the embodiment shown in FIG. 3 is that the write MOS transistor 501 and the read MOS transistor 502 are NMOS transistors, and when the gate voltage is a positive voltage signal, the transistors 501 and 502 can be turned on. The coupled complementary MOS transistor 503 is a PMOS transistor, and when its gate voltage is a negative voltage signal, the transistor 503 can be turned on. The working principle of the gain unit eDRAM unit 500 in the embodiment shown in FIG. 5 is basically the same as that of the gain unit eDRAM unit 400 in the embodiment shown in FIG. 3 , and will not be described in detail here.

It should be further explained that, in order to further improve the data retention time of the gain unit eDRAM unit of the present invention, the coupling complementary MOS transistor and the writing MOS transistor can be designed to have substantially the same structural parameters (such as the MOS tube width-to-length ratio, etc.), so that the respective flow The subthreshold leakage of the overwriting MOS transistor and the subthreshold leakage of the flowing coupled complementary MOS transistor are closer in magnitude. In addition, it is also possible to respectively set substrate bias voltages on the writing MOS transistor and the coupling complementary MOS transistor, so as to simultaneously reduce the subthreshold leakage of the writing MOS transistor and the coupling complementary MOS transistor.

FIG. 6 is a schematic structural diagram of a gain unit eDRAM memory provided by the present invention, which is composed of the array of gain unit eDRAM units shown in FIG. 3 . The single-gain eDRAM memory includes a gain unit array, and the gain unit array is formed by arranging the gain units in the form of rows and columns. The word lines and the bit lines are arranged crosswise, and the gain unit is placed at the point of the crosswise arrangement. The gain unit eDRAM memory also includes a row decoder, a column decoder, a sense amplifier, a word line driver module, a bit line driver module, a common bit line driver module and a logic control module. The function of the logic control module is to control the timing of the word line driver module and the bit line driver module in read operation, write operation, data hold operation and refresh operation. The change of the bit line voltage of the selected row and selected column can be distinguished by the sense amplifier and compared with Vref (reference voltage) to obtain the readout data. The number of row addresses is input to the row decoder, which is used to select WWL and RWL in the array, the column address is input to the column decoder, and the common bit line driver module is used to generate a fixed voltage on the common bit line of all units. high level.

Without departing from the spirit and scope of the present invention, those skilled in the art can make functional equivalent replacements for specific devices in the gain unit eDRAM unit, for example, replacing the coupling complementary MOS transistor with a complementary coupling triode, etc. It should be understood that the invention is not limited to the specific embodiments described in the specification, except as defined in the appended claims.

Although the present invention has been described by way of reference to examples and preferred embodiments, workers skilled in the art will recognize that changes may be made in form or detail without departing from the scope and spirit of the invention. make change.

Claims (8)

1. A gain unit eDRAM unit, comprising a write MOS transistor, a read MOS transistor, a write word line, a write bit line, a read word line, and a read bit line, wherein the gate of the MOS transistor is connected to the write word line, the The source/drain of the write MOS transistor is connected to the write bit line, the drain/source of the write MOS transistor is connected to the gate of the read MOS transistor, and the source/drain of the read MOS transistor is connected to The write word line, the drain terminal/source terminal of the read MOS transistor is connected to the read bit line, and it is characterized in that it also includes a common bit line coupled to a complementary MOS transistor and a fixed voltage, and the source of the coupled complementary MOS transistor The terminal/drain terminal is connected to the common bit line connected to a fixed voltage, the gate of the coupled complementary MOS transistor is connected to the read bit line, and the drain terminal/source terminal of the coupled complementary MOS transistor is connected to the write MOS transistor. a drain terminal/source terminal and a gate of the read MOS transistor; The parasitic capacitance of the active area of the writing MOS transistor, the gate capacitance of the reading MOS transistor, and the parasitic capacitance of the active area of the coupling complementary MOS transistor form an equivalent parasitic capacitance for storing data. 2. The gain unit eDRAM unit according to claim 1, wherein the write MOS transistor and the read MOS transistor are PMOS transistors, and the coupled complementary MOS transistor is an NMOS transistor; or the write MOS transistor and the read MOS transistor The transistor is an NMOS transistor, and the coupled complementary MOS transistor is a PMOS transistor. 3 . The gain unit eDRAM unit according to claim 1 , wherein the coupling complementary MOS transistor and the write MOS transistor have substantially the same structural parameters. 4 . 4. The gain cell eDRAM unit according to claim 1, wherein the write MOS transistor and the coupled complementary MOS transistor are respectively provided with substrate bias voltages to simultaneously reduce the subthreshold of the write MOS transistor and the coupled complementary MOS transistor Leakage. 5. A method of operating the gain unit eDRAM unit as claimed in claim 1, wherein, during data retention operation, the write word line is set to the first potential that writes the MOS transistor to be closed, the write bit line is set to 0 potential, and the read bit line is set to 0 potential. The bit line is set to the second potential that makes the coupling complementary MOS transistor close, the read word line is set to 0 potential or the second potential, and the common bit line connected to a fixed voltage is set to a fixed potential; the subthreshold leakage current of the write MOS transistor is relatively The direction of the equivalent parasitic capacitance is opposite to the direction of the subthreshold leakage current through the coupled complementary MOS transistor relative to the equivalent parasitic capacitance. 6. The operation method according to claim 5, characterized in that, write operation: when writing "1", the write word line is set to the third potential that makes the write MOS transistor conductive, and the read bit line is set to make the coupling complementary MOS transistor The second potential is turned off, the read word line is set to 0 potential or the second potential, the write bit line is set to the first potential, and the equivalent parasitic capacitance is charged to the first potential through the write MOS transistor; when writing "0", the write word line is set to the first potential. In order to make the write MOS transistor turn on the third potential, the read bit line is set to the second potential to turn off the coupled complementary MOS transistor, the read word line is set to 0 potential or the second potential, and the write bit line is set to 0 potential, which is equivalent to parasitic The capacitor is discharged to 0 potential through the write MOS transistor; The fixed potential is close to the first potential. 7. The operation method according to claim 5, characterized in that, read operation: when reading "1", the write word line is set to the first potential that makes the write MOS transistor closed, the write bit line is set to 0 potential, and the read word line is set to 0 potential. The first potential, the read bit line is precharged to 0 potential before the read operation and remains at 0 potential during the read operation; when reading "0", the write word line is set to the first potential that turns off the write MOS transistor, and the write bit line is set to 0 potential , the read word line is set to the first potential, and the potential of the read bit line rises from 0 potential to the potential clamped by the peripheral sense amplifier circuit. 8. The operation method according to claim 5, characterized in that, during the refresh operation, a mode of reading first and then writing is adopted.

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