CN102800359B - A semiconductor memory device - Google Patents

A semiconductor memory device Download PDF

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CN102800359B
CN102800359B CN201110137561.2A CN201110137561A CN102800359B CN 102800359 B CN102800359 B CN 102800359B CN 201110137561 A CN201110137561 A CN 201110137561A CN 102800359 B CN102800359 B CN 102800359B
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device
memory
memory device
gate
connected
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CN102800359A (en
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刘明
许中广
霍宗亮
龙世兵
谢常青
张满红
李冬梅
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中国科学院微电子研究所
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Abstract

本发明公开一种半导体存储器件,包括:存储单元;每个所述存储单元包括字线、位线、阻变存储器件、选通器件和存储电容;所述阻变存储器件的一端与所述位线相连,另一端与所述选通器件的源极/漏极相连;所述选通器件的栅极与一条所述字线相连,所述选通器件的漏极/源极与另一条所述字线相连;所述存储电容的一端与所述选通器件的漏极/源极相连,另一端接地。 The present invention discloses a semiconductor memory device, comprising: a storage unit; each of said memory cells includes word lines, bit lines, resistive memory devices, gating device and a storage capacitor; one end of said resistive memory device and said a bit line connected to the other end of the gating device source / drain connected; said gating device is connected to the gate of the word line, the gate device drain / source with another the word line is connected; one end of the storage capacitor and the gate of the device source / drain connected to ground. 本发明所公开的半导体存储器件,同时具有动态存储器的功耗低,速度快的优点,又能够实现非挥发性的存储。 The semiconductor memory device as disclosed in the present invention, while the dynamic memory with low power consumption, high speed advantages, but also enables the non-volatile memory.

Description

一种半导体存储器件 A semiconductor memory device

技术领域 FIELD

[0001] 本发明涉及集成电路技术领域,特别是涉及一种半导体存储器件。 [0001] The present invention relates to the field of integrated circuit technology, particularly to a semiconductor memory device.

背景技术 Background technique

[0002]目前的半导体存储器市场,以挥发性的动态随机存储器(DRAM)和静态随机存储器(SRAM)及非挥发性的“闪存”存储器(Flash)为代表。 [0002] The current semiconductor memory market to volatile dynamic random access memory (DRAM) and static random access memory (SRAM) and non-volatile "flash" memory (Flash) as the representative. 动态随机存储器(DRAM)是可以快速读写的存储器件,具有高密度,高速度,价格低廉等优势,一直占有很大的半导体存储器市场。 Dynamic random access memory (DRAM) is a quick read-write memory device with a high density, high speed, low cost and other advantages, has always played a large semiconductor memory market. 嵌入式动态随机存储器(eDRAM)和其他逻辑电路共同集成在一个芯片内,可以省去大量的缓冲器和I/O压点,从而可以有更高的速度,更小的面积和更低的功耗。 Embedded dynamic random access memory (eDRAM), and other logic circuits integrated together in one chip, can save a lot of buffer and I / O pads, so that there may be a higher speed, smaller size and lower power consumption. 由于DRAM核与逻辑电路之间有内建的宽位数据总线,这种大量并行处理能力使嵌入式DRAM可以满足吉位时代的T byte/s数据通量的要求。 An internal-bit data bus width between the logic circuit and the DRAM core, so that a large number of parallel processing capability to meet the requirements of embedded DRAM Gb times T byte / s data throughput.

[0003]目前动态随机存储器的结构主要是一晶体管一电容(1T1C)的动态随机存储器结构。 [0003] The current structure of the DRAM is mainly a transistor a capacitor (1T1C) dynamic random access memory structure. 动态随机存储器的存储单元典型地包括两个元件,也就是存储电容器和存取晶体管,构成1T1C的结构。 Memory cells are typically dynamic random access memory comprises two elements, namely a storage capacitor and an access transistor, constituting the 1T1C configuration. 图1是一个传统的动态随机存储器阵列结构,其中100至103是选通晶体管,110至111是位线,108至109是字线,112至113是位线上的寄生电容,104至107是存储电容器。 FIG 1 is a conventional dynamic random access memory array structure, wherein 100 to 103 are gated transistors, 110 to 111 are bit lines, word lines 108-109, 112-113 is a parasitic capacitance of the bit line, is 104 to 107 a storage capacitor. 下面以操作选通晶体管100和存储电容器104构成的存储单元为例说明传统的动态随机存储器的工作过程。 The following operation of the gate transistor 100 to the storage unit and a storage capacitor 104 composed of an example of working process of a conventional dynamic random access memory. 在写操作阶段,数据值被放在位线110上,字线108则被提升,根据数据值的不同,存储电容器118或者充电,或者放电,具体地,当数据为1时,存储电容器104充电,当数据为0时,存储电容器104放电。 During the write phase, data values ​​are placed on bit lines 110, word lines 108 were improved, depending on the data value, or the charging of the storage capacitor 118, or discharging, in particular, when the data is 1, the storage capacitor 104 is charged , when the data is 0, the storage capacitor 104 discharges. 在读操作阶段,位线110首先被预充电,当使字线108有效时,在位线电容112和存储电容器104之间放生了电荷的重新分配,这时位线上的电压发生变化,这一变化的方向决定了被存放数据的值。 In the read operation stage, first the bit line 110 is precharged, when the word line 108 effectively, the released charge redistribution capacitance between the bit lines 112 and the storage capacitor 104, when the bit line voltage is changed, this It determines the direction of change in the value of the data is stored. 1T1C结构动态随机存储器是破坏性的,这就是说存放在单元中的电荷数量在读操作期间被修改,因此完成一次读操作之后必须再恢复到它原来的值。 DRAM 1T1C structure is destructive, which means that the amount of charge stored in the cell is modified during a read operation, so after the completion of a read operation must be restored to its original value. 于是完成读操作之后紧接着就是刷新操作。 So immediately after the completion of the read operation is the refresh operation. 进行刷新操作之后才能进行下一步的读写操作。 Read and write operations to the next step after the refresh operation. 动态随机存储器属于挥发性存储器,断电时其保存的数据会消失,不适用于必须确保非易失数据绝对安全的场合,例如:网络通讯类(路由器、高端交换机、防火墙等);打印设备类(打印机、传真机、扫描仪);工业控制类(工控板、铁路/地铁信号控制系统、高压电继电器等);汽车电子类(行驶记录仪等);医疗设备(如彩超)等。 Dynamic random access memory belongs to the volatile memory, save data when power disappears, it does not apply to the need to ensure the absolute safety of non-data applications such as: network communications (routers, high-end switches, firewalls, etc.); printing device class (printers, fax machines, scanners); industrial control (IPC board, rail / Tube signal control system, high-voltage relays, etc.); automotive electronics (tachograph, etc.); a medical device (e.g., ultrasound) or the like.

发明内容 SUMMARY

[0004] 本发明的目的是提供一种半导体存储器件,能够同时具有动态存储器的功耗低,速度快的优点,又能够实现非挥发性的存储。 [0004] The object of the present invention is to provide a semiconductor memory device, while having a low power consumption can be dynamic memory, speed advantages, but also enables the non-volatile memory.

[0005] 为实现上述目的,本发明提供了如下方案: [0005] To achieve the above object, the present invention provides the following solutions:

[0006] —种半导体存储器件,包括:存储单元;每个所述存储单元包括字线、位线、阻变存储器件、选通器件和存储电容; [0006] - semiconductor memory device, comprising: a storage unit; each of said memory cells includes word lines, bit lines, resistive memory devices, gating device and a storage capacitor;

[0007] 所述阻变存储器件的一端与所述位线相连,另一端与所述选通器件的源极/漏极相连;所述选通器件的栅极与一条所述字线相连,所述选通器件的漏极/源极与另一条所述字线相连;所述存储电容的一端与所述选通器件的漏极/源极相连,另一端接地。 [0007] The barrier is connected to one end of the bit lines of the memory device, the other end of the gating device source / drain connected; is selected from the gate of the pass device is connected to a word line, the gating device is the drain / source is connected to the other word line; end of the storage capacitor and the gate of the device source / drain connected to ground.

[0008] 优选的,所述阻变存储器件的选通管包括:金属-氧化物-半导体场效应晶体管(M0SFET)和三极管。 Strobe [0008] Preferably, the resistive memory device of the tube comprising: a metal - oxide - semiconductor field effect transistor (M0SFET) and transistors.

[0009] 优选的,所述阻变存储器件包括:单极器件、双极器件和无极器件。 [0009] Preferably, the resistive memory device comprising: a monopolar device, bipolar device and polar components.

[0010] 优选的,所述阻变存储器件的阻变层材料包括:钙钛矿氧化物、过渡金属二元氧化物、固态电解质、或有机物。 [0010] Preferably, the resistive memory device of the resistive layer material comprising: a perovskite oxide, a transition metal binary oxides, solid electrolyte, or organic.

[0011] 具体的,存储器包括数个存储单元,每个存储单元位于两条字线与一条位线的交叉区。 [0011] Specifically, the memory includes a plurality of memory cells, each memory cell located at the intersection regions of both a word line and bit line. 每个存储单元包括一个阻变存储单元和一个动态存储单元,其中阻变存储单元由选通器件和一个阻变存储电阻组成,动态存储单元由选通器件和一个存储电容组成,通过两条字线的不同信号选择不同的存储方式,阻变存储单元和动态存储单元共用同一根位线。 Each memory cell comprises a resistive memory cell, and a dynamic memory cells, wherein the resistive memory cell by the gating device and a resistive switching memory resistors, dynamic memory cells by the gating device and a storage capacitor composed by two word different signal selecting line storage, resistive memory cell and a dynamic memory cells share the same bit line. 正常通电时,首先初始化所有RRAM存储单元使其变为低阻态,然后使用非挥发动态半导体存储器件的动态存储单元进行读写操作;断电前将动态存储单元的数据存入缓存,然后将缓存中的数据存入不挥发动态存储器中的阻变存储单元;恢复供电后,读出RRAM单元的数据存入缓存,然后初始化RRAM存储单元为低阻态,再将缓存中的数据写入非挥发动态半导体存储器件中的动态存储单元。 When normal power is first initialized so that all memory cells RRAM to low impedance, and dynamic memory cells using the dynamic non-volatile semiconductor memory device reads and writes; off before the dynamic data is stored in the cache storage unit, and then data stored in the cache memory is non-volatile dynamic resistive memory cell; When power returns, the read data stored in the buffer unit RRAM then initializes RRAM memory cell is low resistance state, then the data is written to the non-cache volatile dynamic semiconductor memory device of dynamic memory cells.

[0012] 根据本发明提供的具体实施例,本发明公开了以下技术效果: [0012] According to a particular embodiment of the present invention provides, the present invention discloses the following technical effects:

[0013] 本发明所公开的半导体存储器件,采用阻变存储器件,正常通电时使用不挥发动态存储器中的动态存储单元进行读写操作,断电后利用不挥发动态存储器中的阻变存储单元存储数据;同时具有动态存储器的功耗低,速度快的优点,又能够实现非挥发性的存储。 [0013] The semiconductor memory device as disclosed in the present invention, a resistive memory device, the use of non-volatile dynamic memory cell of the dynamic memory read and write operations performed when normal power, the use of non-volatile dynamic memory cell of the resistive memory after a power failure storing data; while dynamic memory with low power consumption, high speed advantages, but also enables the non-volatile memory.

附图说明 BRIEF DESCRIPTION

[0014] 为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动性的前提下,还可以根据这些附图获得其他的附图。 [0014] In order to more clearly illustrate the technical solutions in the embodiments or the prior art embodiment of the present invention, the drawings are briefly introduced as required for use in the embodiments describing the embodiments. Apparently, the accompanying drawings described below are merely Some embodiments of the invention, those of ordinary skill in the art is concerned, without any creative effort, and can obtain other drawings based on these drawings.

[0015]图1为现有技术中的动态随机存储器阵列结构图; [0015] FIG. 1 is a configuration diagram of a dynamic random memory array of the prior art;

[0016] 图2为RRAM的结构示意图; [0016] FIG. 2 is a schematic view of an RRAM;

[0017] 图3为RRAM的存储机制的原理示意图; [0017] FIG. 3 is a simplified schematic of the RRAM storage mechanism;

[0018]图4为本发明实施例所述半导体存储器件的单元结构示意图; [0018] FIG. 4 is a schematic configuration example of the semiconductor memory cell device embodiment of the invention;

[0019]图5为本发明实施例所公开的半导体存储器件的操作流程图; [0019] FIG. 5 flowchart of the operation of the semiconductor memory device of the disclosed embodiment of the invention;

[0020]图6为本发明实施例所公开的半导体存储器件的阵列示意图。 [0020] FIG. 6 is a schematic diagram of a semiconductor memory device array of the disclosed embodiment of the invention.

具体实施方式 Detailed ways

[0021] 下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。 [0021] below in conjunction with the present invention in the accompanying drawings, technical solutions of embodiments of the present invention are clearly and completely described, obviously, the described embodiments are merely part of embodiments of the present invention, but not all embodiments example. 基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。 Based on the embodiments of the present invention, all other embodiments of ordinary skill in the art without any creative effort shall fall within the scope of the present invention.

[0022] 本发明的目的是提供一种半导体存储器件,能够同时具有动态存储器的功耗低,速度快的优点,又能够实现非挥发性的存储。 [0022] The object of the present invention is to provide a semiconductor memory device, while having a low power consumption can be dynamic memory, speed advantages, but also enables the non-volatile memory.

[0023] 在众多不挥发存储器中,基于阻变材料的阻变存储器被广泛地研究。 [0023] In many non-volatile memory, widely studied on resistive resistive memory material. 阻变存储器件RRAM主要是利用某些薄膜材料在电激励的作用下会出现不同电阻状态(高、低阻态)的转变现象来进行数据的存储。 It appears different resistance state (high resistance state) transition phenomenon resistive memory device mainly by the action of certain RRAM thin film material in the electrically excited to store data. 研究发现RRAM具有写入电压低,写入擦除时间短,非破坏性读取,结构简单,所需面积小,非挥发性存储等优点,适合高密度非挥发性存储。 It found RRAM has a low writing voltage, write erase time is short, non-destructive read, simple structure, small required area, non-volatile memory, etc., for high-density non-volatile storage.

[0024] 目前RRAM的存储单元结构主要是一晶体管一RRAM(ITIR)和一二极管一RRAM(IDIR)结构。 [0024] It RRAM memory cell structure of a transistor is mainly a RRAM (ITIR) a diode and a RRAM (IDIR) structure.

[0025] 具体地结合图2和图3说明RRAM的基本结构和工作原理。 [0025] In particular in conjunction with FIGS. 2 and 3 illustrate the basic structure and working principle of the RRAM. 图2中:201为阻变层,202为选通晶体管,203为字线,204为位线;图3(13)和图3(c)分别为单极器件和双极器件的工作原理示意图,其中:205、208为SET过程,206、209为RESET过程,207为限流。 Figure 2: is a resistive layer 201, the gate of transistor 202, word line 203, bit line 204; FIG. 3 (13) and 3 (c) are diagrams showing a principle of unipolar devices and bipolar devices wherein: the process of the SET 205, 208, 206, 209 for the RESET process, 207 is a flow restrictor. 单极器件可以在单一方向的偏压下实现电阻的高低转变,而双极器件需要在不同方向的偏压下实现电阻的高低转变。 Unipolar devices can achieve low transition resistance in one direction under the bias, and the bipolar device requires low transition resistance is achieved under the bias of different directions. 具体的:写1时,施加SET电压使其转变为低阻态,写0时施加RESET电压使其转变为高阻态,读取时施加读电压(一般都很小,在0.2v左右)。 Specifically: a write, a voltage is applied so that SET into the low resistance state, a write voltage is applied RESET 0 and turn it into a high impedance state, a read voltage is applied to read (generally very small, about 0.2v).

[0026] 基于DRAM高速、低功耗的特性和RRAM的小尺寸、非挥发的特性,本发明提出一种不挥发动态半导体存储器件,其原理在于正常通电时使用不挥发动态存储器中的动态存储单元进行读写操作,断电后利用不挥发动态存储器中的阻变存储单元存储数据。 [0026] Based on characteristics of the DRAM high speed, low power consumption and small size RRAM, a non-volatile characteristic, the present invention proposes a non-volatile dynamic semiconductor memory device, using the principle that the dynamic memory is non-volatile dynamic memory when the normal power unit performs read and write operations, after a power failure by using a non-volatile resistive memory cell stores the data in the dynamic memory. 其优点在于既利用了动态存储器功耗低,速度快的优点,又实现了非挥发性的存储。 The advantage is that both the use of low-power dynamic memory, the advantages of speed, but also to achieve a non-volatile storage.

[0027] 为使本发明的上述目的、特征和优点能够更加明显易懂,下面结合附图和具体实施方式对本发明作进一步详细的说明。 [0027] For the above-described objects, features and advantages of the invention more apparent, the accompanying drawings and the following specific embodiments of the present invention will be further described in detail.

[0028] 参见图4,为本发明实施例所述半导体存储器件的单元结构示意图。 [0028] Referring to Figure 4, a schematic diagram of a memory cell structure of a semiconductor device according to the embodiment of the invention. 如图4所示,该存储器包括:字线303和305、位线304、阻变存储器件301、选通器件302和存储电容306 ; 4, the memory comprising: word lines 303 and 305, bit line 304, resistive memory devices 301, 302 gating device and a storage capacitor 306;

[0029] 所述阻变存储器件301的一端与所述位线304相连,另一端与选通器件302的源极相连;所述选通器件302的栅极与字线303相连,所述选通器件的漏极与字线305相连;所述存储电容306的一端与选通器件302的漏极相连,另一端接地。 [0029] The resistive memory device 301 connected to one end of the bit line 304, the other end of the source device 302 with the gate connected to the gate; the gate of the gating device 303 is connected to the word line 302, the gate drain of the pass device is connected to word line 305; a drain connected to one end of the gating device 302 of the storage capacitor 306, the other end grounded.

[0030] 需要说明的是,图4中的存储器的单元结构还可以是如下方式: [0030] Note that the cell structure of FIG 4 may also be a memory in the following manner:

[0031] 所述阻变存储器件301的一端与所述位线304相连,另一端与选通器件302的漏极相连;所述选通器件302的栅极与字线303相连,所述选通器件的源极与字线305相连;所述存储电容306的一端与选通器件302的源极相连,另一端接地。 [0031] The resistive memory device 301 connected to one end of the bit line 304, a drain connected to the other end 302 of the gating device; the gate of the gating device 303 is connected to the word line 302, the gate and a source connected to the word line 305 through the device; the source of the storage capacitor 306 and one end of the source gating device 302 is connected to ground. 因为从结构示意图上并无明显区别,因此没有对其进行单独附图。 Because no significant difference from the schematic structure, there is no separate figures thereof.

[0032] 本发明实施例所公开的半导体存储器件,包括若干个图4所示的存储单元。 [0032] The semiconductor memory device according to the embodiment disclosed in the present invention, includes a storage unit shown in FIG number. 与图4中的结构相同,每个存储单元位于两条字线与一条位线的交叉区;所述存储单元包括一个阻变存储单元和一个动态存储单元。 In the same FIG. 4 configuration, each memory cell located at the intersection regions of both a word line and bit line; the memory cell comprising a resistive memory cell, and a dynamic memory cells. 其中阻变存储单元由选通器件302和阻变存储器件301组成,动态存储单元由选通器件302和存储电容306组成,通过两条字线的不同信号选择不同的存储方式,阻变存储单元和动态存储单元共用同一根位线。 Wherein the resistive memory cell 302 by the gating device and a resistive memory device 301 composed of dynamic memory cells 302 by the gating device and a storage capacitor 306 composed of two different signal selecting a word line different storage, resistive memory cell and a dynamic memory cells share the same bit line.

[0033] 实际应用中,所述阻变存储器件的选通管包括:金属-氧化物-半导体场效应晶体管(M0SFET)和三极管。 [0033] In practical applications, the resistive memory device strobe tube comprising: a metal - oxide - semiconductor field effect transistor (M0SFET) and transistors.

[0034] 实际应用中,所述阻变存储器件可以包括:单极器件、双极器件和无极器件。 [0034] In practical applications, the resistive memory device may include: a monopolar device, bipolar device and polar components.

[0035] 实际应用中,所述阻变存储器件的阻变层材料可以包括:钙钛矿氧化物:如SrZr03、LiNb03、BaTi03 等;过渡金属二元氧化物:如Ni0、Ti02、Zr02、Nb205、Ta205、A1203、CoO 等;固态电解质:如Si02、TO3、Cu10.76S0.1、Ag-Ge-Se、Ag-Ge-S 等;有机物:如AIDCN、PVK、PS、PCm、F12TPN等;还有其他如:a_S1:H、μ c_Si等有类似性质的材料。 [0035] In practical applications, the resistive material layer of resistive memory device may include: a perovskite oxide: As SrZr03, LiNb03, BaTi03 like; transition metal binary oxides: as Ni0, Ti02, Zr02, Nb205 , Ta205, A1203, CoO and the like; a solid electrolyte: such as Si02, TO3, Cu10.76S0.1, Ag-Ge-Se, Ag-Ge-S and the like; organic substances: as AIDCN, PVK, PS, PCm, F12TPN the like; further there are others such as: materials properties similar H, μ c_Si like: a_S1.

[0036] 综上,本发明提出的半导体存储器件,正常通电时使用不挥发动态存储器中的动态存储单元进行读写操作,断电后利用不挥发动态存储器中的阻变存储单元存储数据;同时具有动态存储器的功耗低,速度快的优点,又能够实现非挥发性的存储。 [0036] In summary, the semiconductor memory device proposed by the present invention, when the normal power non-volatile dynamic memory cell of the dynamic memory read and write operations, after power using non-volatile resistive memory cell stores the data in the dynamic memory; while low power consumption, speed of dynamic memory has advantages, but also enables the non-volatile memory.

[0037] 需要说明的是,现有技术中有一种采用相变存储单元的不挥发动态存储器。 [0037] Incidentally, the prior art there is a phase change memory cell using a non-volatile dynamic memory. 由于本发明实施例所公开的方案中,采用阻变存储器件,阻变存储器件的存储速度比相变存储单元的存储速度快,因此与现有技术中的采用相变存储单元的不挥发动态存储器相比,本发明所公开的存储器的工作效率得到显著提高。 Since the embodiment of the present invention as disclosed embodiment, the use of resistive memory devices, the resistive memory device is faster than the speed of the memory phase change memory cell storage speed, and so the dynamic non-volatile phase change memory cell using the prior art compared to the memory, the efficiency of the disclosed invention significantly improved the memory.

[0038]图5为本发明实施例所公开的半导体存储器件的操作流程图。 [0038] FIG. 5 flowchart of the operation of the semiconductor memory device of the disclosed embodiment of the invention.

[0039]图6为本发明实施例所公开的半导体存储器件的阵列示意图。 [0039] FIG. 6 is a schematic diagram of a semiconductor memory device array of the disclosed embodiment of the invention. 其中: among them:

[0040] 500-502为位线,503-508为字线,509-517为本发明所述的非挥发性动态半导体存储器件的存储单元,518-520为位线上的寄生电容,521为行译码器,522为列译码器,523为多路选择器,524为写驱动,525为刷新电路,526为读出放大器,527为缓存,528为输入输出。 [0040] The bit lines 500-502, word lines 503-508, 509-517 Non-volatile dynamic memory cell of a semiconductor memory device according to the present invention, the parasitic capacitance of the bit lines 518-520 of 521 row decoder, column decoder 522, multiplexer 523, a write driver 524, a refresh circuit 525, sense amplifier 526, cache 527, input 528 is output.

[0041] 结合图5、图6进一步说明本发明的具体操作过程: [0041] in conjunction with FIGS. 5 and 6 further illustrate the present invention, the specific operation:

[0042] 正常通电时,首先初始化所有RRAM存储单元使其变为低阻态,具体为:利用字线WLl-WLn (504,506等)打开存储单元的选通器件,字线WLl_WLn'(503,505等)接地处理,位线BLl-BLn (501-503等)上施加RRAM单元所需的置位(SET)电压(根据不同材料和结构有所调整)使其转变为低阻态,通过行译码器521选择字线WL1' -WLn'做浮空处理。 When the [0042] normal power, first initializes all RRAM memory cells so that it becomes the low resistance state, in particular: the use of the word lines WLl-WLn (504,506, etc.) open gating device memory cell, the word line WLl_WLn '(503 , 505, etc.) grounded bit lines BLl-BLn (501-503, etc.) required for applying a RRAM cell set (sET) voltage (depending on the material and structure has been adjusted) and turn it into a low resistance state, by The row decoder 521 selects the word line WL1 '-WLn' do float process.

[0043] 然后对该非挥发动态半导体存储器件的动态存储单元进行正常的读写操作,以单元509为例,当需要写“1”时,通过行译码器选择字线WL1,施加高电平如3.3v,打开存储单元的选通器件,通过写驱动524,多路选择器523,列译码器522选择字线BL1,施加高电平,如3.3v ;当需要写“0”时,通过行译码器选择字线WL1,施加高电平打开存储单元的选通器件,通过写驱动,多路选择器,列译码器选择字线BL1,施加低电平,如Ον;读取数据时,通过行译码器选择字线WL1,施加低电平,如0ν,关闭存储单元的选通器件,通过读出放大器526,列译码器和多路选择器选择位线BL1施加预充电电压,如1.5ν,再如前述所打开该存储单元的选通器件,利用电荷分享原理读出该单元的数据,然后根据读出的数据,利用刷新电路525等再为该存储电容写入相同的值,即为刷新操作 [0043] Then the dynamic memory cells of the nonvolatile semiconductor memory device dynamic normal read and write operations, to unit 509, for example, when it is necessary to write "1", the word line WL1 selected by the row decoder, applying a high electrical flat as 3.3V, open gating device memory cell by a write driver 524, multiplexer 523, a column decoder 522 selects the word line BL1, is applied to a high level, such as 3.3V; when it is necessary to write "0" , the selected word line WL1 via the row decoder, a memory cell is applied to high open gating device, via a write driver, the multiplexer selector, column decoder selected word line BL1, a low level is applied, as Ον; read data fetch, the word line WL1 selected by the row decoder, low level is applied, such as 0ν, close gating device memory cell, sense amplifier 526, a column decoder and a multiplexer to select the bit line BL1 is applied precharge voltage, such as 1.5ν, as another example, the gating device of the memory cell is opened, the charge sharing by using the principle of the unit reads the data, and based on the read data, the refresh circuit 525 using the storage capacitor and the like for re-written the same values, i.e. the refresh operation

[0044] 当检测到需要断电时,如前所述对所有动态存储单元进行读操作,并将读出的数据存入缓存527中,然后将缓存中的数据存入该非挥发动态半导体存储器件的阻变存储单元,其中:存“0”时,通过行译码器选择WL1,施加高电平打开存储单元的选通器件,WL1'接地处理,通过写驱动,多路选择器,列译码器选择字线BL1施加RRAM单元所需的复位电压(复位电压根据不同类型的RRAM器件有所调整),存“1”时,不进行任何操作。 [0044] When detecting the need to power down, all as previously described read operation of the dynamic memory cells, and the readout data stored in the buffer 527, and stores the data in the cache memory of the non-volatile dynamic semiconductor the resistive member of the storage unit, wherein: when the stored "0", selected by the row decoder WL1, high open gating device memory cells, WL1 'process is applied to the ground, through the write drivers, multiplexers, the column decoder selects a word line BL1 reset voltage required RRAM cell (reset voltage be adjusted depending on the type of the RRAM device), save "1", no operation is performed.

[0045] 当恢复供电后,通过行译码器选择WL1,施加高电平打开存储单元的选通器件,WL1'接地处理;通过读出放大器,列译码器和多路选择器选择位线BL1位线上施加RRAM单元所需的读电压,如0.2ν,读出RRAM单元的数据存入缓存,然后如前所述初始化RRAM存储单元为低阻态,再通过行译码器选择字线WLl'-WLn'做浮空处理,然后将缓存中的数据前所述的写操作写入该非挥发动态半导体存储器件中的动态存储单元中。 [0045] When power is restored, WL1 selected by the row decoder, a memory cell is applied to high open gating device, WL1 'grounded; sense amplifier, column decoder and multiplexers selected bit line applying a read voltage required RRAM cell bit line BL1, as 0.2ν, RRAM reads data stored in the buffer unit, as described above and then initializes RRAM memory cell is low resistance state, then the selected word line by the row decoder WLl'-WLn 'do float process, and then the data in the cache before the write operation is written to the non-volatile dynamic semiconductor memory device of dynamic memory cells.

[0046] 由上述可知,在本发明的实施例中,本发明综合利用了DRAM器件的高密度、高速度、低功耗和RRAM存储器件的高密度、非挥发性、结构简单等优势,实现了一种新型的非挥发性的动态存储器件。 [0046] From the foregoing, in the embodiment of the present invention, the present invention is the utilization of high-density DRAM devices, high-density high-speed, low power consumption, and RRAM memory devices, non-volatile, and other advantages of simple structure, to achieve a new non-volatile dynamic memory device.

[0047] 本说明书中各个实施例采用递进的方式描述,每个实施例重点说明的都是与其他实施例的不同之处,各个实施例之间相同相似部分互相参见即可。 [0047] In the present specification, the various embodiments described in a progressive manner, differences from the embodiment and the other embodiments each of which emphasizes embodiment, the same or similar portions between the various embodiments refer to each other.

[0048] 本文中应用了具体个例对本发明的原理及实施方式进行了阐述,以上实施例的说明只是用于帮助理解本发明的方法及其核心思想;同时,对于本领域的一般技术人员,依据本发明的思想,在具体实施方式及应用范围上均会有改变之处。 [0048] As used herein through specific examples of the principles and embodiments of the invention are set forth in the above described embodiments are only used to help understand the method and core idea of ​​the present invention; the same time, for those of ordinary skill in the art, according to the ideas of the present invention, there are modifications to the specific embodiments and application scope. 综上所述,本说明书内容不应理解为对本发明的限制。 Therefore, the specification shall not be construed as limiting the present invention.

Claims (4)

1.一种半导体存储器件,其特征在于,包括:存储单元;每个所述存储单元包括字线、位线、阻变存储器件、选通器件和存储电容;每个所述存储单元位于两条字线与一条位线的交叉区; 所述阻变存储器件的一端与所述位线相连,另一端与所述选通器件的源极/漏极相连;所述选通器件的栅极与一条所述字线相连,所述选通器件的漏极/源极与另一条所述字线相连;所述存储电容的一端与所述选通器件的漏极/源极相连,另一端接地。 1. A semiconductor memory device, characterized by comprising: a storage unit; each of said memory cells includes word lines, bit lines, resistive memory devices, gating device and a storage capacitor; each of said memory cell is located between two intersection of word lines and a bit line; the one end of the resistive memory device coupled to the bit line, / the other end is connected to the gate of the source-drain device; gate via the gate device the word line connected to the gate of the device source / drain connected to the other word line; end of the storage capacitor and the gate of the device source / drain connected to the other end ground.
2.根据权利要求1所述的半导体存储器件,其特征在于,所述选通器件包括:金属-氧化物-半导体场效应晶体管(MOSFET)。 2. The semiconductor memory device according to claim 1, wherein said gating device comprising: a metal - oxide - semiconductor field effect transistor (MOSFET).
3.根据权利要求1所述的半导体存储器件,其特征在于,所述阻变存储器件包括:单极器件、双极器件和无极器件。 3. The semiconductor memory device according to claim 1, wherein said resistive memory device comprising: a monopolar device, bipolar device and polar components.
4.根据权利要求1所述的半导体存储器件,其特征在于,所述阻变存储器件的阻变层材料包括:钙钛矿氧化物、过渡金属二元氧化物、固态电解质、或有机物。 4. The semiconductor memory device according to claim 1, wherein said resistive material layer resistive memory device comprising: a perovskite oxide, a transition metal binary oxides, solid electrolyte, or organic.
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