JP2019021356A - Magnetic memory - Google Patents

Abstract

To provide a magnetic memory capable of improving characteristics of the memory.SOLUTION: A magnetic memory according to an embodiment includes a memory cell connected between a first wiring and a second wiring and including a selector element and a magnetoresistive effect element and a circuit to which a write voltage VWR for writing data to the memory cell. The write voltage VWR includes a first voltage VSW and a second voltage VPGM. A voltage value Va of the first voltage VSW is lower than a voltage value Vb of the second voltage VPGM, and a first period TSEL to which the first voltage VSW is applied is longer than a second period TMTJ to which the second voltage VPGM is applied. After the first voltage VSW is applied to the memory cell, the second voltage VPGM is applied to the memory cell.SELECTED DRAWING: Figure 11

Description

  Embodiments described herein relate generally to a magnetic memory.

  As an alternative memory for volatile memories such as SRAM and DRAM, a nonvolatile memory such as MRAM has attracted attention.

  In order to improve the characteristics and functions of a nonvolatile memory, research and development of various operations such as memory circuit configuration, memory cell configuration and structure, data writing, and data reading have been promoted.

Y. Shiota et Al., “Evaluation of write error rate for voltage-driven dynamic magnetization switching in magnetic tunnel junctions with perpendicular magnetization”, Applied Physics Express 9, 013001 (2016), The Japan Society of Applied Physics

  Improve memory characteristics.

  The magnetic memory of this embodiment has a first wiring, a second wiring, a first magnetoresistance effect element, and a first resistance state or a second resistance state lower than the first resistance state. And a first memory cell connected between the first wiring and the second wiring, and a write voltage for writing data to the first memory cell. And a circuit applied to the first memory cell. The write voltage includes a first voltage and a second voltage. The voltage value of the first voltage is lower than the voltage value of the second voltage, and during the first period when the first voltage is applied to the first memory cell, the second voltage is It is longer than the second period applied to the first memory cell. After the first voltage is applied to the first memory cell, the second voltage is applied to the first memory cell.

The schematic diagram for demonstrating the magnetic memory of 1st Embodiment. The schematic diagram for demonstrating the magnetic memory of 1st Embodiment. The schematic diagram for demonstrating the magnetic memory of 1st Embodiment. The schematic diagram for demonstrating the magnetic memory of 1st Embodiment. The schematic diagram for demonstrating the magnetic memory of 1st Embodiment. The schematic diagram for demonstrating the magnetic memory of 1st Embodiment. The schematic diagram for demonstrating the magnetic memory of 1st Embodiment. The schematic diagram for demonstrating the magnetic memory of 1st Embodiment. The schematic diagram for demonstrating the magnetic memory of 1st Embodiment. The schematic diagram for demonstrating the magnetic memory of 1st Embodiment. FIG. 4 is a voltage waveform diagram for explaining the magnetic memory according to the first embodiment. FIG. 2 is an equivalent circuit diagram for explaining the magnetic memory according to the first embodiment. FIG. 2 is an equivalent circuit diagram for explaining the magnetic memory according to the first embodiment. The flowchart for demonstrating the magnetic memory of 1st Embodiment. The schematic diagram for demonstrating the magnetic memory of 1st Embodiment. The timing chart for demonstrating the magnetic memory of 1st Embodiment. The schematic diagram for demonstrating the magnetic memory of 2nd Embodiment. FIG. 6 is a voltage waveform diagram for explaining a magnetic memory according to a second embodiment. The equivalent circuit diagram for demonstrating the magnetic memory of 2nd Embodiment. The equivalent circuit diagram for demonstrating the magnetic memory of 2nd Embodiment. The timing chart for demonstrating the magnetic memory of 2nd Embodiment. The figure for demonstrating the modification of the magnetic memory of 2nd Embodiment. The figure for demonstrating the modification of the magnetic memory of 2nd Embodiment. FIG. 6 is a voltage waveform diagram for explaining a magnetic memory according to a third embodiment. The equivalent circuit diagram for demonstrating the magnetic memory of 3rd Embodiment. The timing chart for demonstrating the magnetic memory of 3rd Embodiment. FIG. 6 is a voltage waveform diagram for explaining a magnetic memory according to a third embodiment. The equivalent circuit diagram for demonstrating the magnetic memory of 3rd Embodiment. FIG. 6 is a voltage waveform diagram for explaining a magnetic memory according to a third embodiment. FIG. 6 is a voltage waveform diagram for explaining a magnetic memory according to a third embodiment. FIG. 6 is a voltage waveform diagram for explaining a magnetic memory according to a third embodiment. FIG. 9 is a voltage waveform diagram for explaining a magnetic memory according to a fourth embodiment. The schematic diagram for demonstrating the magnetic memory of 4th Embodiment. The schematic diagram for demonstrating the magnetic memory of 5th Embodiment. FIG. 9 is a voltage waveform diagram for explaining a magnetic memory according to a fifth embodiment. FIG. 10 is a voltage waveform diagram for explaining a magnetic memory according to a sixth embodiment. FIG. 10 is a voltage waveform diagram for explaining a magnetic memory according to a sixth embodiment. FIG. 10 is a voltage waveform diagram for explaining a magnetic memory according to a sixth embodiment. FIG. 10 is a voltage waveform diagram for explaining a magnetic memory according to a sixth embodiment. FIG. 10 is a voltage waveform diagram for explaining a magnetic memory according to a seventh embodiment. FIG. 10 is a voltage waveform diagram for explaining a magnetic memory according to an eighth embodiment. FIG. 10 is a voltage waveform diagram for explaining a magnetic memory according to an eighth embodiment. FIG. 10 is a voltage waveform diagram for explaining a magnetic memory according to an eighth embodiment. FIG. 10 is a voltage waveform diagram for explaining a magnetic memory according to an eighth embodiment. FIG. 10 is a voltage waveform diagram for explaining a magnetic memory according to an eighth embodiment. FIG. 10 is a voltage waveform diagram for explaining a magnetic memory according to an eighth embodiment. FIG. 10 is a voltage waveform diagram for explaining a magnetic memory according to an eighth embodiment. FIG. 10 is a voltage waveform diagram for explaining a magnetic memory according to a ninth embodiment.

  The magnetic memory and the control method thereof according to the embodiment will be described with reference to FIGS. In the following description, elements having the same function and configuration are denoted by the same reference numerals. Further, in the following embodiments, components (for example, word lines WL, bit lines BL, various voltages and signals, etc.) in which numerals / alphabetical characters are added to the end of the reference numerals for distinction are not distinguished from each other. In this case, a notation in which the number / letter at the end is omitted is used.

(1) First embodiment
A magnetic memory and a control method thereof according to the first embodiment will be described with reference to FIGS.

(A) Configuration
With reference to FIGS. 1 to 4, the overall configuration of the magnetic memory of the present embodiment will be described.

  FIG. 1 is a block diagram illustrating an example of a memory system including a magnetic memory according to the present embodiment.

  As shown in FIG. 1, the memory system includes, for example, a magnetic memory 1, a memory controller 7, and a host device 9 according to the present embodiment.

A magnetic memory (memory device) 1 of this embodiment includes a magnetoresistive effect element as a memory element.
The magnetic memory 1 is directly or indirectly connected to the memory controller 7. For example, the magnetic memory 1 constitutes a storage class memory or a main memory.

The host device 9 can request various operations such as data writing (storage), data reading, and data erasing from the magnetic memory 1 via the memory controller 7.
The host device 9 is, for example, a processor.

  The memory controller 7 is directly or indirectly coupled to the host device 9 via connection terminals, connectors, or cables.

  The memory controller 7 can control the operation of the magnetic memory 1. The memory controller 7 includes a buffer memory and an ECC circuit.

The memory controller 7 generates a command based on a request from the host device 9. The memory controller 7 transmits the generated command to the magnetic memory 1.
The magnetic memory 1 executes an operation corresponding to the command from the memory controller 7.

  For example, when the request from the host device 9 is a data write, the memory controller 7 transmits a write command to the memory device. The memory controller 7 transmits an address of a memory cell to be selected, data to be written to the memory cell, and a control signal together with a write command. The magnetic memory 1 writes data to be written to a selected address based on a write command and a control signal.

  For example, when the request from the host device 9 is to read data, the memory controller 7 transmits a read command to the memory device. The memory controller 7 transmits the address of the memory cell to be selected and a control signal together with the read command. The magnetic memory 1 reads data from the selected address based on the read command and the control signal. The magnetic memory 1 transmits the read data to the memory controller 7. The memory controller 7 receives data from the magnetic memory 1. The memory controller 5 transmits data from the magnetic memory 1 to the host device.

  Thus, the magnetic memory 1 executes a predetermined operation in the memory system.

  Hereinafter, at least one of the memory controller 7 and the host device 9 is called an external device.

  The magnetic memory 1 of this embodiment may be a memory in the memory controller 7 or the host device 9. In this case, the magnetic memory 1 is controlled by the CPU in the memory controller 7 or the CPU (or controller) in the host device 9. In the present embodiment, the memory controller 7 may be formed in the host device 9.

  FIG. 2 is a block diagram showing the internal configuration of the magnetic memory of this embodiment.

  As shown in FIG. 2, the magnetic memory of this embodiment includes a memory cell array 10, a column control circuit 11, a row control circuit 12, first and second write circuits 13A and 13B, and first and second read circuits. 14A and 14B, a decode circuit 15, an I / O circuit 16, a voltage generation circuit 17, a control circuit 18, and the like.

  The memory cell array 10 includes at least a plurality of bit lines BL, a plurality of word lines WL, and a plurality of memory cells MC.

  The plurality of memory cells MC are arranged in a matrix in the memory cell array 10.

  One memory cell MC is connected between one word line WL and one bit line BL.

  The column control circuit 11 controls a column (for example, bit line BL) of the memory cell array 10. A signal CS is supplied to the column control circuit 11. For example, the column control circuit 11 sets one bit line among the plurality of bit lines BL to a selected state based on the signal CS. Hereinafter, the bit line set to the selected state is referred to as a selected bit line. Bit lines other than the selected bit line are called non-selected bit lines.

  The row control circuit 12 controls a row (for example, a word line WL) of the memory cell array 10. A signal RS is supplied to the row control circuit 12. For example, the row control circuit 12 sets one word line among the plurality of word lines WL to a selected state based on the signal RS. Hereinafter, the word line set to the selected state is referred to as a selected word line. Word lines other than the selected word line are called unselected word lines.

  The first and second write circuits (also called a write control circuit or a write driver) 13A and 13B perform various controls for a write operation (data write).

  The first write circuit 13A is provided on the column side of the memory cell array 10, and the second write circuit 13B is provided on the row side of the memory cell array 10. In the following, the first write circuit 13A is referred to as a column side write circuit 13A, and the second write circuit 13B is referred to as a row side write circuit 13B.

  The column side write circuit 13A applies a voltage for a write operation to the selected bit line. The row side write circuit 13B applies a certain voltage for the write operation to the selected word line.

  For example, the write circuits 13A and 13B include a voltage source (or current source), a latch circuit, and the like.

  The first and second readout circuits (also called readout control circuits or readout drivers) 14A and 14B perform various controls for the readout operation (data readout).

  The first read circuit 14A is provided on the column side of the memory cell array 10, and the second read circuit 14B is provided on the row side of the memory cell array 10. Hereinafter, the first readout circuit 14A is referred to as a column side readout circuit 14A, and the second readout circuit 14B is referred to as a row side readout circuit 14B.

  The column side read circuit 14A applies a certain voltage for the read operation to the selected bit line. The row side read circuit 14B applies a certain voltage for the read operation to the selected word line.

  For example, the read circuits 14A and 14B include a voltage source (or current source), a latch circuit, a sense amplifier circuit, and the like.

  Note that the write circuits 13A and 13B and the read circuits 14A and 14B are not limited to circuits independent of each other. For example, the writing circuit and the reading circuit may have common components that can be used with each other, and may be provided as one integrated circuit.

  The decode circuit 15 decodes an address signal provided from, for example, an external device (memory controller or host device). The decode circuit 15 outputs the decoding result of the address signal to the column control circuit 11 and the row control circuit 12.

  The address signal (for example, physical address) includes a column address to be selected and a row address to be selected. For example, the column address decoding result corresponds to the signal CS, and the row address decoding result corresponds to the signal RS.

  The I / O circuit (input / output circuit) 16 is an interface circuit for transmitting and receiving data in the magnetic memory 1. During the write operation, the I / O circuit 16 transfers data from the external device to the write circuits 13A and 13B as write data. During the read operation, the I / O circuit 16 transfers the data output from the memory cell array 10 to the read circuit 14A as read data to an external device.

  The voltage generation circuit 17 generates voltages for various operations of the memory cell array 10 using a power supply voltage provided from an external device.

  The voltage generation circuit 17 outputs various voltages generated for the write operation to the column side and row side write circuits 13A and 13B during the write operation. The voltage generation circuit 17 outputs various voltages generated for the read operation to the column side and row side read circuits 14A and 14B during the read operation.

  A control circuit (also called a state machine or an internal controller) 18 controls the operation of each circuit in the magnetic memory 1 based on a control signal and a command. For example, the command is provided to the magnetic memory 1 from an external device. The control signal is transmitted and received between the magnetic memory 1 and the outside nicely.

  For example, the command CMD is a signal indicating an operation to be executed by the magnetic memory 1. For example, the control signal CNT is a signal for controlling the operation timing between the external devices 7 and 9 and the magnetic memory 1 and the operation timing inside the magnetic memory.

  The magnetic memory of this embodiment is, for example, a cross point type MRAM. In the magnetic memory of this embodiment, the memory cell array 10 has a cross-point structure.

(A-1) Memory cell array
The internal configuration of the memory cell array of the MRAM of this embodiment will be described with reference to FIGS.

<Configuration>
The configuration of the memory cell array of the MRAM according to the present embodiment will be described with reference to FIGS.

  FIG. 3 is an equivalent circuit diagram showing an example of the internal configuration of the memory cell array of the MRAM of this embodiment.

  As shown in FIG. 3, the plurality of word lines WL are arranged in the Y direction. Each word line WL extends in the X direction. The plurality of bit lines BL are arranged in the X direction. Each bit line BL extends in the Y direction.

  Memory cell MC is arranged at the intersection of bit line BL and word line WL. One end of the memory cell MC is connected to the bit line BL, and the other end of the memory cell MC is connected to the word line WL.

  A plurality of memory cells MC arranged in the X direction are commonly connected to one word line WL. The plurality of memory cells MC arranged in the Y direction are commonly connected to one bit line BL.

  One memory cell MC includes one magnetoresistive element 100 and one selector element 200. The magnetoresistive effect element 100 functions as a memory element of the memory cell MC. The selector element 200 functions as a selection element for the memory cell MC.

In the memory cell MC, the magnetoresistive effect element 100 and the selector element 200 are connected in series between the bit line BL and the word line WL.
In the example of FIG. 3, one end of the magnetoresistive effect element 100 is connected to the bit line BL, the other end of the magnetoresistive effect element 100 is connected to one end of the selector element 200, and the other end of the selector element 200 is connected to the word line. Connected to line WL.

  In the internal configuration of the memory cell MC, the magnetoresistive effect element 100 may be provided on the word line side, and the selector element 200 may be provided on the bit line side.

<Memory cell>
FIG. 4 shows an example of the structure of the memory cell in the cross point type memory cell array.
In FIG. 4, a schematic cross-sectional view along the Y direction of one memory cell is shown. In FIG. 4, illustration of an insulating layer covering the memory cell MC and the wirings BL and WL is omitted.

  The bit line BL and the word line WL are stacked in a direction perpendicular to the surface of the substrate 300 (Z direction). For example, the bit line BL is disposed above the word line WL. The bit line BL and the word line WL are conductive layers (for example, metal films).

  For example, the substrate 300 is an insulating layer disposed on a semiconductor substrate (not shown). Elements (for example, a field effect transistor, a resistance element, a capacitor element, and the like) for configuring each circuit 11 to 18 in the magnetic memory 1 may be disposed on a semiconductor substrate below the substrate 300.

  The memory cell MC is provided between the bit line BL and the word line WL.

  For example, the magnetoresistive effect element 100 is provided above the selector element 200. For example, the conductive layer 390 may be provided between the magnetoresistive effect element 100 and the selector element 200. Note that a conductive layer may be provided between the bit line BL and the magnetoresistive effect element 100 or between the word line WL and the selector element.

When the memory cell array 10 has a cross-point structure, the area of the 1-bit memory cell MC is about 4F ² (F: half pitch). Thus, the cross-point type memory cell array 10 has a structure that is advantageous for increasing the storage capacity of the memory. As a result, the storage density of the magnetic memory can be improved.

  Note that the word line WL may be disposed below the bit line BL in a direction perpendicular to the surface of the substrate 300. In this case, the selector element 200 is stacked above the magnetoresistive effect element 100. A plurality of memory cells MC may be stacked in the Z direction.

<Magnetoresistance effect element>
The configuration of the magnetoresistive effect element in the memory cell of the MRAM of this embodiment will be described with reference to FIGS.

  FIG. 5 is a schematic cross-sectional view for explaining the configuration of the magnetoresistive effect element in the memory cell of the MRAM of this embodiment.

  As shown in FIG. 5, the magnetoresistive effect element 100 includes at least two magnetic layers 101 and 102 and a nonmagnetic layer 103 between the magnetic layers 101 and 102.

  For example, the magnetic layers 101 and 102 and the nonmagnetic layer 103 form a magnetic tunnel junction. Thereby, the magnetoresistive effect element 100 has a magnetic tunnel junction. In the present embodiment, the magnetoresistive element 100 having a magnetic tunnel junction is called an MTJ element 100. The nonmagnetic layer 103 in the MTJ element is called a tunnel barrier layer. The tunnel barrier layer 103 is an insulating film containing, for example, MgO.

  The magnetic layer 101 has a variable magnetization direction, and the magnetic layer 102 has a fixed magnetization direction (fixed state or fixed state).

In this embodiment, the magnetic layer 101 whose magnetization direction is variable is called a storage layer (or free layer) 101, and the magnetic layer 102 whose magnetization direction is invariant is a reference layer (or a fixed layer or a pinned layer). ) 102.
The magnetization direction does not change when the voltage or current for reversing (changing) the magnetization direction of the storage layer 101 is supplied to the magnetoresistive effect element 100. Means. The voltage value or current value at which the magnetization direction of the magnetic layer is reversed is called a magnetization reversal threshold value.

  The magnetization reversal threshold value of the reference layer 102 is set to a value higher than the magnetization reversal threshold value of the storage layer 101. Accordingly, even if a voltage or current about the magnetization reversal threshold value of the storage layer 101 is supplied to the magnetoresistive element 100 in order to reverse the magnetization direction of the storage layer 101, the magnetization direction of the reference layer 102 Does not invert.

  The magnetic layer 104 may be provided on the reference layer 102 with the spacer layer 103 interposed therebetween.

  The magnetic layer 104 is also referred to as a shift cancel layer 104. The shift cancel layer 104 is a magnetic layer for reducing the leakage magnetic field of the reference layer 102. The direction of magnetization of the shift cancel layer 104 is opposite to the direction of magnetization of the reference layer 102. Thereby, an adverse effect (for example, magnetic field shift) on the magnetization of the storage layer 101 due to the leakage magnetic field of the reference layer 102 is suppressed.

  The magnetization direction of the reference layer 102 and the magnetization direction of the shift cancellation layer 104 are set to opposite directions by a SAF (synthetic antiferromagnetic) structure.

  In the SAF structure, the reference layer 102 and the shift cancel layer 104 are antiferromagnetically coupled by the spacer layer 105 between the reference layer 102 and the shift cancel layer 104.

  The spacer layer 105 is a nonmagnetic metal film such as ruthenium (Ru), for example. For example, when Ru is used for the spacer layer 105, the antiferromagnetic coupling force in the reference layer 102 and the shift cancel layer 104 can be increased by adjusting the thickness of the spacer layer 105. Thereby, the magnetization direction of the reference layer 102 and the magnetization direction of the shift cancel layer 104 are automatically stabilized in an antiparallel state.

Note that the magnetization directions of the reference layer 102 and the shift cancel layer 104 only need to be antiparallel to each other, and are not limited to the directions shown in FIG.
The stacked body (SAF structure) including the magnetic layers 102 and 104 and the spacer layer 105 may be called a reference layer as a whole.

  The resistance value (magnetic resistance value) of the MTJ element 100 changes according to the relative relationship (magnetization arrangement) between the magnetization direction of the storage layer 101 and the magnetization direction of the reference layer 102.

  FIG. 6 is a schematic diagram for explaining the magnetization arrangement state (resistance state) of the magnetoresistive effect element used in the memory cell of the MRAM of this embodiment.

  FIG. 6A shows a case where the magnetization arrangement of the MTJ element is in a parallel arrangement state (when the resistance state of the MTJ element is a low resistance state). In the present embodiment, with respect to the state of the magnetization arrangement of the MTJ element, the parallel arrangement state is expressed as a P state.

  As shown in FIG. 6A, when the magnetization direction of the storage layer 101 is the same as the magnetization direction of the reference layer 102, the MTJ element 100 has the first resistance value R1.

  FIG. 6B shows a case where the MTJ element is in an antiparallel arrangement state and the MTJ element is in a high resistance state. In the present embodiment, with respect to the state of the magnetization arrangement of the MTJ element, the antiparallel arrangement state is expressed as an AP state.

  As shown in FIG. 6B, when the magnetization direction of the storage layer 101 is opposite to the magnetization direction of the reference layer 102, the MTJ element 100 has the second resistance value R2. The second resistance value is higher than the first resistance value.

  Data (information) is stored in the MTJ element 100 using the fact that the MTJ element 100 has different resistance values depending on the magnetization arrangement state. For example, the MTJ element having the first resistance value or the second resistance value stores 1-bit (“0” or “1”) data.

  For example, when the resistance value of the MTJ element 100 is set to the first resistance value R1, the MTJ element (MTJ element in the P state (low resistance state)) 100 has first data (for example, “0” data). ) Is memorized. When the resistance value of the MTJ element 100 is set to the second resistance value R2, the MTJ element (the MTJ element in the AP state (high resistance state)) 100 receives the second data (for example, “1” data). Remember.

  The MTJ element 100 can store data of 2 bits or more by controlling the element structure (for example, the number of storage layers) or the magnetization of the magnetic layer.

<Selector element>
The configuration of the selector element in the memory cell of the MRAM according to this embodiment will be described with reference to FIGS.

  FIG. 7 is a schematic cross-sectional view for explaining the configuration of the selector element in the memory cell of the MRAM of this embodiment.

  As shown in FIG. 7, the selector element 200 includes, for example, at least two electrodes 210 and 220 and an intermediate layer 230 between the two electrodes 210 and 220.

  The electrodes 210 and 220 are, for example, metal films. The intermediate layer 230 is an insulating film (for example, an oxide film) or a semiconductor film (for example, a silicon film). The intermediate layer 230 may be a stacked film including one or more insulating films and one or more semiconductor films.

  The resistance state of the selector element 200 has a low resistance state or a high resistance state depending on whether a voltage is applied.

When no voltage is applied to the selector element 200, the selector element 200 is in a high resistance state.
By applying a voltage between the electrodes 210 and 220 of the selector element 200 in a predetermined period, the resistance state of the selector element 200 is set to a low resistance state.

  The selector element 200 in the low resistance state has a resistance value R3, and the selector element 200 in the high resistance state has a resistance value R4 (R4> R3).

  In the present embodiment, the high resistance state of the selector element 200 corresponds to the off state of the selector element 200, and the low resistance state of the selector element 200 corresponds to the on state of the selector element 200.

  By setting the selector element 200 to the on state, the memory cell MC is set to the selected state.

  Using FIG. 8, an example of the mechanism of the on / off switch (change in resistance state) of the selector element 200 is considered as follows.

  FIG. 8 is a schematic diagram for explaining the resistance state (on / off state) of the selector element used in the memory cell of the MRAM of this embodiment.

  FIG. 8A is a schematic diagram for explaining a case where the resistance state of the selector element 200 is a low resistance state.

  By applying a voltage, a certain amount of current is generated in the selector element 200. Due to the generated current, the metal of the electrode 210 conducts ions in the intermediate layer 230.

  As a result, a conductive path (conductive filament) 290 caused by metal ions is formed in the intermediate layer 230 as shown in FIG. For example, one electrode 210 is electrically connected to the other electrode 220 through the conduction path 290. Note that the conduction path 290 may not be in complete contact with the electrodes 210 and 220.

  Thus, by forming a conduction path that connects the two electrodes 210 and 220, the resistance state of the selector element 200 becomes a low resistance state. When the resistance state of the selector element 200 becomes a low resistance state, the selector element 200 is turned on.

  FIG. 8B is a schematic diagram for explaining a case where the resistance state of the selector element 200 is a high resistance state.

  When no voltage is applied to the selector element 200 or the current generated in the selector element 200 is small, no conduction path is formed in the intermediate layer 230.

  As shown in FIG. 8B, the state in which the conduction path connecting the two electrodes 210 and 220 is not formed in the intermediate layer 230 corresponds to the high resistance state of the selector element 200.

  As shown in FIG. 8B, the high resistance state of the selector element 200 is that the conduction path 299 is partially formed in the intermediate layer 230 without connecting the two electrodes 210 and 220. May also include a state.

  As a trend, the time for forming the metal conduction path in the intermediate layer 230 of the selector element 200 is sufficiently longer than the period of precession of electrons (magnetization) in the memory layer 101 of the MTJ element. Therefore, compared to the time for the magnetization reversal of the MTJ element 100, the on / off transition time of the selector element 200 (the time for transition from the off state to the on state or the time for transition from the on state to the off state) ) Is very long.

  The resistance value R3 of the selector element 200 in the low resistance state is smaller than the resistance value R1 of the MTJ element 100 in the low resistance state. For example, the resistance value R3 of the selector element 200 in the low resistance state is a value within a range of 1/10 to 1/1000 of the resistance value of the MTJ element 100 in the low resistance state.

  The resistance value R4 of the selector element 200 in the high resistance state is higher than the resistance value R2 of the MTJ element 100 in the high resistance state. For example, the resistance value R4 of the selector element 200 in the high resistance state is a value in the range of 10 to 1000 times the resistance value R2 of the MTJ element 200 in the high resistance state.

(B) Basic operation
With reference to FIGS. 9 to 11, the basic operation of the cross-point type MRAM of this embodiment will be described.

<Basic operation of magnetoresistive element>
FIG. 9 is a diagram for explaining a basic operation example of a magnetoresistive element (MTJ element) in the MRAM of the present embodiment.

  In the MRAM of the present embodiment, data writing to the MTJ element (reversal of magnetization of the storage layer) is performed using the voltage effect of the MTJ element.

  FIG. 9A is a schematic diagram illustrating an example of a voltage application state to the MTJ element during a write operation.

  As shown in FIG. 9A, in the write operation using the voltage effect, the magnetization arrangement of the MTJ element 100 is changed to an antiparallel arrangement state or a parallel arrangement by applying a voltage (write voltage) VWR to the MTJ element 100. Set to state. Hereinafter, the method (write operation) for writing data to the MTJ element 100 using the voltage effect is referred to as voltage write. In the present embodiment, the MRAM in which the voltage effect is used for data writing is called a voltage writing type MRAM (or voltage torque type MRAM). An MTJ element in which the magnetization of the memory layer 101 is reversed by a voltage effect during data writing (writing operation) is called a voltage effect type MTJ element.

  In order to reverse the magnetization direction of the storage layer 101 of the MTJ element 100, a write voltage from the voltage source 900 is applied to the MTJ element 100. A voltage value of a certain period included in the write voltage (hereinafter also referred to as a magnetization reversal voltage or a program voltage) is equal to or higher than the magnetization reversal threshold value of the storage layer 101 and is greater than the magnetization reversal threshold value of the reference layer 102 small.

  When a program voltage is applied to the MTJ element 100, the reference layer 102 side is set to a high potential, and the storage layer 101 side is set to a low potential side.

  For example, in this embodiment, as shown in FIG. 9A, when a voltage is applied to the MTJ element 100, the voltage application state in which the reference layer side is set to a high potential and the storage layer side is set to a low potential is positive. It is called a bias state.

  As described below, in the MRAM of this embodiment, the voltage effect type MTJ element 100 is executed by mainly controlling the pulse width of the program voltage.

  FIG. 9B is a diagram schematically showing the magnetization movement of the magnetic layer due to the voltage effect. The magnitude of magnetization of the magnetic layer is constant. Therefore, the trajectory of the precessing magnetization follows a spherical surface as shown in FIG.

  As shown in FIG. 9B, the magnetic layer (memory layer) 110 has a magnetization Zi set in a certain direction (hereinafter referred to as an initial state magnetization) Zi before the voltage is applied to the MTJ element 100. Have For example, the orientation of the magnetization Zi in the initial state of the storage layer 101 is stable in the direction perpendicular to the layer surface of the storage layer 101 (the stacking direction of the storage layer and the reference layer).

  When a program voltage is applied to the MTJ element 100, the movement of magnetization of the storage layer 101 is excited by reducing the magnetic anisotropy energy of the storage layer 101. As a result, the magnetization Zi in the initial state of the storage layer 101 starts precession around the external magnetic field Hext.

  At the timing when the application of the program voltage is stopped, the precession of the magnetization Zx of the storage layer stops and stabilizes in the vertical direction.

The period from the start of application of the program voltage to the stop of application substantially corresponds to the pulse width of the program voltage.
Here, the pulse width of the program voltage (program voltage application period) is set to about half the period of the precession of magnetization of the storage layer 101 (period in which the magnetization rotates 180 °). As a result, the magnetization of the storage layer 101 stops in the direction perpendicular to the layer surface while the magnetization of the storage layer 101 is reversed.

  As described above, the MRAM of this embodiment can reverse (switch) the magnetization direction of the storage layer by controlling the pulse width of the program voltage.

  FIG. 9C is a graph showing an example of the relationship between the pulse width of the applied voltage to the MTJ element and the switch probability (magnetization inversion probability of the storage layer) of the MTJ element. The horizontal axis of the graph of FIG. 9C corresponds to the pulse width of the applied voltage. The vertical axis of (c) in FIG. 9 corresponds to the switch probability of the MTJ element. The switching probability of the MTJ element has substantially the same meaning as the switching probability of the magnetization direction of the storage layer of the MTJ element.

  As shown in FIG. 9C, the switching probability of the MTJ element behaves so as to oscillate (increase and decrease) periodically with respect to the pulse width of the applied voltage (program voltage). As shown in FIG. 9C, the switch probability decreases as the pulse width (application time) of the applied voltage increases.

  As described above, in writing data to the MTJ element 100, the precession of the magnetization of the storage layer 101 is applied so that the magnetization direction of the storage layer 101 stops at a timing rotated by 180 ° from the initial state. The voltage pulse width is set.

  Based on the example of FIG. 9C, the pulse width of the applied voltage is set to the pulse width Tz in order to realize the magnetization reversal of the storage layer 101 with high probability. For example, the pulse width Tz of the applied voltage is set in the range of about 0.5 nanoseconds to 1.0 nanoseconds. The pulse width Tz is appropriately set based on experimental results and simulation results for the MTJ element.

  When the switching of the MTJ element 100 is executed by controlling the pulse width of the applied voltage, the pulse width of the voltage for switching the magnetization arrangement state of the MTJ element 100 from the P state to the AP state is the magnetization arrangement of the MTJ element 100. The state is substantially the same as the pulse width of the voltage for switching from the AP state to the P state.

  The polarity of the voltage for switching the magnetization arrangement state of the MTJ element from the P state to the AP state is the same as the polarity of the voltage for switching the magnetization arrangement state of the MTJ element from the AP state to the P state. .

  Thus, in the voltage writing type MRAM, the data to be written does not depend on the polarity of the voltage applied to the MTJ element 100. The voltage effect type MTJ element is a unipolar memory element for data writing.

  Therefore, for example, in the data write sequence, it is desirable that an operation (for example, a read operation) for determining the current data holding state (magnetization arrangement state) of the MTJ element is performed before the write operation. . In the present embodiment, the read operation before writing data in the write sequence is called pre-read or internal read.

  The magnetic characteristics of the magnetic layers 101 and 102 are designed so that the inversion threshold value of the reference layer 102 related to the voltage value is higher than the inversion threshold value of the storage layer 101 related to the voltage value. Therefore, even if the write voltage (program voltage) VWR is applied to the MTJ element 100, the magnetization of the reference layer 102 is not reversed.

<Basic operation of selector element>
FIG. 10 is a diagram illustrating an example of the current-voltage characteristic (IV characteristic) of the selector element in the MRAM according to the present embodiment. In FIG. 10, the horizontal axis of the graph corresponds to the voltage applied to the selector element. In FIG. 10, the vertical axis (log scale) of the graph corresponds to the current flowing through the selector element.

  When no voltage is applied to the selector element 200, the selector element 200 is in a high resistance state.

  As shown in FIG. 10, when the voltage applied to the selector element 200 in the high resistance state is a positive voltage, the current flowing in the selector element 200 is steep when the voltage value V2 of the positive applied voltage is reached. Has increased. This increase in current indicates a decrease in the resistance value of the selector element 200.

  Since the conduction path resulting from the metal of the electrodes 210 and 220 is formed in the intermediate layer 230 with the voltage value V2 as a threshold value (the two electrodes 210 and 220 are electrically connected), the resistance of the selector element 200 The state becomes a low resistance state.

  Thus, when the voltage value of the applied voltage reaches a certain value, the selector element 200 changes from the high resistance state to the low resistance state. As a result, the selector element 200 is set to an on state. Hereinafter, the voltage value at which the resistance state of the selector element 200 switches from the high resistance state to the low resistance state (voltage value at which the selector element 200 is turned on) is referred to as an on voltage.

  The voltage value of the applied voltage is decreased from the voltage value V2. When the voltage value of the applied voltage reaches the voltage value V1 from the voltage value V2, the current flowing in the selector element 200 decreases sharply. This decrease in current indicates an increase in the resistance value of the selector element 200.

  When the voltage value of the applied voltage is smaller than the ON voltage, the ionic conduction of the metal is suppressed and the conduction path disappears (or the conduction path becomes shorter), so that the resistance state of the selector element 200 is changed from the low resistance state to the high resistance state. Change to state.

  As described above, when the voltage value of the applied voltage is lower than the ON voltage (voltage value V2), the resistance state of the selector element 200 changes from the low resistance state to the high resistance state. As a result, the selector element 200 is set to an off state.

  Hereinafter, the voltage value at which the resistance state of the selector element 200 is switched from the resistance state to the high resistance state (voltage value at which the selector element 200 is turned off) is referred to as an off voltage.

When the applied voltage to the selector element 200 in the high resistance state is a negative voltage, when the voltage value of the negative applied voltage reaches a certain voltage value −V4, the current flowing in the selector element 200 increases. . This increase in current indicates a decrease in the resistance value of the selector element 200.
In this way, the selector element 200 changes from the high resistance state to the low resistance state by the application of the negative voltage. As a result, the selector element 200 is set to an on state.

The voltage value of the applied voltage is increased from the voltage value −V4 toward the voltage value −V3. When the voltage value of the applied voltage reaches the voltage value −V3, the current flowing in the selector element 200 decreases. This decrease in current indicates an increase in the resistance value of the selector element 200.
Thus, the resistance state of the selector element 200 changes from the low resistance state to the high resistance state by application of a negative voltage. As a result, the selector element is set to an off state.

  Thus, the selector element 200 has an on-voltage and an off-voltage in the negative voltage region as well as the positive voltage. The selector element 200 is a bipolar switch element.

  As described above, the selector element 200 can control ON / OFF by controlling the applied voltage value.

  The configuration of the selector element 200 (or the MTJ element 100) is designed so that the voltage value V2 (or the absolute value of the voltage value −V4) is smaller than the magnetization reversal threshold value of the MTJ element 100.

  Note that the current value of the current flowing through the selector element 200 when a voltage is applied is preferably set to be equal to or less than a certain current value Iz. Thereby, destruction of the selector element 200 is prevented. A current having a certain current value (or the current value itself) Iz is called a limiting current Iz. The limit current Iz indicates a current (current value) that may destroy the selector element.

  Regarding the on / off voltage of the selector element, the absolute value of the negative voltage value −V4 may be substantially the same as or different from the absolute value of the positive voltage value V2. Similarly, the absolute value of the negative voltage value −V3 may be substantially the same as or different from the absolute value of the positive voltage value V1.

<Pulse shape of write voltage>
FIG. 11 shows a pulse waveform of a voltage used for the operation of the cross point type MRAM of this embodiment. The voltage in FIG. 11 is a write voltage used for the write operation of the cross-point type MRAM of this embodiment.

  FIG. 11A shows a voltage waveform (relationship between voltage value and time) of the write voltage (potential difference between terminals of the memory cell) VWR applied to the memory cell. FIG. 11B shows a voltage waveform of a voltage (potential difference between the terminals of the selector element) VSEL applied to the selector element when a write voltage is applied to the memory cell. FIG. 11C shows a voltage waveform of a voltage (potential difference between terminals of the MTJ element) VMJ applied to the MTJ element when a write voltage is applied to the memory cell.

  As shown in FIG. 11A, the write voltage VWR has a stepped pulse waveform.

  In the first period TSEL of the pulse waveform of the write voltage VWR, the first voltage value Va is applied to the memory cell MC, and in the second period TMTJ after the first period TSEL, from the first voltage value Va. A high second voltage value Vb is applied to the memory cell MC. The first period TSEL is longer than the second period TMTJ.

  The first voltage value Va is a voltage value for switching the selector element 200 in the memory cell MC to an on state (setting the selector element 200 to a low resistance state).

  The second voltage value Vb is a voltage value for switching the MTJ element 100 in the memory cell MC (reversing the magnetization of the storage layer).

  In the present embodiment, for clarification of the description, the portion having the voltage value Va for switching the selector element 200 in the write voltage VWR is also referred to as a switch voltage VSW. The portion of the write voltage VWR having the voltage value Vb for changing the resistance state of the memory element (in this case, reversing the magnetization direction of the memory layer of the MTJ element) is also referred to as a program voltage (or magnetization reversal voltage) VPGM. It is released.

  In the present embodiment, for the sake of clarity, the period TSEL is also called a switch period, and the period TMTJ is also called a program period.

In the present embodiment, the voltage value of the switch voltage VSW of the selector element 200 is lower than the voltage value (magnetization reversal threshold) of the program voltage VPGM of the MTJ element 100. The resistance state of the selector element 200 is a voltage value lower than the voltage value for changing the resistance state of the MTJ element 100 and changes from the high resistance state to the low resistance state.
Further, as described above, the period during which the selector element 200 changes from the off state to the on state (or from the on state to the off state) is longer than the magnetization reversal period of the storage layer 101 of the MTJ element 100.

  The write voltage VWR is divided and applied to the selector element 200 and the MTJ element 100, respectively. The divided voltages VSEL and VMTJ are applied to the selector element 200 and the MTJ element 100 so as to have voltage values corresponding to the resistance value of the selector element 200 and the resistance value of the MTJ element 100, respectively.

  In the present embodiment, the selector element 200 is set to the off state at the start of application of the write voltage (for example, time t1). Therefore, the resistance value of the off-state selector element 200 is higher than the resistance value of the MTJ element 100 at time t1.

  Therefore, as shown in FIGS. 11B and 11C, most of the write voltage VWR is applied to the selector element 200 during the period from time t1 to time tx in the period TSEL. For example, the applied voltage VSEL to the selector element 200 has a voltage value Va.

  In the period TSEL, the voltage VMTJ applied to the MTJ element 100 is smaller than the voltage applied to the selector element 200. For example, in the period TSEL, almost no voltage is applied to the MTJ element, and the applied voltage VMTJ to the MTJ element is substantially zero.

  A voltage value greater than zero may be applied to the MTJ element 100 depending on the resistance ratio between the selector element 200 and the MTJ element 100. In this case, the MTJ element 100 and the selector element 200 have a voltage value that is sufficiently smaller than the voltage applied to the selector element 200 and smaller than the magnetization reversal threshold value of the MTJ element 100. It is desirable to be designed.

When a certain period elapses from the start of application of the write voltage, for example, at time tx, the selector element 200 switches from the off state (high resistance state) to the on state (low resistance state). As a result, the resistance value of the selector element 200 in the on state is lower than the resistance value of the MTJ element 100.
As a result, the voltage value of the voltage VSEL applied to the selector element 200 decreases, and the voltage value of the voltage VMTJ applied to the MTJ element 100 increases. At time tx, the voltage value of the voltage VSEL is lower than the voltage value of the voltage VMTJ.

  Here, since the voltage value of the write voltage in the period TSEL is smaller than the magnetization reversal threshold value of the MTJ element, even if the voltage VMJ applied to the MTJ element 100 increases at time tx, the magnetization reversal of the MTJ element 100 is performed. Does not occur.

  After time tx, at time t2, the voltage value of the write voltage VWR is increased from the voltage value Va to the voltage value Vb. Along with this, the voltage value of the applied voltage VMTJ of the MTJ element 100 also increases.

As a result, the voltage value of the applied voltage VMTJ of the MTJ element 100 becomes equal to or higher than the magnetization reversal threshold value of the storage layer 101. Therefore, the magnetization of the storage layer 101 starts precession and rotation of the magnetization of the storage layer 101 occurs.
At time t3, the voltage value of the write voltage VWR is decreased from the voltage value Vb to the voltage value Va. As a result, the precession of magnetization of the storage layer 101 stops.

The voltage value Vb is applied to the memory cell MC during the period TMTJ from time t2 to time t3. In the MRAM of this embodiment, the period TMTJ in which the voltage value Vb is applied is set to a length corresponding to the half cycle of the magnetization precession of the storage layer 101.
Therefore, in the period TMTJ (for example, time t3), the magnetization of the storage layer 101 is reversed. As a result, data is written into the memory cell MC.

  Here, when the switching time (time tx) of the selector element 200 varies, the timing of starting the application of a voltage equal to or higher than the magnetization reversal threshold value to the MTJ element 100 may vary.

  In the present embodiment, in the period TSEL, the magnitude of the voltage value of the write voltage VWR is smaller than the program voltage (magnetization reversal threshold) of the MTJ element 100, so that even if the selector element 200 is turned on, the storage layer 101 Does not start precession, and the initial state of the MTJ element 100 is maintained.

  In the present embodiment, when the voltage value of the write voltage VWR increases from the voltage value Va to the voltage value Vb at the timing of transition from the period TSEL to the period TMTJ (for example, time t2), the magnetization of the storage layer 101 precesses. To start. Accordingly, the program operation of the MTJ element 100 starts at time t2.

  For example, in the present embodiment, the change timing (time t2) from the voltage value Va to the voltage value Vb takes into account variations in the timing (time tx) when the selector element 200 is turned on based on experimental results or simulations. The timing is set. In the present embodiment, the timing of the change from the voltage value Va to the voltage value Vb is not the same as the timing at which the selector element 200 is turned on. The change timing from the voltage value Va to the voltage value Vb is a timing after the timing when the selector element 200 is turned on.

  In the MRAM of the present embodiment, there is a certain period between the timing when the selector element 200 is turned on and the timing when the program voltage (magnetization reversal threshold) is applied to the MTJ element 100.

  As described above, in the MRAM according to the present embodiment, after the selector element 200 is switched to the on state by a low voltage value, a certain time margin is ensured, and the MTJ element 100 is reversed in magnetization by the high voltage value.

  Note that the characteristics of the selector element 200 are designed based on the characteristics shown in FIG. 10 so that the state of the selector element 200 changes from the on-state to the off-state after time t3.

  In the MRAM of this embodiment, even if there is a variation in the switch time of the selector element 200 due to the control of the voltage value and application timing of the write voltage VWR, the application time of the program voltage of the MTJ element 100 does not vary.

  As a result, the MRAM of this embodiment can reduce the write error of the MTJ element.

(C) Specific example
A specific example of the MRAM of this embodiment will be described with reference to FIGS.

(C-1) Configuration example of write circuit
12 and 13 are equivalent circuit diagrams showing an example of the internal configuration of the write circuit of the MRAM of this embodiment. FIG. 12 shows an example of the internal configuration of the column side write circuit in the MRAM of this embodiment. FIG. 13 shows an example of the internal configuration of the row side write circuit in the MRAM of this embodiment.

  As shown in FIG. 12, the column side write circuit 13A includes a logic control circuit 500 and a voltage output circuit 510.

The logic control circuit 500 controls the voltage output timing in the voltage output circuit 510 using the control signals SEL and WR from the control circuit 18.
The control signal SEL is a signal for controlling the application timing of the switch voltage.
The control signal WR is a signal for controlling the application timing of the program voltage to the MTJ element 100.

  The voltage output circuit 510 outputs a voltage having the voltage value Va or the voltage value Vb to the column control circuit 11 at a timing based on the control by the logic control circuit 500.

For example, the logic control circuit 500 includes an OR gate 130, an AND gate 134, and inverters (NOT gates) 131, 133A, 133B, and 133C.
For example, the voltage output circuit 510 includes two P-type field effect transistors P1 and P2, one N-type field effect transistor N1, and voltage terminals 199a, 199b, and 199c. Hereinafter, the P-type field effect transistor is represented as a P-type transistor, and the N-type field effect transistor is represented as an N-type transistor.

A control signal WR is supplied to one input terminal of the OR gate 130.
The control signal SEL is supplied to the other input terminal of the OR gate 130 via the inverter 133A.
The output terminal of the OR gate 130 is connected to the gate of the P-type transistor P1.

  One end (one of source / drain) of the P-type transistor P1 is connected to a terminal 199a to which a voltage value Va is applied.

  The other end of the P-type transistor (the other of the source / drain) is connected to the voltage node 111 of the column control circuit 11.

  A control signal WR is supplied to the input terminal of the inverter 131. The output terminal of the inverter 131 is connected to the gate of the P-type transistor P2.

  One end (one of source / drain) of the P-type transistor P2 is connected to a voltage terminal 199b to which a voltage value Vb is applied. The other end (the other of the source / drain) of the P-type transistor P2 is connected to the voltage node 111 of the column control circuit 11. As described above, the voltage value Vb is higher than the voltage value Va.

The control signal SEL is supplied to one input terminal of the AND gate 134 via the inverter 133B. The control signal WR is supplied to the other input terminal of the AND gate 134 via the inverter 133C.
The output terminal of the AND gate 134 is connected to the gate of the N-type transistor N1.

  One end (one of source / drain) of the N-type transistor N1 is connected to the voltage node 111 of the column control circuit 11. The other end (the other of the source / drain) of the N-type transistor N1 is connected to a voltage terminal (ground terminal) 199c to which a ground voltage VSS (for example, 0 V) is applied.

  On / off of the P-type transistor P <b> 1 is controlled based on the output signal of the OR gate 130.

  When the signal level of the control signal WR is “L (low)” level and the signal level of the control signal SEL is “H (High)” level, the OR gate outputs the signal of “L” level, Output.

  The P-type transistor P1 is turned on by the “L” level signal. As a result, the P-type transistor P1 outputs the voltage value Va to the column control circuit 11.

  On / off of the P-type transistor P2 is controlled based on the output signal of the inverter 131.

  When the signal level of the control signal WR is “H” level, the inverter 131 outputs an “L” level signal.

  The P-type transistor P2 is turned on by the “L” level signal. As a result, the P-type transistor P2 outputs the voltage of the voltage value Vb to the column control circuit 11.

  ON / OFF of the N-type transistor N1 is controlled based on the output signal of the AND gate 134.

When at least one of the signal level of the control signal SEL and the signal level of the control signal WR is “H” level, the AND gate 134 outputs a signal of “L” level.
The N-type transistor N1 is turned off by the “L” level signal.

When both the control signal SEL and the control signal WR are at “L” level, the AND gate 134 outputs a signal at “H” level.
The N-type transistor N1 is turned on by the “H” level signal. Thereby, the N-type transistor N1 can connect the ground terminal 199c to the column control circuit 11. The on-state N-type transistor N1 outputs the ground voltage VSS to the column control circuit 11.

  As a result, the column side write circuit 13A can discharge the selected bit line BLi when both the control signal SEL and the control signal WR are at "L" level.

For example, even if both the control signal SEL and the control signal WR are simultaneously at the “H” level, the logic control circuit 500 and the voltage are set so that the voltage value Vb is output from the column side write circuit 13A to the column control circuit 11. Each element of the output circuit 510 is designed. Therefore, the writing circuit 13A in FIG. 12 may not synchronize the falling time of the control signal SEL and the rising time of the control signal WR.
Further, the voltage values of the voltage terminals 199a and 199b may be appropriately changed according to the output voltage of the row side write circuit 13B.

  As shown in FIG. 13, the row side write circuit 13 </ b> B includes a logic control circuit 520 and a voltage output circuit 530.

  The logic control circuit 520 controls the output timing of the voltage in the voltage output circuit 530 using the control signals SEL and WR from the control circuit 18.

  The voltage output circuit 530 outputs a voltage to the row control circuit 12 at a timing based on control by the logic control circuit 520.

For example, the logic control circuit 520 includes an OR gate 135.
For example, the voltage output circuit 530 includes one N-type transistor N1.

A control signal WR is supplied to one input terminal of the OR gate 135. A control signal SEL is supplied to the other input terminal of the OR gate 135.
The output terminal of the OR gate 135 is supplied to the gate of the N-type transistor N2.

  One end (one of source / drain) of the N-type transistor N2 is connected to the voltage node 121 of the row control circuit 12.

  The other end (the other of the source / drain) of the N-type transistor N2 is connected to the ground terminal 199d.

  On / off of the N-type transistor N2 is controlled based on the output signal of the OR gate 135.

  When at least one of the signal level of the control signal WR and the signal level of the control signal SEL is “H” level, the OR gate 135 outputs an “H” level signal.

  The N-type transistor N2 is turned on by the “H” level signal. As a result, the N-type transistor N2 outputs the ground voltage VSS to the row control circuit 12.

(C-2) Example of operation
An example of an operation example of the MRAM of this embodiment will be described with reference to FIGS.

FIG. 14 is a flowchart for explaining an operation example of the MRAM according to the present embodiment.
FIG. 15 is a diagram schematically showing the potential state of the wiring in the memory cell array during the operation of the MRAM of this embodiment.
FIG. 16 is a timing chart for explaining an operation example of the MRAM according to the present embodiment. FIG. 16 shows changes in the signal level of the control signal and the voltage of each wiring during the write operation of the MRAM of this embodiment.

  Here, FIG. 1 to FIG. 13 and the like are also used as appropriate in order to explain an operation example of the MRAM of this embodiment.

  As shown in FIG. 14, a sequence including the write operation of the MRAM of this embodiment is started (step ST0).

  For example, the write sequence of the MRAM according to the present embodiment is such that a write command, various control signals, addresses, and data to be written to memory cells (hereinafter referred to as write data) are transferred from an external device to the MRAM according to the present embodiment. Is started.

  For example, a write command and a control signal are supplied to the control circuit 18. The control circuit 18 controls the operations of the circuits 11 to 17 in the MRAM 1 based on the write command and the control signal. Write data is supplied to the write circuits 13A and 13B (and read circuits 14A and 14B) via the I / O circuit 16, for example.

  The address is supplied to the decode circuit 15. The decode circuit 15 decodes the address. The decoding circuit 15 supplies the decoding result to the column control circuit 11 and the row control circuit 12 as a selected column signal CS and a selected row signal RS (and a non-selected signal).

  Prior to data writing, pre-reading (internal reading) is performed on the selected cell to be written (step ST1).

  At least data in the selected cell is read by the read circuits 14A and 14B (or write circuits 13A and 13B). For example, the read data is temporarily held in a latch circuit (not shown) in the read circuit 14A. The read data is compared with the write data, and it is determined whether or not the read data and the write data are the same (step ST2).

  When the write data and the read data are the same, the write sequence ends without executing the write operation (without applying the write voltage to the memory cell).

  If the data to be written is different from the read data, data writing (program operation) to the selected cell is executed (step ST3). Thereby, application of the write voltage VWR is executed.

  As shown in FIG. 15, for example, a write voltage VWR is applied to the selected bit line BLi, and a voltage (ground voltage) of 0 V is applied to the selected word line WLi. As described above, in this embodiment, the selected bit line BLi is set to the high potential side when the write voltage VWR is applied, and the selected word line WLi is set to the low potential side when the write voltage VWR is applied. .

  In the present embodiment, the potential state of the bit lines (non-selected bit lines) BLx other than the selected bit line BLi is set to a floating state. Similarly, the potential state of word lines (non-selected word lines) WLx other than the selected word line WLi is set to a floating state. In this case, since no voltage is applied to the unselected bit line BLx and the unselected word line WLx, generation of power consumption in the memory cell array 10 can be suppressed.

  In this case, it is desirable that the selector element 200 is designed so that the selector element 200 in the non-selected cell MCx is not turned on by the sneak voltage (or sneak current) of the write voltage VWR.

  Under the control of the write circuits 13A and 13B, a write voltage VWR having a stepped pulse waveform is applied to the memory cell (selected cell) MCi via the selected bit line BLi and the selected word line WLi.

  As shown in FIG. 16, at the time t0 before the start of the application of the write voltage VWR, the signal level of the selected column signal CS and the signal level of the selected row signal RS are, for example, based on the decoding result of the decoding circuit 15. Transition from the “L” level to the “H” level. The selected bit line BLi and the selected word line WLi are set to the selected state by the “H” level selected column signal CS and the “H” level selected row signal RS. As a result, the selected bit line BLi and the selected word line WLi can be applied with a voltage.

  For example, the decode circuit 15 outputs an “L” level signal as a non-selection signal to the column control circuit 11 and the row control circuit 12 in order to control the potential of the non-selection bit line BLx and the non-selection word line WLx. it can. As a result, the non-selected bit line BL and the non-selected word line WL are set in an electrically floating state.

  At time t0, the control signal SEL is set to the “L” level, and the control signal WR is set to the “L” level.

  The column side write circuit 13A operates as follows according to the control signals SEL and WR.

The “L” level control signal WR is supplied to the inverter 131.
The inverter 131 outputs an “H” level signal to the gate of the P-type transistor P2. The P-type transistor P2 is turned off by the “H” level signal.

  The voltage node 111 of the column control circuit 11 is electrically isolated from the voltage terminal 199b by the P-type transistor P2 in the off state.

  An inverted signal of the control signal SEL is supplied to the OR gate 130 via the inverter 133A. The OR gate 130 outputs an “H” level signal to the gate of the P-type transistor P1 based on the “L” level control signal WR and the “H” level inverted signal. The P-type transistor P1 is turned off by the “H” level signal.

  The voltage node 111 of the column control circuit 11 is electrically isolated from the voltage terminal 199a by the P-type transistor P1 in the off state.

  “L” level control signals SEL and WR are supplied to inverters 133B and 133C, respectively. An “H” level signal is supplied to one input terminal of the AND gate 134, and an “H” level signal is supplied to the other input terminal of the AND gate 134. As a result, the AND gate 134 outputs an “H” level signal to the gate of the N-type transistor N1. The N-type transistor NT1 is turned on by an “H” level signal.

  The voltage node of the column control circuit 11 is electrically connected to the ground terminal 199c via the N-type transistor N1 in the on state. As a result, the selected bit line BLi is discharged.

  The row side write circuit 13B operates as follows according to the control signals WR and SEL.

  The OR gate 135 outputs an “L” level signal to the gate of the N-type transistor N2 in response to the “L” level control signals WR and SEL.

  The N-type transistor N2 is turned off by the “L” level signal.

  The voltage node 121 of the row control circuit 12 is brought into a floating state by the N-type transistor N2 in the off state.

  At time t1, the control circuit 18 changes the signal level of the control signal SEL from the “L” level to the “H” level in order to set the selector element 200 to the ON state. The signal level of the control signal SEL is set to the “H” level. The signal level of the control signal WR is maintained at the “L” level.

  When the “H” level control signal SEL is supplied at time t1, the column side write circuit 13 operates as follows.

  Inverter 131 outputs an “H” level signal (inverted signal WR) to the gate of P-type transistor P2.

  As a result, the voltage node 111 of the column control circuit 11 is electrically isolated from the voltage terminal 199b by the P-type transistor P2 in the off state.

  The “H” level control signal SEL is supplied to the inverter 133B, and the “L” level control signal WR is supplied to the inverter 133C. An “L” level signal (inverted signal SEL) and an “H” level signal (inverted signal WR) are supplied to the AND gate 134. Therefore, the AND gate 134 outputs an “L” level signal to the gate of the N-type transistor N1. The N-type transistor N1 is turned off by the “L” level signal. As a result, the voltage node 111 of the column control circuit 11 is electrically isolated from the ground terminal 199c.

An “H” level control signal SEL is supplied to the inverter 133A.
An inverted signal of the control signal SEL is supplied to the OR gate 130 via the inverter 133A. The “L” level control signal WR and the “L” level inverted signal are supplied to the OR gate 130.

Therefore, the OR gate 130 outputs an “L” level signal to the gate of the P-type transistor P1. The P-type transistor P1 is turned on by an “L” level signal.
As a result, the voltage node 111 of the column control circuit 11 is electrically connected to the voltage terminal 199a by the P-type transistor P1 in the on state.

  As a result, the voltage value Va is applied from the voltage terminal 199a to the voltage node 111 of the column control circuit 11.

  When the “H” level control signal SEL is supplied at time t1, the low-side write circuit 13B operates as follows.

  “H” level control signal SEL and “L” level control signal WR are supplied to OR gate 135. Therefore, the OR gate 135 outputs an “H” level signal to the gate of the N-type transistor N2.

The N-type transistor N2 is turned on by an “H” level signal.
As a result, the voltage node 121 of the row control circuit 12 is electrically connected to the ground terminal 199d by the N-type transistor N2 in the on state.

  In this way, the column control circuit 11 applies the voltage of the voltage value Va to the selected bit line BLi by the “H” level control signal SEL and the “L” level control signal WR, and the row control circuit 12 A voltage VSS (0 V) is applied to the selected word line WLi.

  As a result, the potential difference Va between the selected bit line BLi and the selected word line WLi is applied to the selected cell MC as the voltage value of the write voltage.

  Here, as described above, the resistance value of the selector element 200 in the off state is higher than the resistance value of the MTJ element 100. Therefore, most of the write voltage VWR (voltage value Va) is applied to the selector element 200.

  Therefore, a voltage divided by the selector element 200 in the write voltage VWR is applied to the selector element 200 as a switch voltage.

  The switch voltage in the write voltage is applied to the selected cell in the period TSEL from time t1 to time t2. The voltage value Va of the switch voltage is equal to or higher than the ON voltage of the selector element 200 and is smaller than the magnetization reversal threshold value of the MTJ element 100.

  By applying the switch voltage VSW over the period TSEL, the resistance state of the selector element 200 changes from the high resistance state to the low resistance state at a certain time tx in the period TSEL. Thereby, the selector element 200 is set to an on state.

  After a period of time has elapsed since the selector element 200 was switched from the off state to the on state, data writing (program operation) to the MTJ element 100 is performed.

  At time t2, the control circuit 18 changes the signal level of the control signal SEL from the “H” level to the “L” level for the program operation (magnetization inversion of the storage layer) of the MTJ element 100. At substantially the same time, the control circuit 19 changes the signal level of the control signal WR from the “L” level to the “H” level. The time t2 is a time after the time tx when the selector element 200 is turned on.

  When the “H” level control signal WR is supplied at time t2, the column side write circuit 13A operates as follows.

  “H” level control signal WR is supplied to inverter 131. The inverter 131 supplies an “L” level signal to the gate of the P-type transistor P2. The P-type transistor P2 is turned on by the “L” level signal.

  As a result, the voltage node 111 of the column control circuit 11 is electrically connected to the voltage terminal 199b by the P-type transistor P2 in the on state.

The “L” level control signal SEL is supplied to the inverter 133B, and the “H” level control signal WR is supplied to the inverter 133C. An “H” level signal (inverted signal SEL) and an “L” level signal (inverted signal WR) are supplied to the AND gate 134. Therefore, the AND gate 134 outputs an “L” level signal to the gate of the N-type transistor N1. The N-type transistor N1 is turned off by the “L” level signal.
As a result, the voltage node 111 of the column control circuit 11 is electrically isolated from the ground terminal 199c by the N-type transistor N1 in the off state. At this time, for example, the voltage node 111 is in a floating state with respect to the ground terminal 199c.

  An inverted signal of the control signal SEL is supplied to the OR gate 130 via the inverter 133A. Therefore, the “H” level control signal WR and the “H” level signal are supplied to the OR gate 130.

Therefore, the OR gate 130 outputs an “H” level signal to the gate of the P-type transistor P1. The P-type transistor P1 is turned off by the “H” level signal.
The voltage node 111 of the column control circuit 11 is electrically isolated from the voltage terminal 199a by the P-type transistor P1 in the off state. As a result, the supply of voltage from the voltage terminal 199a to the column control circuit 11 is cut off.

As a result, a voltage having a voltage value Vb is applied from the voltage terminal 199b to the voltage node 111 of the column control circuit 11.
Thus, at time t2, the voltage value of the output voltage of the column side write circuit 13A continuously changes from the voltage value Va to the voltage value Vb.

  When the “H” level control signal WR is supplied at time t2, the low-side write circuit 13B operates as follows.

“H” level control signal WR and “L” level control signal SEL are supplied to OR gate 135. Therefore, the OR gate 135 outputs an “H” level signal to the gate of the N-type transistor N2. The N-type transistor N2 is turned on by an “H” level signal.
The voltage node 121 of the row control circuit 12 is electrically connected to the ground terminal 199d by the N-type transistor N2 in the on state.

  As described above, the column control circuit 11 applies the voltage of the voltage value Vb (Vb> Va) to the selected bit line BLi, and the row control circuit 12 applies the ground voltage VSS (0 V) to the selected word line WLi.

  As a result, the potential difference Vb between the selected bit line BLi and the selected word line WLi is applied to the selected cell MCi as the voltage value of the write voltage VWR.

  In the present embodiment, the voltage value of the write voltage rises after a certain period has elapsed after the selector element 200 is turned on.

  Here, the resistance value of the selector element 200 is sufficiently lower than the resistance value of the MTJ element. Therefore, most of the write voltage VWR (voltage value Vb) is applied to the MTJ element 100.

  Therefore, a voltage divided by the MTJ element 100 in the write voltage VWR is applied to the MTJ element 100 as a program voltage.

  The program voltage of the write voltage VWR is applied to the selected cell in a period T2 from time t2 to time t3. The voltage value Vb of the program voltage is a voltage value equal to or higher than the magnetization reversal threshold value of the MTJ element 100. For example, the voltage value Vb is preferably a value set so that the current flowing through the selector element 200 is equal to or less than the limit current.

  By applying the program voltage, the magnetization of the storage layer 101 of the MTJ element 100 starts precession.

  At time t3, the signal level of the control signal WR is changed from the “H” level to the “L” level. The signal level of the control signal SEL is maintained at the “L” level.

  The column side write circuit 13A operates as follows by the control signals SEL and WR at time t3.

The “L” level control signal WR is supplied to the inverter 131. The inverter 131 supplies an “H” level signal to the gate of the P-type transistor P1. The P-type transistor P1 is turned off by the “H” level signal.
The voltage node 111 of the column control circuit 11 is electrically isolated from the voltage terminal 199b by the P-type transistor P1 in the off state.

The “L” level control signal SEL is supplied to the inverter 133B, and the “L” level control signal WR is supplied to the inverter 133C. Two “H” level signals are supplied to the AND gate 134. Therefore, the AND gate 134 outputs an “H” level signal to the gate of the N-type transistor N1. The N-type transistor N1 is turned on by the “H” level signal.
The voltage node 111 of the column control circuit 11 is electrically connected to the ground terminal 199c by the N-type transistor N1 in the on state.

The “L” level control signal WR and the “H” level inverted signal are supplied to the OR gate 130. Therefore, the OR gate 130 outputs an “H” level signal to the gate of the P-type transistor P2. The P-type transistor P2 is turned off by the “H” level signal.
The voltage node 111 of the column control circuit 11 is electrically separated from the voltage terminal 199a by the P-type transistor P2 in the off state.

  As a result, the ground terminal 199c is connected to the voltage node of the column control circuit 11. As a result, the voltage node 111 of the column control circuit 11 is discharged.

  The row side write circuit 13B operates as follows in accordance with the control signals SEL and WR at time t3.

  The “L” level control signal WR and the “L” level control signal SEL are supplied to the OR gate 135.

  Therefore, the OR gate 135 outputs an “L” level signal to the gate of the N-type transistor N2. The N-type transistor N2 is turned off by the “L” level signal.

  The voltage node 121 of the row control circuit 12 is brought into a floating state by the N-type transistor N2 in the off state.

  Thus, at time t3, the voltage value of the selected bit line BLi drops from the voltage value Vb to 0V. The selected word line WLi is in a floating state.

  As described above, the voltage application period (program time) TMTJ having the voltage value Vb from time t2 to time t3 is set to substantially the same length as the half cycle of magnetization reversal of the memory layer 101.

  Therefore, in the MTJ element 100 in the selected cell MC, the magnetization direction of the storage layer 101 is reversed with respect to the state before the voltage of the voltage value Vb is applied.

  As a result, the magnetization arrangement state (resistance state) of the MTJ element 100 changes to a state corresponding to the write data. As a result, in the MRAM of this embodiment, data is written into the selected cell MCi during the write operation.

  At time t4, the signal levels of the selection signals CS and RS are changed from the “H” level to the “L” level. As a result, the column control circuit 11 deactivates the selected bit line BLi, and the row control circuit 12 deactivates the selected word line WLi. As a result, the selected cell MCi is deactivated.

  For example, the selector element 200 changes from the on state to the off state after time t3 (or time t4).

  The column control circuit 11 cancels the floating state of the non-selected bit line BLi, and the row control circuit 12 cancels the floating state of the non-selected word line WLx.

  The control circuit 18 detects the end of application of the write voltage. The control circuit 18 ends the control of each circuit for the write operation corresponding to the command. For example, the control circuit 18 can notify the external device of the end of the write operation.

  Thereby, the write operation of the MRAM of this embodiment is completed.

  As described above, the write operation of the MRAM of this embodiment is executed.

(D) Summary
The magnetic memory of this embodiment has memory cells connected between the bit lines and the word lines. The memory cell includes a selector element and a magnetoresistive element. The selector element and the magnetoresistive element are connected in series between the bit line and the word line.

  In the magnetic memory (for example, MRAM) of the present embodiment, the write voltage during the write operation has the first voltage value in the first period, and the second voltage in the second period after the first period. Has a voltage value. The second voltage value is higher than the first voltage value.

  The first voltage value is a voltage value for setting the selector element to the ON state.

  The second voltage value is a voltage value equal to or higher than the magnetization reversal threshold value of the storage layer of the magnetoresistive effect element. In the first period, the selector element is set to an on state. In the second period, the magnetization direction of the memory layer of the magnetoresistive effect element is reversed. The second period is shorter than the first period.

  In the magnetic memory of the present embodiment, the magnetoresistive effect element is a voltage effect type magnetoresistive effect element. Therefore, in the magnetoresistive element, the reversal of the magnetization of the storage layer depends on the magnitude of the second period.

  The magnetic memory of this embodiment can apply a voltage equal to or higher than the magnetization reversal threshold value to the MTJ element after a certain period has elapsed since the selector element was turned on.

  Therefore, in the magnetic memory according to the present embodiment, even when the selector element is turned on (switched from the high resistance state to the low resistance state) at each selector element (memory cell), the magnetization of the magnetoresistive effect element is different. It is possible to suppress fluctuations in the start timing of application of a voltage (program voltage) equal to or higher than the inversion threshold.

  As a result, the magnetic memory of this embodiment can prevent the pulse width of the program voltage from deviating from the value set for the magnetization reversal of the storage layer. As described above, the magnetic memory according to the present embodiment can apply the program voltage having the pulse width set for the magnetization reversal of the storage layer to the memory cell relatively stably.

As a result, the magnetic memory of the present embodiment can reduce the error occurrence rate related to data writing of the magnetic memory using the voltage effect type magnetoresistive effect element.
Therefore, the magnetic memory of this embodiment can improve the reliability of data writing to the memory cell using the voltage effect type magnetoresistive effect element.

  As described above, the magnetic memory of this embodiment can improve the memory characteristics.

(2) Second embodiment
A magnetic memory (for example, MRAM) and a control method thereof according to the second embodiment will be described with reference to FIGS.
(A) Basic example
FIG. 17 is a schematic diagram showing the potential state of each wiring in the memory cell array during the write operation of the MRAM of this embodiment.

  As shown in FIG. 17, in the present embodiment, during the write operation to the selected cell, the voltage VINH1 is applied to the unselected bit line BLx, and the voltage VINH2 is applied to the unselected word line WLx.

  As a result, the MRAM according to the present embodiment can suppress malfunction of the non-selected cell MCx during the write operation (for example, erroneous writing to the non-selected cell).

  Hereinafter, the voltage applied to the non-selected word line and the non-selected bit line during the write operation (and the read operation) is referred to as a non-select voltage.

  FIG. 18 is a voltage waveform diagram showing unselected voltages of unselected bit lines and word lines during the write operation in the MRAM of this embodiment. FIG. 18 shows a pulse waveform of the write voltage VWR, a pulse waveform of the non-selection voltage VINH1 applied to the bit line, and a pulse waveform of the non-selection voltage VINH2 applied to the word line.

  As shown in FIG. 18, the non-selection voltages VINH1 and VINH2 have a rectangular pulse shape. The voltage values of the non-selection voltages VINH1 and VINH2 are constant during the application period of the write voltage VWR. The non-selection voltage VINH1 has a voltage value Vi1, and the non-selection voltage VINH2 has a voltage value Vi2.

  The voltage values Vi1 and Vi2 are voltage values smaller than the ON voltage (for example, voltage value Va) of the selector element.

  For the non-selected cell MCx connected between the non-selected bit line BLx and the non-selected word line WLx, the potential difference (VINH1-VINH2) between the voltage of the non-selected bit line BLx and the voltage of the non-selected word line WLx is Applied.

  With respect to an unselected cell (hereinafter also referred to as a selected word line shared cell) MCx connected between the unselected bit line BLx and the selected word line WLi, the voltage of the unselected bit line BLx and the selected word line WLi A potential difference (VINH1−VWL) from a voltage (herein expressed as “VWL”) is applied.

  A voltage (here, “VBL”) of the selected bit line BLi with respect to an unselected cell (hereinafter also referred to as a selected bit line shared cell) MCx connected between the selected bit line BLi and the unselected word line WLx. A potential difference (VBL−VINH2) between the voltage of the unselected word line WLx and the unselected word line WLx is applied.

  In the following description, when a non-selected cell (selected bit line shared cell) connected to a selected bit line and a non-selected cell (selected word line shared cell) connected to a selected word line are not distinguished, the selected bit line is shared. The cell and the selected word line shared cell are also called half-selected cells. In addition, unselected cells that are not connected to the selected bit line BLi and the selected word line WLi are also called unshared cells for differentiation.

  For example, the rise start time (timing) ta of the non-selection voltages VINH1 and VINH2 is earlier than the rise start time t1 of the write voltage VWR.

  The falling start time tb of the non-selection voltages VINH1 and VINH2 is later than the falling start time t3 of the write voltage VWR.

  As a result, the period TA during which the non-selection voltages VINH1 and VINH2 are applied to the non-selected bit lines / word lines BLx and WLx is a period during which the write voltage VWR is applied to the selected bit lines / word lines BLi and WLi ( (Period from time t1 to time t3).

  In this case, even if the voltage value of the write voltage VWR is 0 V, the voltage value (potential difference) of the applied voltage to the non-selected cell MCx becomes the voltage value Vi1, the voltage value Vi2, or the voltage value Vi1-Vi2. Therefore, the MRAM according to the present embodiment can prevent the malfunction of the unselected cell even when the write voltage VWR is not applied to the selected bit line BLi and the selected word line WLi.

(B) Specific example
A specific example of the MRAM of this embodiment will be described with reference to FIGS.

<Circuit example>
19 and 20 are equivalent circuit diagrams showing an example of the internal configuration of the write circuit of the MRAM of this embodiment. FIG. 19 shows an example of the internal configuration of the column side write circuit in the MRAM of this embodiment. FIG. 20 shows an example of the internal configuration of the row side write circuit in the MRAM of this embodiment.

  As shown in FIG. 19, the column side write circuit 13A further includes a P-type transistor P3 and an inverter 139A.

One end of the current path of the P-type transistor P3 is connected to the voltage terminal 199e. A voltage value Vi1 is applied to the voltage terminal 199e. The other end of the current path of the P-type transistor P3 is connected to the second voltage node 119 of the column control circuit 11.
The gate of the P-type transistor P3 is connected to the output terminal of the inverter 139A.

  The control signal INH1 is supplied to the gate of the P-type transistor P3 via the inverter 139A. The P-type transistor P3 is turned on or off in accordance with the signal level of the control signal INH1.

  The unselected voltage VINH1 having the voltage value Vi1 is applied to the unselected bit line BLx via the column control circuit 11 by the P-type transistor P3 in the on state.

  As shown in FIG. 20, the row side write circuit 13B includes a P-type transistor P4 and an inverter 139B.

One end of the current path of the P-type transistor P4 is connected to the voltage terminal 199f. The voltage value Vi1 is applied to the voltage terminal 199e. The other end of the current path of the P-type transistor P4 is connected to the second voltage node 129 of the row control circuit 12.
The gate of the P-type transistor P4 is connected to the output terminal of the inverter 139B.

  The control signal INH2 is supplied to the gate of the P-type transistor P4 via the inverter 139B. The P-type transistor P3 is turned on or off according to the signal level of the control signal INH2.

  The unselected voltage VINH2 having the voltage value Vi2 is applied to the unselected word line WLx via the row control circuit 12 by the P-type transistor P3 in the on state.

<Operation example>
FIG. 21 is a timing chart for explaining an operation example of the MRAM of this embodiment.

  The voltage application to the selected bit line BLi and the selected word line WLi is controlled by the control signals SEL and WR as in the above example (for example, FIG. 16).

  Application of voltages to the non-selected bit line BLx and the non-selected word line WLx is controlled by control signals INHc and INHr.

  As shown in FIG. 21, at time t0, the selection signals CS and RS are set to the “H” level for the selected bit line BLi and the selected word line WLi. For example, the selection signal is set to the “L” level for the non-selected bit line BLx and the non-selected word line WLx.

  At time t0, the signal levels of the control signals INH1 and INH2 are “L” level.

  In the column side write circuit 13A, an “H” level signal is input to the gate of the P-type transistor P3 via the inverter 139A. As a result, the P-type transistor P3 is turned off. The voltage node 119 of the column control circuit 11 is electrically isolated from the voltage terminal 199e by the off-state P-type transistor P3.

  In the low-side write circuit 13B, an “H” level signal is input to the gate of the P-type transistor P4 via the inverter 139B. As a result, the P-type transistor P3 is turned off. The voltage node 129 of the row control circuit 12 is electrically isolated from the voltage terminal 199f by the P-type transistor P4 in the off state.

  Thus, at time t0, the potential of the unselected bit line BLi and the potential of the unselected word line WLx are set to 0 V (or a floating state).

  At time ta between time t0 and time t1, the control circuit 18 changes the signal levels of the control signals INH1 and INH2 from the “L” level to the “H” level.

  In the column side write circuit 13A, an “H” level signal INH1 is supplied to the inverter 139A. Inverter 139A outputs an “L” level signal to the gate of P-type transistor P3. The P-type transistor P3 is turned on by the “L” level signal.

  A non-selection voltage VINH1 having a voltage value Vi1 is applied to the voltage node 119 of the column control circuit 11 via the P-type transistor P3 in the on state. The column control circuit 11 applies the non-selection voltage VINH1 to the non-selection bit line BLx.

  In the low-side write circuit 13B, the “H” level signal INH2 is input to the inverter 139B. Inverter 139B outputs an “L” level signal to the gate of P-type transistor P4. The P-type transistor P4 is turned on by the “L” level signal.

  A non-selection voltage VINH2 having a voltage value Vi2 is applied to the voltage node 129 of the row control circuit 12 via the P-type transistor P4 in the on state. The row control circuit 12 applies the non-selection voltage VINH2 to the non-selected word line WLx.

  As described in the first embodiment, application of the write voltage VWR is started at time t1.

  When the write voltage VWR is applied, the following voltage is applied to the non-selected cell MCx. The voltage applied to the selected bit line common cell is “VWR-VINH1”. The voltage applied to the selected word line common cell is “VINH2”. The voltage applied to the other non-selected cells (non-common cells) is “VINH1-VINH2”.

  For example, regarding the non-selection voltages VINH1 and VINH2, for example, the magnitude of the voltage value Vi1 is the same as the voltage value Vi2. For example, the voltage values Vi1 and Vi2 are set to half the voltage value Va (Va / 2).

  Thus, in the period TSEL, the voltage applied to the selected cell (non-shared cell) connected to the unselected bit line BLx and the unselected word line WLx becomes 0V. In this case, the power consumption of the memory cell array 10 is mainly generated in the selected bit line shared cell and the selected word line shared cell (half-selected cell).

  The voltage applied to the selected bit line shared cell is the difference between the voltage value of the write voltage VWR and the voltage value of the non-selection voltage VINH2. The voltage applied to the selected word line shared cell is the difference between 0V and the voltage value of the non-selection voltage VINH1.

  For example, in the period TSEL, the applied voltage to the selected bit line shared cell is “Va / 2” (absolute value), and the applied voltage to the selected word line shared cell is “Va / 2” (absolute value). In the period TMTJ, the applied voltage to the selected bit line shared cell is “Vb−Va / 2” (absolute value), and the applied voltage to the selected word line shared cell is “Va / 2” (absolute value).

  As described above, in this embodiment, when the non-selection voltages VINH1 and VINH2 are used during the write operation, the power consumption generated in the MRAM is minimized.

  The polarity of the voltage applied to the selected bit line shared cell is opposite to the polarity of the voltage applied to the selected word line shared cell.

The voltage value Vi1 of the non-selection voltage VINH1 may be different from the voltage value Vi2 of the non-selection voltage VINH2.
For example, the voltage value Vi1 of the non-selection voltage VINH1 is set to a magnitude (Va / 3) that is about one third of the voltage value Va. For example, the voltage value Vi2 of the non-selection voltage VINH2 is set to a magnitude (2Va / 3) that is about two-thirds of the voltage value Va.

  Thereby, in the period TSEL, the applied voltage to all the non-selected cells in the memory cell array 10 becomes the voltage value Va / 3.

  In this case, the MRAM according to the present embodiment can ensure the resistance against the variation of the switch voltage of the selector element 200 in the non-selected cell MCx. Therefore, the MRAM of this embodiment can suppress malfunction of the selector element 200 in the non-selected cell MCx.

  In the period TSEL and the period TMTJ, the write circuits 13A and 13B apply the non-selection voltages VINH1 and VINH2 to the non-selected bit lines BLx and the non-selected word lines WLx, and the write circuits 13A and 13B write as described above. The voltage VWR is applied to the selected cell MCi.

The selector element 200 in the selected cell MCi is set to the on state by the write voltage VWR having the voltage value Va in the period TSEL. The magnetization of the storage layer of the MTJ element 100 in the selected cell MCi is reversed by the write voltage VWR having the voltage value Vb in the period TMTJ.
At time tb after time t3, the signal levels of the control signals INH1 and INH2 are changed from the “H” level to the “L” level.

  In the column side write circuit 13A, an “L” level signal INH1 is supplied to the inverter 139A. Inverter 139A outputs an “H” level signal to the gate of P-type transistor P3. The P-type transistor P3 is turned off by the “H” level signal.

  In the low-side write circuit 13B, an “L” level signal INH2 is supplied to the inverter 139B. Inverter 139B outputs an “H” level signal to the gate of P-type transistor P4. The P-type transistor P4 is turned off by the “H” level signal.

  As a result, the application of the non-selection voltage to the non-selected bit line BLx and the non-selected word line WLx is stopped.

  At time t4, the signal levels of the selection signals CS and RS are changed from the “H” level to the “L” level. As a result, the selected cell MCi is deactivated. Further, the non-selected cell MCx is also released from the state where the non-selected voltage can be applied.

  Thus, in the MRAM of this embodiment, the write operation for the selected cell is completed.

  As described above, the MRAM according to the present embodiment can execute the write operation on the selected cell even when a voltage is applied to the unselected bit line and the unselected word line.

(C) Modification
A modification of the MRAM of this embodiment will be described with reference to FIG.

  FIG. 22 is a voltage waveform diagram for explaining a modification of the MRAM of the present embodiment.

  The modification of FIG. 22 is different from the example of FIG. 21 in the timing of starting and stopping the application of the non-selection voltages VINH1 and VINH2 to the non-selected bit line BLx and the non-selected word line WLx during the MRAM write operation. .

  As shown in FIG. 22, the rising start time of the non-selection voltages VINH1 and VINH2 is set to substantially the same time as the rising start time t1 of the write voltage VWR.

  The start time of falling of the non-selection voltages VINH1 and VINH2 is set to substantially the same time as the start time t2 of the rising of the program voltage (increase from the voltage value Va to the voltage value Vb).

  For example, in the circuits of FIGS. 19 and 20, the start time of the rise / fall of the non-selection voltage shown in FIG. 22 can be controlled by controlling the timing of the signal level change of the control signals INH1 and INH2.

As described above, the switch time (magnetization reversal time) of the MTJ element is shorter than the switch time of the selector element.
Therefore, even if a non-selected cell including an off-state selector element is in a floating state or a voltage is applied in the period TMTJ, the possibility of erroneous writing in the non-selected cell is small.

  In the example of FIG. 22, the application period of the non-selection voltage to the non-selected cell is shortened. As a result, the MRAM according to the modification of the present embodiment can suppress an increase in power consumption during the write operation when the applied voltage of the non-selected cell is controlled.

  FIG. 23 is a timing chart for explaining a modified example different from FIG. 22 in the write operation of the MRAM of the present embodiment.

  As shown in FIG. 23, the falling start time of the non-selection voltages VINH1 and VINH2 may be set to substantially the same time as the falling start time t3 of the program voltage VPGM.

  As a modification of the example of FIG. 18, only the rise start time ta of the non-selection voltages VINH1 and VINH2 may be different from the rise start time t1 of the write voltage VWR, or the non-selection voltages VINH1 and VINH2 Only the falling start time tb of the write voltage VWR may be different from the fall time t3 of the write voltage VWR.

(D) Summary
The magnetic memory of this embodiment applies a non-selection voltage to a non-selected bit line and a non-selected word line during a write operation.
Thereby, the magnetic memory according to the present embodiment can suppress the malfunction of the non-selected cell during the write operation.

  As a result, the magnetic memory of this embodiment can improve the reliability of the memory.

  Therefore, the magnetic memory of the second embodiment can improve the memory characteristics.

(3) Third embodiment
A magnetic memory (for example, MRAM) and a control method thereof according to the third embodiment will be described with reference to FIGS.

(A) Basic example
A basic example of the MRAM of this embodiment will be described with reference to FIG.

  FIG. 24 is a voltage waveform diagram showing the pulse waveform of the write voltage used in the write operation of the MRAM of this embodiment.

  As shown in FIG. 24, in this embodiment, a certain period TI is provided between the application period TSEL of the switch voltage VSW for the selector element 200 and the application period TMTJ of the program voltage VPGM for the MTJ element 100. .

  By this period TI, the switch voltage VSW is separated from the program voltage VPGM.

  In the period TI, the voltage value of the write voltage VWR is smaller than the voltage value Va. For example, the voltage value of the write voltage VWR in the period TI is set to 0V.

  The length of the period TI is shorter than the period in which the selector element 200 transitions from the on state (low resistance state) to the off state (high resistance state). The selector element 200 maintains the on state in the period TI and the period TMTJ.

  Therefore, as shown in FIG. 23, even if a period of a voltage value smaller than the voltage value of the switch voltage is provided between the switch voltage and the program voltage in the write voltage VWR, the present embodiment The effect similar to the effect of embodiment can be acquired.

(B) Specific example
A specific example of the MRAM of this embodiment will be described with reference to FIGS.

(B-1) Specific example 1
A specific example 1 of the MRAM according to the present embodiment will be described with reference to FIGS.

<Configuration example>
FIG. 25 is an equivalent circuit diagram showing an example of the internal configuration of the column side write circuit in the specific example of the MRAM of the present embodiment.

  As shown in FIG. 25, the column side write circuit 13A includes two inverters 137A and 137B and two P-type transistors P1 and P2.

One end of the P-type transistor P1 is connected to the voltage terminal 199a. The other end of the P-type transistor P1 is connected to the voltage node 111 of the column control circuit 11. The gate of the P-type transistor P1 is connected to the output terminal of the inverter 137A.
A control signal SEL is supplied to the input terminal of the inverter 137A.

  The control signal SEL is supplied to the gate of the P-type transistor P1 through the inverter 137A.

  One end of the P-type transistor P2 is connected to the voltage terminal 199b. The other end of the P-type transistor P2 is connected to the voltage node of the column control circuit 11. The gate of the P-type transistor P2 is connected to the output terminal of the inverter 137B.

  A control signal WR is supplied to the input terminal of the inverter 137B.

  The control signal WR is supplied to the gate of the P-type transistor P2 via the inverter 137B.

  In the MRAM of this embodiment, the configuration of the row side write circuit 13B is substantially the same as the example shown in FIG.

  Like the write voltage VWR shown in FIG. 24, there is an interval (period) TI having a certain length between the switch period TSEL of the selector element 200 and the program period TMTJ of the MTJ element 100.

  As a result, in the MRAM according to the present embodiment, the application of the switch voltage and the application of the program voltage when the write operation is applied are controlled independently of each other.

  When the write voltage VWR of FIG. 24 is applied to the selected cell MCi, for example, as in the example of FIG. 15, the unselected bit line BLx and the unselected word line WLx are set in an electrically floating state. .

<Operation example>
FIG. 26 is a timing chart for explaining an operation example of the MRAM according to the present embodiment.

  As shown in FIG. 26, at time t1 before the start of application of the write voltage VWR, the signal level of the selected column signal CS and the signal level of the selected row signal RS are changed from the “L” level to the “H” level. The The selected bit line BLi and the selected word line WLi are activated and set to the selected state by the “H” level selected column signal CS and the “H” level selected row signal RS. As a result, the selected bit line BLi and the selected word line WLi are in a state in which a voltage can be applied.

  For example, the unselected bit line BLx and the unselected word line WLx are set in an electrically floating state.

  At time t0, the control signal SEL is set to the “L” level, and the control signal WR is set to the “L” level.

  In the column side write circuit 13A, the “L” level control signal SEL is supplied to the inverter 137A, and the “L” level control signal WR is supplied to the inverter 137B.

  Inverter 137A outputs an “H” level signal to the gate of P-type transistor P1. The P-type transistor P1 is turned off by the “H” level signal.

  Inverter 137B outputs an “H” level signal to the gate of P-type transistor P2. The P-type transistor P2 is turned off by the “H” level signal.

  As a result, the voltage node of the column control circuit 11 is electrically isolated from the voltage terminals 199a and 199b.

  In the row side write circuit 13B, the voltage node 121 of the row control circuit 12 is electrically connected to the ground terminal 199d by the control signals WR and SEL at the “L” level.

  At time t1, the control circuit 18 changes the signal level of the control signal SEL from the “L” level to the “H” level. The signal level of the control signal WR is maintained at the “L” level.

  When the “H” level control signal SEL is supplied at time t1, the column side write circuit 13A operates as follows.

“H” level control signal SEL is supplied to inverter 137A.
The inverter 137A outputs an “L” level signal (an inverted signal of the “H” level signal SEL) to the gate of the P-type transistor P1.

  As a result, the voltage terminal 199a of the column side write circuit 13A is electrically connected to the voltage node 111 of the column control circuit 11.

  Inverter 137B outputs an “H” level signal to the gate of P-type transistor P2. The column control circuit 11 is electrically isolated from the voltage terminal 199b by the P-type transistor P2 in the off state.

  In this way, the voltage value Va is applied to the selected bit line BLi.

  In the low-side write circuit 13B, the OR gate 135 outputs an “H” level signal to the gate of the N-type transistor N2 in response to the “H” level control signal SEL and the “L” level control signal WR. As a result, the N-type transistor N2 is set to an on state.

  The voltage node 121 of the row control circuit 12 is electrically connected to the ground terminal 199d by the N-type transistor N2 in the on state.

  As a result, a voltage of 0V is applied to the selected word line WLi.

  Thus, at time t1, application of the write voltage VWR (switch voltage VSW) having the voltage value V1 is started. As described above, most of the write voltage VWR (voltage value Va) is applied to the selector element 200.

  By applying the voltage value Va, the resistance state of the selector element 200 in the selected cell MCi changes from the high resistance state to the low resistance state in the period TSEL from the time t1 to the time t2a.

  Thereby, the selector element 200 is set to an on state.

  At time t2a, the control circuit 18 changes the signal level of the control signal SEL from the “H” level to the “L” level.

  When the “L” level control signal SEL is supplied at time t1, the column side write circuit 13A operates as follows.

“L” level control signal WR is supplied to inverter 137A.
An “H” level signal is supplied from the inverter 137A to the P-type transistor P1. Therefore, the P-type transistor P1 is turned off. The P-type transistor P2 is also in an off state.

  As a result, the voltage node 111 of the column control circuit 11 is electrically isolated from the voltage terminals 199a and 199b.

  Thus, the application of voltage to the selected bit line BLi is temporarily stopped.

  In the low-side write circuit 13B, when the “L” level control signal SEL and the “L” level control signal WR are supplied, the N-type transistor N2 is in the ON state.

  Therefore, a voltage of 0 V is applied to the selected word line WLi by the N-type transistor N2 in the on state.

  As a result, the voltage applied to the selected cell is 0 V at time t2a during the write operation.

In a period TI from time t2a to time t2b, the signal levels of the control signals SEL and WR are maintained at the “L” level. The period TI is shorter than the period until the selector element 200 in a state where no voltage is applied switches from the on state to the off state.
Therefore, the selector element 200 maintains the on state during the period TI.

  At time t2b, the control circuit 18 changes the signal level of the control signal WR from the “L” level to the “H” level. The signal level of the control signal SEL is maintained at the “L” level.

  When the “H” level control signal WR is supplied at time t2b, the column side write circuit 13A operates as follows.

  “H” level control signal WR is supplied to inverter 137B. The inverter 137B supplies an “L” level signal to the gate of the P-type transistor P2. The P-type transistor P2 is turned on by the “L” level signal.

  As a result, the voltage node 111 of the column control circuit 11 is electrically connected to the voltage terminal 199b by the P-type transistor P2 in the on state.

  The P-type transistor P1 is turned off by the “H” level signal from the inverter 137A.

  As a result, the voltage Vb of the voltage terminal 199b is applied to the voltage node 111 of the column control circuit 11.

  When the “H” level control signal WR is supplied, the row side write circuit 13B operates as follows.

“H” level control signal WR and “L” level control signal SEL are supplied to OR gate 135. In response to the “H” level signal from the OR gate 135, the N-type transistor N2 is turned on.
The voltage node 121 of the row control circuit 12 is electrically connected to the ground terminal 199d by the N-type transistor N2 in the on state.

As described above, the column control circuit 11 applies the voltage Vb to the selected bit line BLi, and the row control circuit 12 applies the ground voltage VSS (0 V) to the selected word line WLi.
As a result, the potential difference Vb between the selected bit line BLi and the selected word line WLi is applied to the selected cell MCi.

  As described above, most of the write voltage VWR (voltage value Vb) is applied to the MTJ element 100 as the program voltage.

  At time t3, the signal level of the control signal WR is changed from the “H” level to the “L” level. The signal level of the control signal SEL is maintained at the “L” level.

  At time t3, the column side write circuit 13A operates as follows according to the control signals SEL and WR.

In response to the “L” level control signal WR, the inverter 137B supplies the “H” level signal to the gate of the P-type transistor P2. The P-type transistor P1 is turned off by the “H” level signal.
The voltage node 111 of the column control circuit 11 is electrically isolated from the voltage terminal 199b by the off-state P-type transistor P2 by the off-state P-type transistor.
Further, the voltage node 111 of the column control circuit 11 is electrically separated from the voltage terminal 199a by the P-type transistor P2 in the off state.

  As a result, the application of voltage from the column side write circuit 13A to the selected bit line BLi is stopped.

  At time t3, the row side write circuit 13B operates as follows according to the control signals SEL and WR.

  In response to the “L” level control signal WR and the “L” level control signal SEL, the OR gate 135 outputs an “H” level signal to the gate of the N-type transistor N2. The N-type transistor N2 is turned on by the “H” level signal.

  The voltage node 121 of the row control circuit 12 is electrically connected to the ground terminal 199d by the N-type transistor N2 in the on state.

  As a result, the ground voltage is applied from the row side write circuit 13B to the selected word line WLi.

  Thus, at time t3, the voltage applied to the selected cell becomes 0V.

  Therefore, the program voltage is applied to the selected cell in the period TMTJ from time t2b to time t3.

  As described above, write data is written to the MTJ element 100 in the selected cell MCi by applying the voltage value Vb in the application period TMTJ from time t2b to time t3.

  At time t4, the signal levels of the selection signals CS and RS are set to the “L” level. As a result, the column control circuit 11 deactivates the selected bit line BLi, and the row control circuit 12 deactivates the selected word line WLi. As a result, the selected cell is deactivated.

  As described above, the write operation of the MRAM of this embodiment is completed.

  As in this specific example, in the MRAM of the present embodiment, the write circuits 13A and 13B are configured so that the voltage is not applied to the selected cell MCi (or the switch between the switch voltage application period and the program voltage application period). A write voltage VWR including TI) can be generated.

(B-2) Specific example 2
A specific example 2 of the MRAM according to the present embodiment will be described with reference to FIGS.

  FIG. 27 is a voltage waveform diagram showing pulse waveforms of various voltages used in the write operation in the specific example 2 of the MRAM of the present embodiment.

  As shown in FIG. 27, when the write voltage VWR has an interval TI between the switch voltage and the program voltage, the unselected voltages VINH1 and VINH2 are applied to the unselected bit line BLx and the unselected word line WLx. May be.

  Thereby, the MRAM according to the second specific example of the present embodiment can suppress the malfunction of the non-selected cell during the write operation.

  FIG. 28 is an equivalent circuit diagram showing a configuration example of the write circuit of the MRAM of this embodiment.

  As shown in FIG. 28, the column side write circuit 13B further includes a P-type transistor P3 for outputting the non-selection voltage VINH1.

One end of the P-type transistor P3 is connected to the voltage terminal 199e. The other end of the P-type transistor P3 is connected to the voltage node 111 of the column control circuit 11. The gate of the P-type transistor P3 is connected to the output terminal of the inverter 139A.
A control signal INH1 is supplied to the input terminal of the inverter 139A.

  In this specific example, the row side write circuit 13B may be the same circuit as the circuit shown in FIG.

  As shown in FIG. 27, the start time of the rise of the non-selection voltages VINH1 and VINH2 is substantially the same as the time t1 of the start of the rise of the switch voltage in the write voltage VWR (for example, change from 0 V to the voltage value Va). Are set to the same timing.

  At time t1, the signal levels of the control signals INH1 and INH2 are changed from the “L” level to the “H” level. As a result, the P-type transistor P3 of FIG. 28 and the P-type transistor P4 of FIG. 20 are turned on.

  Therefore, the unselected voltages VINH1 and VINH2 are applied to the unselected bit line BLx and the unselected word line WLx.

  The start time of falling of the non-selection voltages VINH1 and VINH2 is set at substantially the same timing as the time t2a of the start of falling of the switch voltage VSW (for example, a change from the voltage value Va to 0V).

  At time t2a, the signal levels of the control signals INH1 and INH2 are changed from the “H” level to the “L” level. As a result, the P-type transistor P3 in FIG. 28 and the P-type transistor in FIG. 20 are turned off.

  Therefore, the application of the non-selection voltages VINH1 and VINH2 to the non-selected bit line BLx and the non-selected word line WLx is stopped.

  In this way, in the examples of FIGS. 27 and 28, the voltage values of the non-selection voltages VINH1 and VINH2 increase at time t1 and decrease at time t2a.

  As described above, specific example 2 of the MRAM according to the present embodiment can suppress an increase in power consumption due to the non-selection voltage when the non-selection voltage for preventing erroneous writing is used.

(B-3) Specific example 3
A specific example 3 of the magnetic MRAM according to the present embodiment will be described with reference to FIGS.

  FIG. 29 is a voltage waveform diagram of the write voltage and the non-select voltage in the write operation of the specific example 3 of the MRAM of the present embodiment.

  As shown in FIG. 29, the application timing of the non-selection voltages VINH1 and VINH2 may be different from the rising and falling timings of the switch voltage / program voltage included in the write voltage.

  In this specific example, the rise time ta of the non-selection voltages VINH1 and VINH2 is earlier than the rise time t1 of the switch voltage (write voltage VWR).

  The falling start time tb of the non-selection voltages VINH1 and VINH2 is later than the falling start time t2a of the switch voltage, and the start time of the rising of the program voltage (for example, a change from 0 V to the voltage value Vb). It is earlier than t2b.

  FIG. 30 is a voltage waveform diagram of the write voltage and the non-select voltage showing a modification of FIG.

  As shown in FIG. 30, only the rise start time ta of the non-selection voltages VINH1 and VINH2 may be different from the rise start time of the switch voltage (write voltage).

  Note that, contrary to FIG. 30, only the start time of the fall of the non-selection voltages VINH1 and VINH2 may be different from the start time of the fall of the switch voltage.

  FIG. 31 is a voltage waveform diagram of the write voltage and the non-select voltage showing a modification of FIG.

  As shown in FIG. 31, the time tb2 at which the non-selection voltages VINH1 and VINH2 start to fall may be later than the time t3 at which the program voltage starts to fall (change from the voltage value Vb to 0V).

  Specific example 3 of the MRAM of the present embodiment can increase the rising margin of the voltage pulse.

  As described above, the magnetic memory of the third embodiment can improve memory characteristics.

(4) Fourth embodiment
With reference to FIGS. 32 and 33, a magnetic memory (for example, MRAM) and a control method thereof according to the fourth embodiment will be described.

  In the present embodiment, the read operation of the MRAM of the above-described embodiment will be described.

  As described above, in the voltage-effect MTJ element, the polarity of the voltage for changing the magnetization arrangement state of the MTJ element from the P state to the AP state is the voltage for changing the magnetization arrangement state of the MTJ element from the AP state to the P state. The polarity is the same.

  In such a unipolar element, it may be desirable that the polarity of the read voltage is opposite to the polarity of the write voltage in order to suppress erroneous writing to the memory cell during the read operation.

  In this case, the selected word line is set to the high potential side and the selected bit line is set to the low potential side during the read operation, contrary to the relationship between the potentials of the bit line and the word line during the write operation. The

  FIG. 32 is a voltage waveform diagram showing the read voltage during the read operation of the MRAM of this embodiment.

  As shown in FIG. 32, in the first period TSEL of the pulse waveform of the read voltage VRD, the voltage value Vc is applied to the memory cell (selected cell) MC, and in the second period TRD following the first period TSEL. A second voltage value Vr lower than the first voltage value Vc is applied to the memory cell MC.

  The first voltage value Vc is a voltage value for setting the selector element 200 to the on state. For example, the voltage value Vc has substantially the same voltage value as the voltage value Va of the switch voltage in the write voltage VWR. The voltage value Vc is smaller than the magnetization reversal threshold value (for example, the voltage value Vb) of the MTJ element.

  The second voltage value Vr is a voltage value for determining the resistance state of the MTJ element 100. The voltage value Vr is a voltage value smaller than the magnetization reversal threshold value of the storage layer 101. In the present embodiment, a portion of the read voltage VRD having the voltage value Vr may be referred to as a determination voltage VDTM.

  For example, the determination of data in the selected cell MCi uses the sense amplifier circuit of the read circuits 14A and 14B to generate a current in a wiring (for example, a bit line) or to change a potential / current value of the wiring during the period TRD. It is executed by being detected. The determination result of the data in the selected cell MCi is obtained during the period TRD.

  FIG. 32 shows an example in which the magnitude of the voltage value Vc is larger than the magnitude of the voltage value Vr. However, according to the characteristics of the MTJ element 100 and the selector element 200, the voltage value Vc may be the same as the voltage value Vr, or the voltage value Vc may be smaller than the voltage value Vr. Also good.

  During the read operation, as in the write operation, most of the read voltage VRD is distributed to the selector element 200 during the period until the selector element 200 is set to the on state (the period from time tr to time tx). Pressed. Therefore, during the period from time tr to time tx, the inter-terminal voltage VSEL of the selector element 200 has the voltage value Vc.

  When the selector element 200 changes to the on state at time tx, most of the read voltage VRD is divided into the MTJ element 100. Therefore, in the period from time tx to ts, the terminal voltage VMTJ of the MTJ element 100 has the voltage value Vc. In the period from time ts to tt, the voltage VMTJ between terminals of the MTJ element 100 has a voltage value Vr.

  For example, the characteristics of the selector element 200 are designed so that the selector element 200 changes from an on state to an off state after time tt.

  FIG. 33 is a schematic diagram showing the potential state of the wiring in the memory cell array in the read operation of the MRAM of this embodiment.

  During the read operation of the MRAM, the column side read circuit 14A and the row side read circuit 14B in FIG. 2 apply the read voltage VRD to the selected cell MCi.

  As shown in FIG. 33, in the read operation for the selected cell MCi, a read voltage VRD having a certain voltage value is applied to the selected word line WLi, and a voltage of 0 V is applied to the selected bit line BLi.

  During the read operation, the selected word line WLi is set to the high potential side, and the selected bit line BLi is set to the low potential side.

  For example, the row side read circuit 14B applies a positive voltage to the selected word line WLi. The column side read circuit 14B applies a voltage of 0 V to the selected bit line BLi. A current (read current) flows in the selected cell MCi by the read voltage VRD. As a result, the selected cell MC outputs a signal (read signal).

  The column side read circuit 14B senses a read signal output from the selected cell MCi to the selected bit line BLi. The magnitude (for example, current value) of the read signal from the selected cell MCi changes according to the resistance state (magnetization arrangement state) of the MTJ element 100.

  Based on the sense result of the read signal of the selected cell MCi by the column side read circuit 14B (for example, the comparison result of the magnitude of the read signal), the data in the selected cell MCi is determined and read.

  By controlling the potentials of the selected bit line BLi and the selected word line WLi as shown in FIG. 33, the polarity of the voltage applied to the selected cell (MTJ element) MCi during the read operation is changed to the polarity of the voltage applied to the selected cell during the write operation. The opposite is true.

  In this embodiment, as in the read operation of FIG. 33, the state in which the voltage is applied to the MTJ element 100 so that the potential of the selected word line WLi is higher than the potential of the selected bit line BLi is negative. It is called a bias state.

  On the other hand, a state in which a voltage is applied to the MTJ element 100 so that the potential of the bit line becomes higher than the potential of the word line as in the write operation is called a positive bias state.

  For example, as shown in FIG. 9A, in the positive bias state, the reference layer 102 of the MTJ element 100 is set to the high potential side, and the storage layer 101 of the MTJ element 100 is set to the low potential side. In contrast, in the negative bias state, the reference layer 102 of the MTJ element 100 is set to the low potential side, and the storage layer 101 of the MTJ element 100 is set to the high potential side.

  As described above, the selector element 200 is a bipolar element. Therefore, even when the read voltage VRD in the positive bias state is applied to the memory cell MC, the selector element 200 can be set to the on state.

For example, the read circuits 14A and 14B set the unselected bit line BLx and the unselected word line WLx to an electrically floating state during the read operation.
When the non-selected bit line, BLx, and non-selected word line WLx are set in an electrically floating state during the read operation, the power consumption of the MRAM during the read operation can be reduced.

  Note that the read voltage VRD having the pulse shape of FIG. 35 can be generated by a circuit similar to the circuit configuration of the write circuit (for example, the circuit of FIG. 12). For example, the voltage value of the power supply terminal that outputs the determination voltage is set to the voltage value Vr, and the voltage value of the power supply terminal 199b of the circuit of FIG. Further, instead of the control signal WR, a control signal for controlling the output timing of the determination voltage is supplied to the circuit of FIG. Such circuits are included in the readout circuits 14A and 14B.

  For example, the read operation in the MRAM of the present embodiment can be applied to the prior read of the write operation.

  As described above, the magnetic memory of the fourth embodiment can execute a read operation.

(5) Fifth embodiment
With reference to FIGS. 34 and 35, a magnetic memory (for example, MRAM) and a control method thereof according to the fifth embodiment will be described.

  FIG. 34 is a diagram schematically showing the voltage application state of each wiring in the memory cell array during the read operation of the MRAM of this embodiment.

  As shown in FIG. 34, in the period TRD when the read voltage VRD is applied, the non-selection voltages VINHA and VINHb may be applied to the non-selection bit line BLx and the non-selection word line WLx.

  For example, during the read operation, the unselect voltages VINHA and VINHb are applied to the unselected bit line BLx and the unselected word line WLx by the read circuits 14A and 14B.

  FIG. 35 is a voltage waveform diagram of various voltages used in the read operation of the MRAM of this embodiment.

  As shown in FIG. 35, when the switch voltage is applied at the read voltage VRD (period TSEL), the voltage values of the non-selection voltages VINHA and VINHb are set to 0V. In the period TSEL, a voltage of 0 V is applied to the non-selected bit line BLx and the non-selected word line WLx. As a result, the selector element 200 of the non-selected cell MCx is not turned on and maintains the off state.

  Note that a voltage that is equal to or lower than the ON voltage (for example, the voltage value Vc) of the selector element 200 and greater than 0 V may be applied to the non-selected bit line BLx and the non-selected word line WLx in the period TSEL. .

  In the period TRD in which the voltage of the voltage value Vr is applied to the MTJ element 100, the unselected voltages VINH3 and VINH4 of the voltage value Vr are applied to the unselected bit line BLx and the unselected word line WLx.

  As a result, the potential difference between the selected word line WLi and the unselected bit line BLx and the potential difference between the unselected bit line BLx and the unselected word line WLx become 0V. Therefore, the current (output signal) from the selected word line shared cell and the current from the non-shared cell are reduced.

  Here, when a current flows through the non-selected cell MCx, the current from the non-selected cell MCx may be mixed with the read current flowing through the selected cell, and the read signal of the selected cell MCi may fluctuate.

  As the number of memory cells in the memory cell array increases, the total current from the plurality of non-selected cells increases. For this reason, when the storage density of the memory cell array increases, the read signal of the selected cell may deteriorate.

  As in the present embodiment, the unselected voltages VINH1 and VINH2 are applied to the unselected bit line BLx and the unselected word line WLx, thereby reducing the output signal (noise) from the unselected cell MCx.

  For example, the read operation in the MRAM of the present embodiment can be applied to the prior read of the write operation.

  As a result, the MRAM according to the present embodiment can suppress degradation of the read signal (read current) of the selected cell due to noise from the non-selected cell.

  As described above, the magnetic memory of the fifth embodiment can execute a read operation.

(6) Sixth embodiment
A magnetic memory (for example, MRAM) and a control method thereof according to the sixth embodiment will be described with reference to FIGS.

  As described above (see, for example, FIG. 14), when a voltage effect type MTJ element is used for a memory element, as a write sequence, before data is written to the MTJ element (inversion of magnetization of the storage layer), the memory cell MC The data stored in is determined by pre-reading.

  In the MRAM of this embodiment, the pre-read and write operations are executed using a series of voltage pulses. As a result, the switch of the selector element in the memory cell is made common between the pre-read and write operations, and only one time is required.

  As a result, the MRAM according to the present embodiment can shorten the period of the write sequence and improve the operation speed of the memory.

  Hereinafter, the write sequence of the MRAM according to the present embodiment will be described more specifically.

(A) Basic example
FIG. 36 is a voltage waveform diagram showing voltages used in the write operation of the MRAM of this embodiment.

  36 shows the voltage waveform of the write voltage VWR, the voltage waveform of the voltage applied to the selected word line WLi, and the voltage waveform of the voltage applied to the selected bit line BLi.

  As shown in FIG. 36, the setting of the ON state of the selector element 200 and the application of the read voltage are executed before the application of the program voltage of the voltage value Vb.

As described above, in the MRAM of this embodiment, the voltage effect type MTJ element operates as a unipolar memory element.
Therefore, the setting of the ON state of the selector element 200 and the reading operation with respect to the MTJ element 100 are executed using a voltage having a polarity opposite to the polarity of the program voltage VPGM. Since selector element 200 is a bipolar element, selector element 200 can be set to an on state even when a voltage is applied to a selected cell in a negative bias state.

  At the time of setting the ON state of the selector element 200 and applying the read voltage, the selected word line WLi is set to the high potential side so that the bias state of the MTJ element 100 becomes a negative bias state, and the selected bit line BLi is Set to the low potential side.

  In the period TSEL from the time tr, the voltage of the voltage value Vc is applied to the selected word line WLi. In the period TSEL, a voltage of 0 V is applied to the selected bit line BLi. By the application of the voltage value Vc, the selector element 200 is set to the ON state at a certain time tx in the period TSEL.

  At time ts after time tx, the potential of the selected word line WLi is lowered, and the voltage value of the selected word line WLi is set to the voltage value Vr. Depending on the characteristics of the selector element 200 and the MTJ element 100, the voltage value of the selected word line WLi may be increased to a voltage value Vc or higher.

  In a period TRD from time ts, the selected bit line BLi is applied with a voltage of 0V. In the period TRD, the determination voltage having the voltage value Vr is applied to the MTJ element 100 in the negative bias state. Thereby, the data in the selected cell MCi is determined in the period TRD. When the data in the selected cell MCi is different from the write data, the program voltage VPGM is applied after the read voltage VRD is applied.

  At time tt, the voltage value of the selected word line WLi is reduced from the voltage value Vr to 0V. At time tt, the voltage value of the selected bit line BLi is increased from 0V to the voltage value Vb. As a result, the program voltage having the voltage value Vb is applied to the MTJ element 100 in the positive bias state.

  At time tu, the voltage value of the selected bit line BLi is decreased from the voltage value Vb to 0V. A period TMTJ from time tt to time tu corresponds to the length of a half cycle of the precession of magnetization of the storage layer 101 (period from time t2 to time t3 in FIG. 11).

  As a result, a program voltage having a pulse width (period) TMTJ from time tt to time tu is applied to the MTJ element 100. Thereby, in the MTJ element 100 of the selected cell MCi, the magnetization of the storage layer 101 is reversed.

  The characteristics of the selector element 200 are designed such that the selector element 200 changes from the on state to the off state after time tu. The selector element 200 continues to be in the on state during the period from time ts to time tt.

  When the data in the selected cell MCi is the same as the write data, the write sequence ends without applying the program voltage VPGM after applying the read voltage VRD.

  The on / off control of the selector element 200 and the application of the read voltage VRD may be executed by the read circuits 14A and 14B, or may be executed by the write circuits 13A and 13B.

  As described above, in the MRAM according to the present embodiment, the pre-read and write operations (program operations) are continuously executed by the write voltage having a pulse waveform in which the read voltage and the program voltage are continuous.

(B) Modification
A modification of the MRAM of this embodiment will be described with reference to FIG.

  FIG. 37 is a voltage waveform diagram showing the voltage waveform of the write voltage, the voltage waveform of the selected bit line, and the voltage waveform of the selected word line in a modification of the MRAM of this embodiment.

  In the example of FIG. 36, the start time of the fall of the voltage value of the selected word line WLi is set to the same time as the start time of the rise of the voltage value of the selected bit line BLi.

  As shown in FIG. 37, the start time of the fall of the voltage value of the selected word line WLi may be later than the rise timing of the voltage value of the selected bit line BLi.

  For example, at time tu, the voltage value of the selected word line WLi is decreased from the voltage value Vr to 0 V simultaneously with the start of the fall of the voltage value of the selected bit line BLi.

  In this case, in the period TMTJ, the voltage value of the selected word line WLi is maintained at the voltage value Vr.

  Accordingly, the voltage value of the selected bit line BLi in the period TMTJ is set to the sum (Vb + Vr) of the magnetization reversal threshold value Vb of the MTJ element 100 and the voltage value Vr of the read voltage.

(C) Specific example
A specific example of the MRAM of this embodiment will be described with reference to FIGS.

  When a write voltage in which a read voltage and a program voltage are continuous is applied to the selected cell, the non-select voltage may be applied to the non-selected bit line and the non-selected word line.

  FIG. 38 is a voltage waveform diagram showing the voltage waveform of the write voltage, the voltage waveform of the selected / unselected bit line, and the voltage waveform of the selected / unselected word line in an example of the MRAM of this embodiment. is there.

  As shown in FIG. 38, when the write voltage VWR is applied, the non-selection voltage VINHa is applied to the non-selection bit line BLx, and the non-selection voltage VINHb is applied to the non-selection word line WLx.

  At time tr, the application of the non-selection voltages VINHA and VINHb to the non-selected bit line BLx and the non-selected word line WLx is substantially the same as the timing at which the voltage Vc (for example, Vc = Va) is applied to the selected word line WLi. At the same time.

  For example, in the period TSEL (from time tr to time ts), the voltage value of the unselected bit line BLx is set to the voltage value Via, and the voltage value of the unselected word line WLx is set to the voltage value Vib.

In the period TSEL, the voltage value Via is applied to the memory cell between the selected bit line BLi and the unselected word line WLx in a negative bias state with respect to the MTJ element 100.
The voltage value Via-Vc is applied to the memory cell between the unselected bit line BLx and the selected word line WLi.

In the period TRD, the voltage value of the unselected bit line BLx is set to the voltage value Vr, and the voltage value of the unselected word line WLx is set to the voltage value Vr.
As in the example of FIG. 38, the malfunction of the selector element 200 and the deterioration of the read margin are suppressed by applying the voltage to the unselected bit line BLx and the unselected word line WLx.

  FIG. 39 is a voltage waveform diagram of the write voltage, selected / unselected bit line, and selected / unselected word line of the MRAM, showing an example different from the specific example of FIG.

  In the example shown in FIG. 39, in the period TSEL, the unselected voltage VINHa having the voltage value Via is applied to the unselected bit line BLx, and the unselected voltage VINHb having the voltage value Vib is applied to the unselected word line WLx. .

  In the pre-read period TRD and the program voltage application period TMTJ, the voltage values of the unselected bit lines BLx and the unselected word lines WLx are set to 0V.

  Here, as shown in FIG. 38 and FIG. 39, the voltage applied to the selected bit line shared cell has a voltage value Via during the period when the voltage in which the selected cell is in the negative bias state is applied. The applied voltage has a voltage value Vc−Vib, and the voltages applied to the other non-selected cells have a voltage value Via−Vib.

  For example, when the voltage values Via and Vib are set to about half the voltage value Vc (Vc / 2), the applied voltage to the non-selected cell between the non-selected bit line and the non-selected word line is 0V. Become. In this case, the power consumption generated in the memory cell array 10 can be reduced.

  The voltage value Via is set to about two thirds of the voltage value Vc (2Vc / 3), and the voltage value Vib is set to about one third of the voltage value Vc (Vc / 3). In this case, the voltage value of the applied voltage for all the non-selected cells is about the voltage value Vc / 3. In this case, even if there is a variation in the switch voltage among the plurality of selector elements 200 in the memory cell array 10, the malfunction of the selector element 200 is suppressed.

  In the present embodiment, the potential state of the unselected bit line BLx and the unselected word line WLx may be set to an electrically floating state during a write operation.

(D) Summary
In the magnetic memory of this embodiment, in the write sequence for the memory cell including the voltage effect type MTJ element, the pre-read and the program voltage are continuously executed by sharing the ON operation of the selector element.

  Therefore, the magnetic memory of this embodiment can shorten the period of the pre-read and write operations. As a result, the magnetic memory of this embodiment can speed up the write operation (write sequence).

  As described above, the magnetic memory of the sixth embodiment can improve memory characteristics.

(7) Seventh embodiment
With reference to FIG. 40, the magnetic memory (for example, MRAM) of 7th Embodiment is demonstrated.

In the above-described embodiment, the case where the polarity of the read voltage is opposite to the polarity of the write voltage (program voltage) has been described.
On the other hand, in the MRAM of this embodiment, the polarity of the read voltage is set to be the same as the polarity of the write voltage. As a result, the MRAM of this embodiment can easily control the application of voltage to the wiring in the memory cell array, and can simplify the circuit design of the read circuit and the write circuit.

  FIG. 40 is a voltage waveform diagram showing the applied voltage to the selected cell and the applied voltage to the wiring in the memory cell array in the write sequence of the MRAM of this embodiment.

As shown in FIG. 40, the switch voltage VSW is applied to the selected cell MCi in the period TSEL of the write sequence. A voltage having a positive voltage value Va is applied to the selected bit line BLi, and a voltage of 0 V is applied to the selected word line WLi.
Thereby, the selector element 200 is set to an on state.

In the period TRD, the read voltage VR is applied to the selected cell MCi. A voltage having a positive voltage value Vr is applied to the selected bit line BLi, and a voltage of 0 V is applied to the selected word line WLi.
By pre-reading, the data holding state in the selected cell is determined.

  When data is written to the selected cell MCi based on the result of pre-reading, the program voltage VPGM is applied to the selected cell MCi in the period TMTJ. A voltage having a positive voltage value Vb is applied to the selected bit line BLi, and a voltage of 0 V is applied to the selected word line WLi.

  Thus, when the polarity of the read voltage is the same as the polarity of the program voltage, a voltage of 0 V is applied to the selected word line during the write sequence.

  If the magnetization of the MTJ element is not reversed based on the result of the pre-reading, a voltage of 0 V is applied to the selected bit line BLi in the period TMTJ.

  As in this embodiment, even if the polarity of the voltage applied to the MTJ element at the time of pre-reading is the same as the polarity of the voltage applied to the MTJ element at the time of the program operation, the MRAM of this embodiment Reading and programming operations can be executed continuously.

  Note that, as in the MRAM of this embodiment, even when a write operation in which a pre-read and a program operation are continuously performed in a positive bias state, the non-select voltage is applied to the non-select bit line and the non-select word line. It may be applied. In addition, during the write operation of the MRAM of this embodiment, the unselected bit line and the unselected word line may be set in an electrically floating state.

  As described above, the magnetic memory of the seventh embodiment can simplify the internal configuration of the circuit.

(8) Eighth embodiment
With reference to FIGS. 41 to 47, a magnetic memory (for example, MRAM) of the eighth embodiment will be described.

  The MRAM according to the embodiment performs a verify operation on the selected cell in order to verify whether or not predetermined data is written in the selected cell after the application of the write voltage.

  In the verify operation, data is read from the selected cell after application of the write voltage. It is verified whether or not the read data matches the write data.

  As described above, the switching probability of the voltage effect MTJ element depends on the pulse width of the program voltage. When the memory cell array has a large storage capacity, the voltage pulse shape may be distorted from an ideal shape due to parasitic components of the wiring. Along with this, there is a possibility that the error occurrence rate related to data writing increases.

  As in this embodiment, in order to suppress data write errors, it is desirable to execute an operation (for example, a verify operation) for confirming the success or failure of data write after application of a program voltage.

  The verify operation is executed by substantially the same operation as the read operation (pre-read).

(A) Basic example
FIG. 41 is a flowchart for explaining the write sequence of the MRAM according to the present embodiment.

  As shown in FIG. 41, a program voltage is applied to the MTJ element based on the result of pre-reading (step ST3).

  After application of the program voltage, a verify operation is executed (step ST4).

  Based on the result of the verify operation, it is determined whether or not the data write to the selected cell has been verified (step ST5).

  If the data write does not pass the verify pass (when the program operation fails), the program operation is executed again. In the re-program operation when the verify pass is not performed, at least one of the magnitude of the pulse width TMTJ and the voltage value of the program voltage may be changed.

  The program voltage application and the verify operation are repeatedly performed until the data writing to the selected cell is verified.

  When the data write is a verify pass (when the write operation is successful), the write operation is completed.

  If the result of the verify pass is not obtained even when the program voltage is applied a predetermined number of times, the selected cell may be changed to another memory cell.

  FIG. 42 is a voltage waveform diagram showing applied voltages to the selected cells in the write sequence of the MRAM of this embodiment.

  FIG. 42 shows voltage waveforms of the write voltage, the applied voltage of the selected bit line, and the applied voltage of the selected word line in the write sequence of the MRAM of this embodiment.

  As shown in FIG. 42, the pre-read, program operation, and verify operation are executed using a series of voltage pulses. Thereby, the switch of the selector element in the selected cell is made common in each operation. Therefore, it is only necessary that the selector element is set once in the write sequence. Therefore, the MRAM of this embodiment can speed up the write sequence.

  In the write voltage of FIG. 42, similar to the example of FIG. 36, after the pre-read is executed in the negative bias state, the program voltage is applied to the selected cell MCi in the positive bias state.

  At time tt, the voltage value of the selected word line WLi is lowered from the voltage value Vr to 0V. When the program voltage is applied (during the period TMTJ), the voltage value of the selected word line WLi is maintained at 0V.

  After the program voltage VPGM is applied, a verify operation is performed.

For the verify operation, the selected cell MCi is set to a negative bias state.
At time tu of the period TVF for the verify operation, the voltage value of the selected word line WLi is set to the voltage value Vr and the voltage value of the selected bit line BLi is set to 0 V, substantially in the same manner as in the previous read. Is done.

  As a result, a read current flows in the selected cell MCi in the negative bias state. A read signal is output from the selected cell MCi.

  At time tv, the voltage value of the selected word line WLi is reduced from the voltage value Vr to 0V.

  Thus, the data of the selected cell is read in the period TVF. The success or failure of data writing is determined based on the result of the read operation after application of the program voltage.

  Based on the determination result, completion of the write operation or application of the program voltage again is determined.

  When the program operation is executed again based on the result of the verify operation, the pulse-shaped write voltage shown in FIG. 42 is applied to the selected cell. However, the switch voltage VSW and the program voltage VPGM (for example, the write voltage in FIG. 11) may be applied to the selected cell MCi without applying the read voltage (voltage value Vr) for pre-reading.

  The selector element 200 is designed so as to be set to an off state after the time tv. The selector element 200 continues to be in the on state in the period TRD, the period TMTJ, and the period TVF.

  FIG. 43 is a voltage waveform diagram of applied voltages to the bit lines and the word lines in the write sequence of the MRAM of this embodiment, showing a modification of FIG.

  As shown in FIG. 43, in the application period TMTJ of the program voltage VPGM, the voltage value of the selected word line WLi may be maintained at the voltage value Vr.

  Thereby, in the MRAM in the example of FIG. 43, the number of times of controlling the potential of the selected word line WLi is reduced. As a result, the MRAM of this embodiment using the operation example of FIG. 43 can simplify the control of the write operation.

  In this case, the voltage value applied to the MTJ element 100 is applied to the selected bit line BLi during the program operation (period from time tt to time tu) so that the voltage value is equal to or higher than the magnetization reversal threshold value. The voltage value of the voltage is set so as to have the sum (Vb + Vr) of the voltage value Vb and the voltage value Vr.

(B) Specific example
A specific example of the MRAM of this embodiment will be described with reference to FIGS.

  In this embodiment, a non-selection voltage may be applied to the non-selected bit line and the non-selected word line.

  FIG. 44 is a voltage waveform diagram of applied voltages to the bit lines and the word lines in the write sequence of the MRAM according to the embodiment.

  As shown in FIG. 44, the unselected voltage VINH1 is applied to the unselected bit line BLx, and the unselected voltage VINH2 is applied to the unselected word line WLx.

  In the period TSEL (time tr to time ts), the voltage value of the unselected bit line BLx and the voltage value of the unselected word line WLx are set to 0V. In the period TSEL, a voltage of 0 V is applied to the non-selected cell and the selected bit line shared cell, and a voltage of the voltage value Vc is applied to the selected word line shared cell.

  At time ts, the voltage value of the unselected bit line BLx and the voltage value of the unselected word line WLx are increased from 0 V to the voltage value Vr.

  In the period TRD, the voltage values (absolute values) of the non-selection voltages VINH1 and VINH2 are set to the voltage value Vr. Thereby, in the pre-read period TRD, a voltage of 0 V is applied to the non-shared cell and the selected word line shared cell.

  At time tt, the voltage value of the unselected bit line BLx and the voltage value of the unselected word line WLx are reduced from the voltage value Vr to 0V.

  In a period TMTJ from time tt to time tu, a program voltage having a voltage value Vb is applied to the selected cell MCi. In the period TMTJ, the voltage values (absolute values) of the non-selection voltages VINH1 and VINH2 are 0V.

  At time tu, the voltage value of the unselected bit line BLx and the voltage value of the unselected word line WLx are increased from 0V to the voltage value Vr.

  At time tv, the voltage value of the unselected bit line BLx and the voltage value of the unselected word line WLx are decreased from the voltage value Vr to 0V.

  In the period TVF from time tu to time tv, the voltage values (absolute values) of the non-selection voltages VINH1 and VINH2 are set to the voltage value Vr.

  Thus, a voltage of 0 V is applied to the non-shared cell and the selected word line shared cell in the period TVF during the verify operation.

  As described above, the MRAM in the example of FIG. 44 suppresses deterioration of the read margin.

  FIG. 45 is a voltage diagram showing an example of a pattern of applied voltages to the bit line and the word line in the write sequence of the MRAM of this embodiment.

  As shown in FIG. 45, a voltage value (absolute value) greater than 0V may be applied to the unselected bit line BLx and the unselected word line WLx in the switch period TSEL of the selector element.

  In the period TSEL, the non-selection voltage VINH1 has a voltage value Vi1. The voltage value Vi1 is applied to the non-selected bit line BLx. The non-selection voltage VINH2 has a voltage value Vi2. The voltage value Vi2 is applied to the unselected word line WLx.

  Here, substantially in the same manner as in the examples of FIGS. 38 and 39, when the voltage values Vi1 and Vi2 are about the voltage value Vc / 2, an increase in power consumption in the memory cell array 10 can be suppressed.

  Further, when the voltage value Vi1 is set to about 2Vc / 3 and the voltage value Vi2 is set to about Vc / 3, malfunction of the selector element 200 can be suppressed.

  FIG. 46 is a voltage waveform diagram of each voltage for explaining a modification of FIG.

  As shown in FIG. 46, when the program voltage is applied to the selected cell MCi, the potentials of the unselected bit line BLx and the unselected word line WLx may be maintained at the voltage value Vr.

  47 is a voltage waveform diagram of each voltage for explaining a modification of FIG.

  As shown in FIG. 47, even when a positive voltage value is applied to the non-selected bit line BLx and the non-selected word line WLx in the period TSEL in which the selector element 200 is set to the on state, At the time of voltage application, the voltage value of the voltage applied to the non-selected bit line BLx and the voltage value of the voltage applied to the non-selected word line WLx may be set to the voltage value Vr.

  Note that during the write operation of the MRAM of this embodiment, the unselected bit lines and the unselected word lines may be set in an electrically floating state.

(C) Summary
In the magnetic memory of this embodiment, the verify operation is executed after the program operation.

  Thereby, the magnetic memory of this embodiment can improve the reliability of data writing.

  In the magnetic memory according to the present embodiment, in the write sequence, the pre-read, the program voltage, and the verify operation are continuously executed by sharing the ON operation of the selector element. Thereby, the magnetic memory of this embodiment can speed up the write operation (write sequence).

  As described above, the magnetic memory of the eighth embodiment can improve the memory characteristics.

(9) Ninth embodiment
With reference to FIG. 48, a magnetic memory (for example, MRAM) and a control method thereof according to the ninth embodiment will be described.

  FIG. 48 is a voltage waveform diagram showing an example of the pulse waveform of the write voltage in the MRAM of this embodiment.

  As shown in FIG. 48, the voltage bias state for the selected cell in the pre-read and verify operations may be the same as the voltage bias state for the selected cell in the program operation.

  For example, during the pre-read and verify operations, the read voltage VRD is applied to the selected cell in a positive bias state.

  As a result, in the MRAM of the present embodiment, the selected bit line BLi is set to the high potential side and the selected word line WLi is set to the low potential side during the pre-read and verify operations.

  As described in the seventh embodiment, the polarity of the voltage applied to the selected cell for the pre-read and verify operations is set to be the same as the polarity of the voltage applied to the selected cell for the program operation. As a result, the MRAM of this embodiment only needs to set the potential of the selected word line WLi to 0 V throughout the write sequence.

  As in this embodiment, even if the polarity of the voltage applied to the MTJ element during the pre-read and verify operations is the same as the polarity of the voltage applied to the MTJ element during the program operation, The MRAM can continuously execute the pre-read, program operation, and verify operation.

  Even when a read operation (determination of the resistance state of the MTJ element) is performed on the MTJ element in the positive bias state, a non-select voltage is applied to the non-selected bit line and the non-selected word line. Good. In addition, during the write operation of the MRAM of this embodiment, the unselected bit line and the unselected word line may be set in an electrically floating state.

  As described above, the magnetic memory of the ninth embodiment can improve the memory characteristics.

(10) Other
In the above-described embodiment, a memory device using a magnetoresistive effect element as a memory element is illustrated. However, the above-described embodiment may be applied to a memory device (for example, a resistance change type memory) using a variable resistive element other than the magnetoresistive effect element as a memory element.

  In the above-described embodiment, the example in which the bit line is set to the high potential side and the word line is set to the low potential side during the write operation has been described. However, in the magnetic memory (or resistance change type memory) of the present embodiment, the bit line during the write operation depends on the connection relationship between the memory element (for example, magnetoresistive element) and the selector element with respect to the bit line and the word line. May be set on the low potential side, and the word line may be set on the high potential side.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  1: magnetic memory, 100: magnetoresistive effect element, 200: selector element, MC: memory cell.

The magnetic memory of this embodiment has a first wiring, a second wiring, a first magnetoresistance effect element, and a first resistance state or a second resistance state lower than the first resistance state. And a first memory cell connected between the first wiring and the second wiring, and a write voltage for writing data to the first memory cell. And a circuit applied to the first memory cell. The write voltage includes a first voltage , a second voltage, and a third voltage . The voltage value of the first voltage is lower than the voltage value of the second voltage and higher than the voltage value of the third voltage. The first period during which the first voltage is applied to the first memory cell is longer than the second period during which the second voltage is applied to the first memory cell. After the first voltage is applied to the first memory cell, the second voltage is applied to the first memory cell, before application of the first voltage, and application of the second voltage. Later, the third voltage is applied to the first memory cell.

The magnetic memory of this embodiment has a first wiring, a second wiring, a first magnetoresistance effect element, and a first resistance state or a second resistance state lower than the first resistance state. A first memory cell connected between the first wiring and the second wiring, and a write voltage for writing data in the first memory cell, And a circuit applied to the first memory cell. The write voltage includes a first voltage, a second voltage, and a third voltage. The voltage value of the first voltage is lower than the voltage value of the second voltage and higher than the voltage value of the third voltage. The first voltage changes the first selector element from the first resistance state to the second resistance state, and the second voltage controls the magnetization of the first magnetoresistance effect element. . The first period during which the first voltage is applied to the first memory cell is longer than the second period during which the second voltage is applied to the first memory cell. After the first voltage is applied to the first memory cell, the second voltage is applied to the first memory cell, before application of the first voltage, and application of the second voltage. Later, the third voltage is applied to the first memory cell.

Claims (11)

A first wiring;
A second wiring;
A first magnetoresistive element, and a first selector element having a first resistance state or a second resistance state lower than the first resistance state, wherein the first wiring and the second A first memory cell connected to the wiring;
A circuit for applying a write voltage for writing data to the first memory cell to the first memory cell;
Comprising
The write voltage includes a first voltage and a second voltage;
The voltage value of the first voltage is lower than the voltage value of the second voltage,
The first period during which the first voltage is applied to the first memory cell is longer than the second period during which the second voltage is applied to the first memory cell,
After the first voltage is applied to the first memory cell, the second voltage is applied to the first memory cell;
Magnetic memory. The first voltage is a voltage for changing the first selector element from the first resistance state to the second resistance state,
The second voltage is a voltage for controlling the magnetization of the first magnetoresistive element.
The magnetic memory according to claim 1. The circuit applies a third voltage lower than the second voltage to the first memory in order to determine data in the first memory cell before writing data to the first memory cell. Applied to the cell,
The third voltage is applied to the first memory cell within a third period between the first period and the second period.
The magnetic memory according to claim 1 or 2. When the third voltage is applied, the potential of the second wiring is higher than the potential of the first wiring,
When the second voltage is applied, the potential of the first wiring is higher than the potential of the second wiring;
The magnetic memory according to claim 3. At the time of applying the first voltage, the potential of the second wiring is higher than the potential of the first wiring;
The magnetic memory according to claim 4. When applying the third voltage, the potential of the first wiring is higher than the potential of the second wiring;
When the second voltage is applied, the potential of the first wiring is higher than the potential of the second wiring;
The magnetic memory according to claim 3. The circuit applies a fourth voltage to the first memory cell after the data write to the first memory cell in order to verify the result of the data write to the first memory cell;
The fourth voltage is applied to the first memory cell after application of the second voltage.
The magnetic memory according to claim 1. In a fourth period between the first period and the second period, a fifth voltage lower than the first voltage is applied to the first memory cell;
The fourth period is shorter than a period during which the first selector element changes from the second resistance state to the first resistance state.
The magnetic memory according to claim 1 or 2. The first magnetoresistance effect element includes a first magnetic layer, a second magnetic layer, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer,
The first magnetic layer is connected to the first wiring, and the second magnetic layer is connected to the second wiring;
The magnetic memory according to claim 1. The first selector element includes a first electrode, a second electrode, and a first layer between the first electrode and the second electrode,
The first layer includes an insulating layer or a semiconductor layer,
The magnetic memory according to claim 1. A magnetoresistive effect element including a first magnetic layer, a second magnetic layer, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer;
A selector element including a first electrode, a second electrode, and a first layer between the first electrode and the second electrode, the selector element connected in series to the magnetoresistive element;
A write circuit that outputs a write voltage including a first voltage and a second voltage to the magnetoresistive element and the selector element;
Comprising
The voltage value of the first voltage is lower than the voltage value of the second voltage,
The first period during which the first voltage is output is longer than the second period during which the second voltage is output,
After the first voltage is output, the second voltage is output.
Magnetic memory.