CN105047225A - Nonvolatile memory write protection circuit capable of avoiding rewriting - Google Patents
Nonvolatile memory write protection circuit capable of avoiding rewriting Download PDFInfo
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Abstract
The invention belongs to the technical field of the semiconductor memory, and particularly relates to a nonvolatile memory write protection circuit capable of avoiding rewriting. The write protection circuit structure comprises a storage bit, a data control logic module, two column selection transistors, two write access control transistors, two preread control transistors, a current source, a comparator, a latch, a write driving circuit and a write control signal generation circuit, wherein the storage bit is constructed by two units; the data control logic module is used for deciding to open a write access of a left unit or a right unit of the two units according to data to be written; the two column selection transistors are controlled by the same column selection signal; the grid electrodes of the two write access control transistors are independently controlled by a write control signal; the grid electrodes of the preread control transistors are independently controlled by a read control signal; and the write control signal generation circuit inputs a write enable signal and outputs a preread control signal and a write control signal. The invention also puts forwards a write operation flow which aims at a one-time programming memory which constructs the storage bit on the basis of double storage cells, can avoid malicious or unintentional rewriting damage and provides a high-safety storage scheme for sensitive data.
Description
Technical field
The invention belongs to semiconductor memory technologies field, be specifically related to a kind of nonvolatile memory write-protect circuit, particularly a kind of write-protect circuit preventing distorting for one-time programming nonvolatile memory.
Background technology
Information age, provide easily simultaneously to people in infotech, also bring a severe problem, that is exactly information security, especially the safety issue of sensitive data, and wherein the safe storage of sensitive data is the key ensureing security.
Semiconductor memory uses the data assemblies of 0 or 1 to store information, and each memory device unit of composition mass storage can store data (0 or 1).Usually, whether continue storage with the data of power down background storage and judge in memory, storer can be divided into volatile memory and nonvolatile memory, and wherein after nonvolatile memory power down, data can continue to keep.Because most of sensitive data needs permanent storage, therefore in the nonvolatile memory stored in systems in which more.Therefore from the angle of nonvolatile memory write circuit, preventing sensitive data from being rewritten destruction becomes key issue.
Wherein, one-time programming storer (One-timeProgrammable, OTP) technology, owing to it is characterized in that single programming operation, namely just can not again programme after first time programming, it is irreversible that this state changes, make it have certain advantage preventing rewriting, be generally used for storing various types of sensitive data and security information, such as key, equipment Serial Number, manufacture indicate, and other sensitive data etc.
But assailant may write to distort destruction again, or accidental maloperation can cause rewriting destruction.Owing to usually storing very key message in these otp memories, data are rewritten destruction and system works can be brought abnormal.Therefore propose to prevent the write-protect technology of the non-volatile otp memory of malice rewriting or accidentally maloperation rewriting necessary.
In the prior art, US Patent No. 7817456B2 proposes a kind of write-protect circuit engineering for masking film program ROM, as shown in Figure 1.A programming lock-in circuit 102, forbids again programming to destroy data to programmed storage line.This patent for be the write-protect of masking film program ROM changed from antifuse (Antifuse) OTP memory cell.Masking film program transistor 112,113,114 etc. is had in programming lock-in circuit 102, once whole storer is by after masking film program, these masking film program transistors are also in conducting state, the wordline of masking film program ROM is connected to ground by controlling transistor 115, thus the high voltage programming signal that circuit for producing high voltage 101 produces is bypassed, avoid the write again to program storage row.
Due to the write-protect that this technology is for masking film program ROM, and be not suitable for otp memory.Because after mask transistor is got through by the fabrication phase, the full line be connected with mask transistor all can not write.And OTP retains user in operational phase also ability once able to programme, its dirigibility is much higher than masking film program ROM, therefore can not adopt the method will write voltage and mask completely in this patent.
Along with the development of novel memory devices, such as resistance-variable storing device, phase transition storage, ferroelectric memory, magnetic store etc., more and more become the potentiality replacer in nonvolatile memory field.Use above-mentioned novel memory devices to realize otp memory, to store the data with higher-security, become a key areas.In prior art, China Patent Publication No. CN1764982A, CN1795512A etc. propose the technology being built bank bit by the double memory cell of novel memory devices, to improve anti-technological fluctuation ability and the operational reliability of storer, in the carried bank bit based on two unit, if one is in conducting state, one is in non-conducting state, then can normal storage 0 or 1, if two unit are in identical state, then think store invalid data.
Chinese patent CN102169719A proposes the method realizing otp memory on the basis based on two cell formation bank bit, as shown in Figure 2, wherein 204 is the bank bits built by two variable-resistance memory unit, 203 is column selection siphunculus arrays, 201 is write driver module, 202 is data control logics, is 1 or 1 according to input data, selects to apply program voltage to BL or BL_.In bank bit 204, two storage unit are initially non-conducting state.If input data are 1, apply voltage to BL, then the left storage unit in bank bit 204 is programmed to conducting state, and right storage unit remains on non-conducting state, and definable is now stored as 0; If input data are 0, apply voltage to BL_, then the right storage unit in bank bit 204 is programmed to conducting state, and left storage unit remains on non-conducting state, and definable is now stored as 1.In this structure, the reset write being programmed for non-conducting state from conducting state is driven and remove, thus make the position being stored as 0 can not be stored as 1 instead, thus achieve OTP function.
But, if to bank bit by programming, again malice or be not intended to write contrary data, then can destroy the content of this bank bit.Such as, if bank bit 204 is programmed for 1, namely left storage unit is programmed for conducting state, right storage unit remains on non-conducting state, if now write startup write operation to be again programmed for 0, right storage unit then can be made to be programmed for conducting state, and left storage unit is also conducting state, the data of this bank bit 204 will be destroyed, and become invalid bit.
Therefore, need the write-protect technology proposing a kind of OTP for two unit bank bit realization, prevent data by malice or be not intended to rewrite destruction.
Summary of the invention
The technical problem to be solved in the present invention is, proposes a kind of write-protect circuit of the nonvolatile memory for one-time programming, can realize the write-protect by turn to one-time programming storer, prevents malice or rewrites unintentionally.
The write-protect circuit preventing the nonvolatile memory distorted that the present invention proposes, mainly for the write-protect circuit of one-time programming storer being made up of the memory construction of a bank bit two unit, its circuit structure, as shown in Figure 3, comprise: current source 311, bank bit 301, data control logic 304, comparer 310, write driving circuit 307, control signal produces circuit 313, latch Latch312, also comprise: two column selection transistors: the first transistor 302, transistor seconds 303, two control transistor: third transistor 306, transistor 4 305, two pre-read control transistor: the 5th transistor 308, the 6th transistor 309, wherein:
(1) described bank bit 301, comprise a left storage unit 321, right storage unit 322, described left storage unit 321 and right storage unit 322 control by same row selection signal, and when row selection signal is effective, left storage unit 321 and right storage unit 322 are chosen simultaneously;
Described left storage unit 321 and right storage unit 322, be all in non-conducting state when original state, and now, bank bit 301 possesses the ability of disposable programmable.
Described left storage unit 321 and right storage unit 322, wherein, one is programmed and is in conducting state, when another is in non-conducting state, can normal storage Bit data position.Such as, if left storage unit 321 be conducting state, right storage unit 322 is non-conducting state, then think and store data 0, otherwise, then think and store data 1.If left storage unit 321 and right storage unit 322 are in conducting state simultaneously, then what think storage is invalid data.
Described left storage unit 321, right storage unit 322, can be built by the various non-volatile memory device stored based on high low resistance, such as, can be the structures such as variable-resistance memory unit, phase-change memory cell, ferroelectric storage cell, magnetic cell, its conducting state and non-conducting state represent low resistance state and high-impedance state respectively.
Described left storage unit 321, right storage unit 322, it can be the storage unit of other type, comprise electricity erasing electric programming read-only memory (EEPROM), flash memory (Flash) etc., described conducting state and non-conducting state represent the physical state that its floating gate charge is programmed and is wiped free of respectively.
Described left storage unit 321, right storage unit 322, wherein can comprise gate transistor.
(2) described two column selection transistors: the first transistor 302, transistor seconds 303, its grid controls by same array selecting signal, and when array selecting signal is effective, the first transistor 302 and transistor seconds 303 are opened by selection simultaneously; The first transistor 302 and transistor seconds 303 are connected on the right bit line BL_R at the left bit line BL_L at left storage unit place, right storage unit place respectively.
(3) described data control logic module 304, its input one is write data, input two is from writing driving circuit 307, through series connection third transistor 306, the 4th transistor 305 write drive singal, exporting one is connect the first transistor 302, left bit line BL_L, and exporting two is meet transistor seconds 303, right bit line BL_R; Its function is, is 0 or 1 according to write data, selects to write drive singal and passes to left bit line BL_L or right bit line BL_R.
(4) described two pre-read control transistor: the 5th transistor 308, the 6th transistor 309, and its grid all controls by pre-read control signal PreRD, when pre-read control signal PreRD is effective, and the 5th transistor 308 and all conductings of the 6th transistor 309; Described 5th transistor 308 is as switch, and one end is connected to left bit line BL_L, and the other end is connected to and pre-reads voltage signal Vpre node; Described 6th transistor 309 is as switch, and one end is connected to right bit line BL_R, and the other end is connected to and pre-reads voltage signal Vpre node.
(5) described current source 311, it provides fixed current to export, and is applied to and pre-reads on voltage signal Vpre node; When pre-read control signal PreRD is effective, its electric current exports and is applied on left bit line BL_L and right bit line BL_R through the 5th transistor 308, the 6th transistor 309.
(6) described comparer 310, its input one pre-reads voltage signal Vpre, and input two is reference voltage Vref, if Vpre>Vref, then exports high level, if Vpre<Vref, then output low level.
(7) described latch Latch312, its input is the output of comparer 310, and its output is the Output rusults Vcom of the comparer 310 after latching.
The combination of described comparer and latch, can share with the comparer in the normal read circuits of storer and latch, to save area overhead.
(8) described two control transistor: third transistor 306, the 4th transistor 305, and wherein, the 4th transistor 305 controls by the output Vcom of latch Latch312, when Vcom is high level, 4th transistor 305 is opened, and when Vcom is low level, limbs pipe 305 is closed; Third transistor 306 controls by write control signal Wctrl, and when Wctrl is high level, third transistor 306 is opened, and when Wctrl is low level, third transistor 306 is closed.
The order of connection of described 4th transistor 305 and third transistor 306 can be exchanged.
Described 4th transistor 305 and third transistor 306 can be nmos transistor switches, also can be complementary cmos transmission gate switches.
(9) driving circuit 307 is write described in, for generation of the drive singal left storage unit 321 or right storage unit 322 being carried out to write operation, through third transistor 306, the 4th transistor 305, mathematical logic control module 304, the first transistor 302 and transistor seconds 303, be applied on bank bit 301, according to the control of mathematical logic control module 304, determine that voltage is specifically applied in left storage unit 321 or right storage unit 322.
(10) described control signal produces circuit 313, and its input is write enable signal WE, and it exports one is pre-read control signal PreRD, and one is write control signal Wctrl; Its function is, when write enable signal WE is effective, first generates PreRD effective, opens pre-read phase, after obtaining pre-reading result, closes PreRD effectively, opens write control signal Wctrl signal, start to carry out write operation.Namely pre-read control signal is effective, effective early than write control signal, and pre-read control signal invalid while, make write control signal effective.
Based on circuit structure proposed by the invention, its write operation and write-protect flow process are as shown in Figure 4, specific as follows:
(1) step 401: write enable WE effective, write operation starts;
(2) step 402: pre-read control signal PreRD is effective;
(3) step 403: the electric current of current source 311 is applied in left storage unit 321 in parallel and right storage unit 322;
(4) step 404: comparer 310 multilevel iudge pre-reads the height of voltage Vpre and reference voltage Vref;
(5) if Vpre is greater than Vref, then enter programming flow process, specifically comprise:
Step 405: now show that left storage unit 321 and right storage unit 322 are all in non-conducting state, this bank bit 301 was not programmed;
Step 406: it is high level that comparator results obtains Vcom after latch, the 4th transistor 305 is opened;
Step 407: pre-read control signal PreRD is invalid subsequently, and Wctrl is effective;
Step 408: write path and open, bank bit 301 is programmed;
(6) if Vpre is less than Vref, then enter write-protect flow process, specifically comprise:
Step 409: now show that left storage unit 321 and right storage unit 322 have one to be in conducting state, this bank bit was programmed;
Step 410:Vcom is low level, and switch the 4th transistor 305 is closed;
Step 411: pre-read signal PreRD is invalid, and Wctrl is effective;
Step 412: write path obstructed, can not programme to bank bit 301, is in the write-protect state preventing from rewriting.
Technique effect of the present invention is, for the one-time programming storer building bank bit based on double memory cell, proposing the write-protect ability that can prevent from deliberating or rewrite unintentionally destruction, providing the storage scheme of high security for storing sensitive data.
Accompanying drawing explanation
Fig. 1 is a kind of write-protect circuit in prior art.
Fig. 2 is a kind of one-time programming reservoir designs based on two unit bank bit in prior art.
Fig. 3 is the write-protect circuit structure that the present invention proposes.
Fig. 4 is write operation and the write-protect flow process that the present invention proposes write-protect circuit.
Fig. 5 is the embodiment that the present invention proposes write-protect circuit structure.
Embodiment
Below in conjunction with embodiment, the specific embodiment of the present invention is described in further detail.
Fig. 5 be the present invention put forward a kind of embodiment of structure, for the storer based on variable-resistance memory unit 5, wherein bank bit 501, comprise a left storage unit 521, right storage unit 522, left storage unit 521 and right storage unit 522 are the 1T1R structure that a variable-resistance memory unit (ResistiveMemory) and a nmos pass transistor (Transistor) are connected.The grid of the transistor of wherein said left storage unit 521 and right storage unit 522 inside controls by same row selection signal, and when row selection signal is effective, in left storage unit 521 and right storage unit 522, the grid of transistor is chosen simultaneously.
Variable-resistance memory unit Ra in described left storage unit 521, the variable-resistance memory unit Rb in storage unit 522, be all in non-conducting state (high-impedance state) when original state, bank bit 501 possesses the ability of disposable programmable.
Variable-resistance memory unit Ra in described left storage unit 521 and right storage unit 522 and Rb, when one of them be in conducting state (i.e. low resistance state), one be in non-conducting state (i.e. high-impedance state) time, energy normal storage Bit data position, if the resistive element Ra in such as left storage unit 521 is the resistive element Rb in conducting state (i.e. low resistance state), right storage unit 522 is non-conducting state (i.e. high-impedance state), then think and store data 0, otherwise, then think and store data 1.If the variable-resistance memory unit Ra in left storage unit 521 and right storage unit 522 and Rb is in conducting state (i.e. low resistance state) simultaneously, then think that what store is invalid data.
Data control logic module 504 comprises transmission gate 1, transmission gate 2 533, phase inverter 531, latch two latch534.Write data, after latch534 latches, are connected to the control end of transmission gate 1; Through latch534 latch write data after phase inverter 531 is anti-phase, be connected to the control end of transmission gate 2 533.
Write driving circuit 507 and produce programming drive singal, by being subject to the transistor switch 506 of write control signal Wctrl control, by the transistor switch 505 pre-reading result Vcom control, being connected to the input end of transmission gate 532 and transmission gate 533 in data control logic module 504.
When write data are 1, transmission gate 1 is opened, and transmission gate 2 533 is closed, and when Wctrl and Vcom is effective, that writes driving circuit 507 generation writes drive singal through column selection transistor 502, is applied in left storage single 521.When write data are 0, transmission gate 1 is closed, and transmission gate 2 533 is opened when Wctrl and Vcom is effective, and that writes driving circuit 507 generation writes drive singal through column selection transistor 503, is applied in right storage unit 522.
Pre-reading circuit controls transistor 508 by pre-reading, transistor 509, current source 511, comparer 510, latch 512 are formed, wherein the grid of transistor 508 and transistor 509 controls by pre-read control signal PreRD jointly, wherein transistor 508 is as switch, its one end is connected to left bit line BL_L, transistor 509 is as switch, and its one end is connected to left bit line BL_L.And transistor 508 and transistor 509 link together as the other end of switch, namely pre-read voltage Vpre signal node.Generate fixing pre-read current by current source 511 to be applied to and to pre-read in voltage Vpre signal node.An input of comparer 510 pre-reads voltage Vpre signal node, and another input end is reference voltage Vref.The output of comparer 510, after latch Latch512 latches, generates Vcom signal, for controlling the switch of transistor 505.
When the resistive element Ra in left storage unit and right storage unit and Rb is all in non-conducting state (i.e. high-impedance state), pre-reads voltage Vpre higher, be designated as Vpreh; As the resistive element Ra in left storage unit and right storage unit and Rb, one of them is in conducting state, when another is in non-conducting state, pre-reads voltage Vpre lower, is designated as Vprel; The centre chosen between Vpreh and Vprel of reference voltage Vref.
Control signal produces circuit 513, and its input is write enable signal WE, and its output is pre-read control signal PreRD and write control signal Wctrl.Each write operation is triggered by WE signal, and write operation is divided into pre-read phase, write phase by according to effective situation of pre-read signal PreRD and write control signal Wctrl.Can the result Vcom that pre-read phase generates will determine writing drive singal and being applied on bank bit 501 of write phase; if Vcom is high level; show that bank bit 501 is not yet programmed; still there is the ability allowing one-time programming; if Vcom is low level; show that bank bit 501 is programmed, write drive singal and cannot be applied on bank bit 501, the bank bit 501 be programmed thus can be protected to exempt from and again write destruction.
Although the description of this invention is made in the mode of reference example, cognition is arrived by those skilled in the art, without departing from the scope and spirit in the present invention, can make change in form or details.
Claims (10)
1. the write circuit of a nonvolatile memory: it is characterized in that comprising: current source, bank bit, data control logic module, comparer, write driving circuit, control signal produces circuit, latch Latch, also comprise: two column selection transistors: the first transistor, transistor seconds, two control transistor: third transistor, the 4th transistor four; Two pre-read control transistor: the 5th transistor, the 6th transistor, wherein:
(1) described bank bit, comprise a left storage unit, a right storage unit, described left storage unit and right storage unit control by same row selection signal;
Described left storage unit and right storage unit, when to be in non-conducting state simultaneously, described bank bit is in original state; When one is programmed and is in conducting state, when another is in non-conducting state, bank bit normal storage Bit data position; When left storage unit and right storage unit are in conducting state simultaneously, then what bank bit stored is invalid data;
(2) described two column selection transistors: the first transistor, transistor seconds, its grid controls by same array selecting signal; The first transistor and transistor seconds are connected on the right bit line at the left bit line at left storage unit place, right storage unit place respectively;
(3) described data control logic module, its input one is write data, and input two is from writing driving circuit, through the third transistor of series connection, the 4th transistor write drive singal, export one and connect the first transistor, left bit line, export two and connect transistor seconds, right bit line; Its function is, is 0 or 1 according to write data, selects to write drive singal and passes to left bit line or right bit line;
(4) described two pre-read control transistor: the 5th transistor, the 6th transistor, and its grid all controls by pre-read control signal PreRD; Described 5th transistor is as switch, and one end is connected to left bit line, and the other end is connected to and pre-reads voltage signal Vpre node; Described 6th transistor is as switch, and one end is connected to right bit line, and the other end is connected to and pre-reads voltage signal Vpre node;
(5) described current source, it provides fixed current to export, and is applied to and pre-reads on voltage signal Vpre node; When pre-read control signal PreRD is effective, its electric current exports and is applied on left bit line and right bit line through the 5th transistor, the 6th transistor;
(6) described comparer, its input one pre-reads voltage signal Vpre, and input two is reference voltage Vref, if Vpre>Vref, then exports high level, if Vpre<Vref, then output low level;
(7) described latch Latch, its input is the output of comparer, and its output is the Output rusults Vcom of the comparer after latching;
(8) described two control transistor: third transistor, the 4th transistor, and wherein, the 4th transistor gate controls by the output Vcom of latch Latch; Third transistor grid controls by write control signal Wctrl;
(9) driving circuit is write described in, for generation of the drive singal left storage unit or right storage unit being carried out to write operation, through third transistor, the 4th transistor, mathematical logic control module, the first transistor and transistor seconds, be applied on bank bit, according to the control of mathematical logic control module, determine that voltage is specifically applied in left storage unit or right storage unit;
(10) described control signal produces circuit, and its input is write enable signal WE, and it exports one is pre-read control signal PreRD, and another is write control signal Wctrl; Its function is, write enable signal WE effectively, first generates PreRD effective, opens pre-read phase, after obtaining pre-reading result, closes PreRD effectively, opens write control signal Wctrl signal, start to carry out write operation.
2. the write circuit of nonvolatile memory according to claim 1, it is characterized in that left storage unit and right storage unit, built by the various non-volatile memory device stored based on high low resistance, comprise the storage unit that resistance-variable storing device, phase transition storage, ferroelectric memory or magnetic store build, its conducting state and non-conducting state represent low resistance state and high-impedance state respectively.
3. the write circuit of nonvolatile memory according to claim 1, it is characterized in that left storage unit and right storage unit, also comprise electricity erasing electric programming read-only memory, flash memory, described conducting state and non-conducting state represent the physical state that its floating gate charge is programmed and is wiped free of respectively.
4. the write circuit of nonvolatile memory according to claim 1, is characterized in that left storage unit and right storage unit, also comprises gate transistor.
5. the write circuit of nonvolatile memory according to claim 1, is characterized in that comparer, is voltage comparator, namely compares the comparer of two input terminal voltage sizes, or current comparator, namely compares the comparer of two input end size of current.
6. the write circuit of nonvolatile memory according to claim 1, is characterized in that comparer and latch, shares with the comparer in the normal read circuits of storer and latch.
7. the write circuit of nonvolatile memory according to claim 1, is characterized in that control signal produces circuit, wherein, pre-read control signal effective, effective early than write control signal, and pre-read control signal invalid while, make write control signal effective.
8. the write circuit of nonvolatile memory according to claim 1, is characterized in that the order of connection of third transistor and the 4th transistor four is exchanged.
9. the write circuit of nonvolatile memory according to claim 1, is characterized in that third transistor and the 4th transistor are nmos transistor switches, or complementary cmos transmission gate switch.
10., based on a memory write operation method for the write circuit of nonvolatile memory described in claim 1, it is characterized in that concrete steps are:
The first step, to write enable WE effective, and write operation starts;
Second step, pre-read control signal PreRD are effective;
The electric current of the 3rd step, current source is applied in left storage unit in parallel and right storage unit;
4th step, comparer multilevel iudge pre-read the height of voltage Vpre and reference voltage Vref;
If the 5th step Vpre is greater than Vref, then enters programming flow process, specifically comprise:
(1) now show that left storage unit and right storage unit are all in non-conducting state, this bank bit was not programmed;
(2) comparator results obtains Vcom after latch is high level, and the 4th transistor is opened;
(3) pre-read control signal PreRD is invalid subsequently, and Wctrl is effective;
(4) write path to open, bank bit is programmed;
If the 5th step Vpre is less than Vref, then enters write-protect flow process, specifically comprise:
(1) now show that left storage unit and right storage unit have one to be in conducting state, this bank bit was programmed;
(2) comparator results obtains Vcom after latch is low level, and switch the 4th transistor is closed;
(3) pre-read signal PreRD is invalid, and Wctrl is effective;
(4) write path obstructed, can not programme to bank bit, be in the write-protect state preventing from rewriting.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107123443A (en) * | 2016-02-24 | 2017-09-01 | 三星电子株式会社 | Disposable programmable memory and its method for writing data |
| CN108109662A (en) * | 2016-11-24 | 2018-06-01 | 北京兆易创新科技股份有限公司 | A kind of gating circuit switch and the memory comprising the circuit |
| CN112071356A (en) * | 2020-08-14 | 2020-12-11 | 上海华虹宏力半导体制造有限公司 | Margin measuring circuit of multi-time programmable EEPROM unit |
| CN116758963A (en) * | 2023-07-04 | 2023-09-15 | 北京中电华大电子设计有限责任公司 | Write voltage driving circuit for nonvolatile memory and nonvolatile memory |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101359502A (en) * | 2008-07-24 | 2009-02-04 | 复旦大学 | Storage scheme for novel high-density multi-value phase change memory |
| CN102169719A (en) * | 2010-02-25 | 2011-08-31 | 复旦大学 | One time programmable (OTP) resistive random access memory (RRAM) as well as read-write circuit and programming method thereof |
-
2015
- 2015-07-14 CN CN201510410979.4A patent/CN105047225B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101359502A (en) * | 2008-07-24 | 2009-02-04 | 复旦大学 | Storage scheme for novel high-density multi-value phase change memory |
| CN102169719A (en) * | 2010-02-25 | 2011-08-31 | 复旦大学 | One time programmable (OTP) resistive random access memory (RRAM) as well as read-write circuit and programming method thereof |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107123443A (en) * | 2016-02-24 | 2017-09-01 | 三星电子株式会社 | Disposable programmable memory and its method for writing data |
| CN107123443B (en) * | 2016-02-24 | 2020-10-27 | 三星电子株式会社 | One-time programmable memory and data writing method thereof |
| CN108109662A (en) * | 2016-11-24 | 2018-06-01 | 北京兆易创新科技股份有限公司 | A kind of gating circuit switch and the memory comprising the circuit |
| CN112071356A (en) * | 2020-08-14 | 2020-12-11 | 上海华虹宏力半导体制造有限公司 | Margin measuring circuit of multi-time programmable EEPROM unit |
| CN112071356B (en) * | 2020-08-14 | 2023-04-28 | 上海华虹宏力半导体制造有限公司 | Margin measuring circuit of multiple-time programmable EEPROM unit |
| CN116758963A (en) * | 2023-07-04 | 2023-09-15 | 北京中电华大电子设计有限责任公司 | Write voltage driving circuit for nonvolatile memory and nonvolatile memory |
| CN116758963B (en) * | 2023-07-04 | 2024-05-14 | 北京中电华大电子设计有限责任公司 | Write voltage driving circuit for nonvolatile memory and nonvolatile memory |
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