CN103680590B - The I/O circuit of SRAM - Google Patents
The I/O circuit of SRAM Download PDFInfo
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- CN103680590B CN103680590B CN201210339320.0A CN201210339320A CN103680590B CN 103680590 B CN103680590 B CN 103680590B CN 201210339320 A CN201210339320 A CN 201210339320A CN 103680590 B CN103680590 B CN 103680590B
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Abstract
The invention discloses the I/O circuit of a kind of SRAM, including the input circuit electrically connected with sense amplifier in SRAM and output circuit.Wherein, input circuit includes: positive input circuit, for receiving an input signal, and provides the input signal flowing through described positive input circuit；And anti-phase redundancy replicates input circuit, for receiving described input signal and carrying out anti-phase process simultaneously.Output circuit includes: positive output circuit, for receiving the output signal of a pair complementation that sense amplifier sends, and exports the output signal flowing through described positive output circuit；Anti-phase redundancy replicates output circuit, for receiving described output signal with described positive output circuit and carrying out anti-phase process simultaneously.The invention enables the signal flowing through the duplicate circuit of redundancy and original input and output circuit contrary and then complementary, so overall, the signal intensity trend flowing through I/O circuit is stable, and then can effectively prevent the outside power consumption analysis attack to SRAM.
Description
Technical field
The present invention relates to chip secure field, particularly to one for SRAM(StaticRAM, static random read-write memory) prevent the I/O(input/output of power consumption analysis attack) circuit.
Background technology
In recent years, the problem that safety issue has become as the overriding concern of multi-chip design perhaps.Particularly with those based on the equipment having designed by the algorithm of certain rule for, the risk of stolen internal related data becomes more and more higher.Such as some low side processors, induction apparatus and smart card etc. use the product of certain operations rule, and the problem of its safety is faced with the biggest danger, the most wide variety of contactless smart card.
Along with the range of application of smart card progressively expands, the requirement to the problem of safety is more and more higher, does not require nothing more than the safety ensureing data etc., and power consumption to be reduced, cost-effective.The aspect threatening the safety of smart card is a lot, mainly have logical attack, physical attacks, bypass attack, to the attack etc. in terms of transmission, especially power consumption analysis attack (the PAA in bypass attack, PowerAnalysisAttack), being easily achieved, the safety to smart card has the biggest threat.Therefore the research for power consumption analysis attack is always the focus of smart card security Study on Problems.
SRAM is the important component part in all kinds of chips such as smart card, and it primarily serves the purpose of data storage.Including realizing circuit and leaking the information of the aspects such as some operation times, electromagnetic radiation, power consumption in running of the various smart cards of SRAM and all kinds of chip, through this category information, can be analyzed obtaining the sensitive data in the chips such as smart card or key etc., this method is referred to as bypass attack (SCA, SideChannelAttacks).The bypass attack wherein utilizing power consumption information is referred to as power consumption analysis attack, the method can low cost, quickly, nondestructively extract the critical datas such as key in crypto chip, the safety to smart card constitutes huge threat.
The countermeasure taked currently for power consumption analysis attack mainly has two broad aspect, software approach and hardware approach, and the research of majority concentrates in the application of software aspects.Software approach is mainly by the power consumption to a certain system, and at random or relatively other part keeps consistent.But these software approachs generally are directed to specific algorithm and design, range of application is not wide, and has the biggest performance sacrifice, if there being the most senior attacking ways, these countermeasures then can more be prone to be broken.Hardware approach, is primarily referred to as using self synchronous double rail logic unit, dynamically or differential logic unit etc..However, these methods sacrifice the biggest performance indications equally, these methods may bring more risk worse, such as, make system be easier to suffer timing attacks etc., and these methods are not that the safety of memorizer is considered as first.It addition, also having some hardware approach is to account for from structural level, this renaming random for depositor or be processed to instruction all to make power consumption analysis attack become difficulty at instruction window.But these methods are not appropriate for low side processor because these low side processors not have depositor renaming machine-processed or do not have big instruction window to realize executing out.
Therefore, for being directed to power consumption analysis attack, the I/O(input/output of existing SRAM) necessity that could be improved of modular circuit.
Summary of the invention
In view of this, the present invention provides the I/O circuit of a kind of SRAM, effectively to prevent power consumption analysis attack, and the safety of the data that protection is transmitted by described I/O circuit.
The technical scheme of the application is achieved in that
A kind of I/O circuit of SRAM, including input circuit and output circuit, wherein:
Described input circuit includes:
Positive input circuit, for receiving an input signal, and provides the input signal flowing through described positive input circuit；It includes input, outfan and reset terminal；Its input is used for receiving described input signal；Its outfan flows through the input signal of described positive input circuit for output；Its reset terminal is for receiving one first reset signal before often receiving an input signal, to reset；
Anti-phase redundancy replicates input circuit, for receiving described input signal with described positive input circuit and described input signal being carried out anti-phase process simultaneously；It includes input, outfan and reset terminal；Its input is used for receiving described input signal；Its outfan flows through described anti-phase redundancy for output and replicates the described rp input signal of input circuit；Its reset terminal, for before often receiving an input signal, receives described first reset signal with described positive input circuit, to reset simultaneously；
Described output circuit includes:
Positive output circuit, for receiving the output signal of a pair complementation that sense amplifier sends, and exports the output signal flowing through described positive output circuit；It includes first input end, the second input, outfan and reset terminal；Its first input end and the second input are for receiving the output signal of the pair of complementation；Its outfan flows through the output signal of described positive output circuit for output；Its reset terminal is for receiving one second reset signal before often receiving the output signal of a pair complementation, to reset；
Anti-phase redundancy replicates output circuit, for receiving the output signal of the pair of complementation with described positive output circuit and carrying out anti-phase process simultaneously；It includes first input end, the second input, outfan and reset terminal；Its first input end and the second input are for receiving the output signal of the pair of complementation；Its outfan flows through described anti-phase redundancy for output and replicates the described reversed-phase output signal of output circuit；Its reset terminal, for before often receiving the output signal of a pair complementation, receives described second reset signal with described positive output circuit, to reset simultaneously.
Further, described positive input circuit includes:
First not circuit, its input as the input of described positive input circuit to receive described input signal；
Transmission gate circuit, its input connects the outfan of described first not circuit；
OR-NOT circuit, its first input end connects the outfan of described transmission gate circuit, its second input is as the reset terminal of described positive input circuit, receiving described first reset signal before often receiving an input signal at described positive input circuit, its outfan flows through the input signal of described positive input circuit as the outfan of described positive input circuit to provide；
Second not circuit, its input connects the outfan of described OR-NOT circuit, and its outfan connects the first input end of described OR-NOT circuit.
Further, described anti-phase redundancy duplication input circuit includes:
3rd not circuit, for receiving described input signal with described positive input circuit and described input signal being carried out anti-phase process simultaneously, its input replicates the input of input circuit to receive described input signal as described anti-phase redundancy；
First replicates not circuit, and its input connects the outfan of described 3rd not circuit；
Copy transmissions gate circuit, its input connects the described first outfan replicating not circuit；
Replicate OR-NOT circuit, its first input end connects the outfan of described copy transmissions gate circuit, its second input replicates the reset terminal of input circuit as described anti-phase redundancy, receiving described first reset signal to replicate before input circuit often receives an input signal in described anti-phase redundancy with described positive input circuit, its outfan replicates the outfan of input circuit as described anti-phase redundancy simultaneously；
Second replicates not circuit, and its input connects the outfan of described duplication OR-NOT circuit, and its outfan connects the first input end of described duplication OR-NOT circuit.
Further, described transmission gate circuit includes:
One nmos pass transistor, its drain electrode connects the outfan of described first not circuit, and its source electrode connects the first input end of described OR-NOT circuit, and its grid receives one first clock control signal；
One PMOS transistor, its drain electrode connects the outfan of described first not circuit, and its source electrode connects the first input end of described OR-NOT circuit, and its grid receives a second clock control signal.
Further, described copy transmissions gate circuit includes:
One replicates nmos pass transistor, and its drain electrode connects the described first outfan replicating not circuit, and its source electrode connects the first input end of described duplication OR-NOT circuit, and its grid receives described first clock control signal；
One replicates PMOS transistor, and its drain electrode connects the described first outfan replicating not circuit, and its source electrode connects the first input end of described duplication OR-NOT circuit, and its grid receives described second clock control signal.
Further, described first clock control signal and second clock control signal are the clock control signal of a pair complementation.
Further:
Described first replicate not circuit and the first not circuit be manufacture under the conditions of same process there is mutually isostructural not circuit；
Described copy transmissions gate circuit and transmission gate circuit be manufacture under the conditions of same process there is mutually isostructural transmission gate circuit；
Described duplication OR-NOT circuit and OR-NOT circuit be manufacture under the conditions of same process there is mutually isostructural OR-NOT circuit；
Described second replicate not circuit and the second not circuit be manufacture under the conditions of same process there is mutually isostructural not circuit.
Further, described positive output circuit includes:
First NAND gate circuit, its first input end connects described sense amplifier as the first input end of described positive output circuit, to receive the first output signal in the output signal of the pair of complementation；
Second NAND gate circuit, its first input end connects the outfan of described first NAND gate circuit, its second input connects described sense amplifier as the second input of described positive output circuit, with the second output signal in the output signal of the pair of complementation of reception, its the 3rd input is as the reset terminal of described positive output circuit, with often receive a pair complementation at described positive output circuit output signal before receive described second reset signal, its outfan connects the second input of described first NAND gate circuit；
Not circuit, its input connects the outfan of described second NAND gate circuit, and its outfan, as the outfan of described positive output circuit, flows through the output signal of described positive output circuit with output.
Further, described anti-phase redundancy duplication output circuit includes:
First replicates NAND gate circuit, and the second input that its first input end replicates output circuit as described anti-phase redundancy connects described sense amplifier, to receive the second output signal in the output signal of the pair of complementation；
Second replicates NAND gate circuit, its first input end connects the described first outfan replicating NAND gate circuit, the first input end that its second input replicates output circuit as described anti-phase redundancy connects described sense amplifier, with the first output signal in the output signal of the pair of complementation of reception, its the 3rd input replicates the reset terminal of output circuit as described anti-phase redundancy, before replicating, in described anti-phase redundancy, the output signal that output circuit often receives a pair complementation, receive described second reset signal with described positive output circuit simultaneously, its outfan connects the described first the second input replicating NAND gate circuit；
Replicating not circuit, its input connects the described second outfan replicating NAND gate circuit, and its outfan replicates the outfan of output circuit as described anti-phase redundancy, flows through described anti-phase redundancy with output and replicates the output signal of output circuit.
Further:
Described first replicate NAND gate circuit and the first NAND gate circuit be manufacture under the conditions of same process there is mutually isostructural NAND gate circuit；
Described second replicate NAND gate circuit and the second NAND gate circuit be manufacture under the conditions of same process there is mutually isostructural NAND gate circuit；
Described duplication not circuit and not circuit be manufacture under the conditions of same process there is mutually isostructural not circuit.
Can be seen that from such scheme, the I/O circuit of SRAM of the present invention, the duplicate circuit of redundancy is both increased in input and output circuit part, and in the duplicate circuit of redundancy, the signal flowed through is carried out anti-phase process so that the signal flowing through the duplicate circuit of redundancy and original input and output circuit is contrary and then complementary.So, overall, the signal intensity trend flowing through I/O circuit is stable, or will not be captured to the change of " 0 " by outer bound pair signal by " 1 " by " 0 " to " 1 " because of signal, and then can effectively prevent the outside power consumption analysis attack to SRAM.Because the I/O circuit of the present invention uses the duplicate circuit of redundancy, the most compared with prior art it is also easy to realize, and increased cost is the least.
Accompanying drawing explanation
Fig. 1 is the conceptual schematic view of the I/O circuit of SRAM of the present invention；
Fig. 2 is the structural representation of the I/O circuit of SRAM of the present invention；
Fig. 3 is the circuit diagram of the input circuit in the I/O circuit of SRAM of the present invention；
Fig. 4 is the circuit diagram of the output circuit in the I/O circuit of SRAM of the present invention.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearer, develop simultaneously embodiment referring to the drawings, is described in further detail the present invention.
Because power consumption analysis attack reaches to steal the change of the electric current caused when the purpose of data, i.e. signal change mainly by the method for change surveying electric current.If able to make the change of electric current keep consistent, then this attack just cannot be implemented.As it is shown in figure 1, be the concept map of the I/O circuit of SRAM of the present invention.
Power consumption analysis attack utilizes the change of electric current to steal data, i.e. when data occur " 0 " to " 1 " or " 1 " to cause the instantaneous change of electric current big to the transformation of " 0 ", its representative data can be judged according to the frequency of the size of electric current or change.Therefore, as it is shown in figure 1, in order to avoid the generation of this situation, present inventive concept is for compensate electric current, the frequency making " 0 " to " 1 " and " 1 " change to " 0 " is always consistent, so just cannot analyze out its representative data from outside according only to the change of electric current.As in Fig. 1, present inventive concept is, on the basis of original I/O circuit, first increase the I/O circuit RI/O of a redundancy, and the data contrary with original I/O circuit (as represented in Fig. 1) of the I/O circuit RI/O input of this redundancy with a not circuit；Simultaneously, it is also added with reset signal reset, data were all reset once before upper once new data arrives, not only ensure that Q end keeps consistent with the output of Q end " 0 " to " 1 " with the number that " 1 " to " 0 " changes, more making the data that cannot judge flowed through I/O circuit from outside is to maintain or change.It should be noted that the not actual circuit diagram of Fig. 1, not circuit therein is also not offered as the actual not circuit used, and in actual circuit diagram, various ways can be used to realize the anti-phase of data, and Fig. 1 is only to understand idea of the invention figure.
Specifically, as in figure 2 it is shown, the I/O circuit of the SRAM of the present invention, that includes input circuit 1 and output circuit 2 two parts.
Wherein, input circuit 1 further comprises positive input circuit 11 and anti-phase redundancy replicates input circuit 12.The effect of positive input circuit 11 is to receive input signal Din, and input signal D flowing through positive input circuit 11 self is providedout, specifically, input signal D in input circuit 1outThe outfan of residing input circuit 1 connects column select circuit (YMUX), and then is connected to sense amplifier (SA, SenseAmplifier) circuit after described column select circuit；And the effect that anti-phase redundancy replicates input circuit 12 is to provide input signal D provided with positive input circuit 11outContrary a kind of inversion signal, specifically, anti-phase redundancy replicates input circuit 12 and receives described input signal D with positive input circuit 11 simultaneouslyinAnd described input signal carries out anti-phase process and then produces the inversion signal contrary with positive input circuit 11, and the inverted redundancy of output stream replicates the rp input signal D of input circuit 12out-, wherein, anti-phase redundancy replicates the rp input signal D in input circuit 12out-Residing anti-phase redundancy replicates the outfan floating (floating) of input circuit 12.Such as when flowing through the data of described positive input circuit 11 for " 0 ", the data flowing through described anti-phase redundancy duplication input circuit 12 are " 1 ", and when flowing through the data of described positive input circuit 11 for " 1 ", flowing through described anti-phase redundancy and replicating the data of input circuit 12 is " 0 ".
Positive input circuit 11 includes input, outfan and reset terminal；Its input is used for receiving described input signal Din；Its outfan flows through described input signal D of described positive input circuit 11 for outputout(by the signal of the I/O circuit input of the present invention during the input signal of indication is SRAM circuit in the present invention, the most i.e. flow through the signal of input circuit, wherein input signal DinExpression is in the input signal of the input of described input circuit 1, input signal DoutRepresent the input signal of the outfan being in described positive input circuit 11 after flowing through positive input circuit 11)；Its reset terminal is for often receiving input signal DinReceive one first reset signal reset1, to reset before.
Anti-phase redundancy replicates input circuit 12 and includes input, outfan and reset terminal；Its input is used for receiving described input signal Din；Its outfan flows through described anti-phase redundancy for output and replicates the rp input signal D of input circuit 12out-(rp input signal Dout-Represent to flow through and after described anti-phase redundancy replicates input circuit 12, be in the input signal that anti-phase redundancy replicates the outfan of input circuit 12), its outfan is floating；Its reset terminal is for often receiving input signal DinBefore, receive described first reset signal reset1 with described positive input circuit 11, to reset simultaneously.
Output circuit 2 further comprises positive output circuit 21 and anti-phase redundancy replicates output circuit 22.The effect of positive output circuit 21 is the output signal (representing with a line in Fig. 2) receiving a pair complementation that sense amplifier sends, and exports output signal Q flowing through positive output circuit 21out；And the effect that anti-phase redundancy replicates output circuit 22 is to receive the output signal of this pair complementation with positive output circuit 21 and carry out anti-phase process simultaneously, and the inverted redundancy of output stream replicates the reversed-phase output signal Q of output circuit 22out-, wherein, anti-phase redundancy replicates the reversed-phase output signal Q in output circuit 22out-The outfan that residing anti-phase redundancy replicates output circuit 22 is floating.Such as when flowing through the data of described positive output circuit 21 for " 0 ", the data flowing through described anti-phase redundancy duplication output circuit 22 are " 1 ", and when flowing through the data of described positive output circuit 21 for " 1 ", flowing through described anti-phase redundancy and replicating the data of output circuit 22 is " 0 ".
Positive output circuit 21 includes first input end, the second input, outfan and reset terminal；Its first input end and the second input are for receiving the output signal of the pair of complementation；Its outfan flows through output signal Q of positive output circuit 21 for outputout；Its reset terminal is for receiving one second reset signal reset2 before often receiving the output signal of a pair complementation, to reset.
Anti-phase redundancy replicates output circuit 22 and includes first input end, the second input, outfan and reset terminal；Its first input end and the second input are for receiving the output signal of the pair of complementation；Its outfan replicates the reversed-phase output signal Q of output circuit 22 for the inverted redundancy of output streamout-, its outfan is floating；Its reset terminal, for before often receiving the output signal of a pair complementation, receives described second reset signal reset2 with described positive output circuit 21, to reset simultaneously.
As it is shown on figure 3, the positive input circuit 11 in input circuit 1 includes the first not circuit n1, transmission gate circuit, OR-NOT circuit nor and the second not circuit n2；Wherein, the input of the first not circuit n1 as the input of described positive input circuit 11 to receive described input signal Din；The input of transmission gate circuit connects the outfan of described first not circuit n1；The first input end of OR-NOT circuit nor connects the outfan of described transmission gate circuit, second input of OR-NOT circuit nor is as the reset terminal of positive input circuit 11, receiving the first reset signal reset1 before often receiving an input signal at described positive input circuit 11, the outfan of OR-NOT circuit nor is as the outfan of described positive input circuit 11；The input of the second not circuit n2 connects the outfan of described OR-NOT circuit nor, and the outfan of the second not circuit n2 connects the first input end of described OR-NOT circuit nor.
Described transmission gate circuit includes a nmos pass transistor NM and PMOS transistor PM；The drain electrode of described nmos pass transistor NM connects the outfan of described first not circuit n1, and the source electrode of described nmos pass transistor NM connects the first input end of described OR-NOT circuit nor, and the grid of described nmos pass transistor NM receives one first clock control signal CLK；The drain electrode of described PMOS transistor PM connects the outfan of described first not circuit n1, and the source electrode of described PMOS transistor PM connects the first input end of described OR-NOT circuit nor, and the grid of described PMOS transistor PM receives second clock control signal CLKX；Wherein, the first clock control signal CLK and second clock control signal CLKX are the clock control signal of a pair complementation, it is possible to ensure the most always have a clock signal effective, and then make the described transmission gate circuit can break-even transmission high level or low level.
Anti-phase redundancy in input circuit 1 replicates input circuit 12 and includes the 3rd not circuit n3, the first duplication not circuit r_n1, copy transmissions gate circuit, replicates OR-NOT circuit r_nor and second duplication not circuit r_n2；Wherein, the 3rd not circuit n3 is for receiving described input signal D with described positive input circuit 11 simultaneouslyinAnd to described input signal DinCarrying out anti-phase process, the input of the 3rd not circuit n3 replicates the input of input circuit 12 to receive described input signal D as described anti-phase redundancyin；First input replicating not circuit r_n1 connects the outfan of the 3rd not circuit n3；The input of copy transmissions gate circuit connects the described first outfan replicating not circuit r_n1；The first input end replicating OR-NOT circuit r_nor connects the outfan of described copy transmissions gate circuit, the second input replicating OR-NOT circuit r_nor replicates the reset terminal of input circuit 12 as anti-phase redundancy, often to receive input signal D at anti-phase redundancy duplication input circuit 12inReceive the first reset signal reset1 with positive input circuit 11, the outfan replicating OR-NOT circuit r_nor replicates the outfan of input circuit 12 as anti-phase redundancy before simultaneously；Second input replicating not circuit r_n2 connects the outfan of described duplication OR-NOT circuit r_nor, and the second outfan replicating not circuit r_n2 connects the first input end of described duplication OR-NOT circuit r_nor.
Described copy transmissions gate circuit includes that a duplication nmos pass transistor r_NM and replicates PMOS transistor r_PM；The drain electrode of described duplication nmos pass transistor r_NM connects the described first outfan replicating not circuit r_n1, the source electrode of described duplication nmos pass transistor r_NM connects the first input end of described duplication OR-NOT circuit r_nor, and the grid of described duplication nmos pass transistor r_NM receives described first clock control signal CLK；The drain electrode of described duplication PMOS transistor r_PM connects the described first outfan replicating not circuit r_n1, the source electrode of described duplication PMOS transistor r_PM connects the first input end of described duplication OR-NOT circuit r_nor, and the grid of described duplication PMOS transistor r_PM receives described second clock control signal CLKX；Wherein, first clock control signal CLK and second clock control signal CLKX are the clock control signal of a pair complementation, ensure that and the most always have a clock signal effective, and then make the described copy transmissions gate circuit can break-even transmission high level or low level.
Can be seen that from described above and Fig. 3, anti-phase redundancy replicates in input circuit 12, in addition to the 3rd not circuit n3, remaining circuit structure is identical with described positive input circuit 11, and then because the inverting function of the phase inverter of the 3rd not circuit n3 formerly, make anti-phase redundancy replicate the signal that flowed through of the input circuit 12 circuit structure after the 3rd not circuit n3 and synchronization and flow through the signal contrast of described positive input circuit 11, such as, replicate as a example by the outfan of input circuit 12 by positive input circuit 11 and anti-phase redundancy；When input signal D flowing through this positive input circuit 11 that the outfan of positive input circuit 11 exportsoutDuring for " 1 ", anti-phase redundancy replicates input signal D flowing through this anti-phase redundancy duplication input circuit 12 that the outfan of input circuit 12 is exportedout-For " 0 "；Otherwise, when input signal D flowing through this positive input circuit 11 that the outfan of positive input circuit 11 exportsoutDuring for " 0 ", anti-phase redundancy replicates input signal D flowing through this anti-phase redundancy duplication input circuit 12 that the outfan of input circuit 12 is exportedout-For " 1 ".So, flow through the signal code of positive input circuit 11 just to replicate input circuit 12 and compensated by flowing through anti-phase redundancy, the frequency making " 0 " to " 1 " and " 1 " change to " 0 " is always consistent, so just cannot analyze out its representative data from outside according only to the change of electric current.
It addition, the effect of the first reset signal reset1 makes positive input circuit 11 and anti-phase redundancy replicate input circuit 12 is receiving next input signal DinThe most all it is reset once, the most not only ensure that input signal D flowing through positive input circuit 11outAnd flow through input signal D of anti-phase redundancy duplication input circuit 12out-Both keep consistent by the number of times of conversion between " 0 ", " 1 ", and more making the data signal that cannot judge to flow through described input circuit 1 from outside is to maintain or change.
Now by an instantiation, input circuit 1 work process is introduced.
In next input signal DinBefore arriving, first pass through the first reset signal reset1 and reset, more next input signal D of inputin.Such as, if upper input signal DinIt is 001；After positive input circuit 11 is by resetting to 000, " 1 " is occurred once arrive the change of " 0 ", then input next one input signal Din011, occur twice " 0 " to arrive the change of " 1 ", three changes occur altogether；And anti-phase redundancy replicates input circuit 12 and just realizes the change contrary with positive input circuit 11, the change that " 1 " arrives " 0 ", generation once " 0 " is i.e. occurred to arrive the change of " 1 " twice.So being to maintain consistent for input circuit 1 generally signal " 0 " to " 1 " with the number of " 1 " to the upset of " 0 ", i.e. three times " 0 " is arrived " 1 " and three times " 1 " and is arrived " 0 ".If upper input signal DinIt is 001, next input signal DinBe 110, then positive input circuit 11 reset occurs once " 1 " to arrive the change of " 0 ", and signal input generation twice " 0 " arrives the change of " 1 "；And replicate input circuit 12 by anti-phase redundancy and make " 0 " be to maintain consistent with " 1 " to the number that " 0 " overturns to " 1 ".No matter therefore input signal DinIt is maintenance state or change, " 0 " all can be occurred to arrive " 1 " and " 1 " and arrive the upset change of " 0 ", be consistent from the curent change trend measured by outside, protect the data message flowing through input circuit 1 to the full extent.
Replicate on input circuit 12 architecture basics in above positive input circuit 11 and anti-phase redundancy, more preferably, described first replicate not circuit r_n1 and the first not circuit n1 be manufacture under the conditions of same process there is mutually isostructural not circuit；Described copy transmissions gate circuit and transmission gate circuit be manufacture under the conditions of same process there is mutually isostructural transmission gate circuit, specifically, described duplication nmos pass transistor r_NM and nmos pass transistor NM is the nmos pass transistor manufactured under the conditions of same process, and described duplication PMOS transistor r_PM and PMOS transistor PM are the PMOS transistor manufactured under the conditions of same process；Described duplication OR-NOT circuit r_nor and OR-NOT circuit nor be under the conditions of same process manufacture there is mutually isostructural OR-NOT circuit；Described second replicate not circuit r_n2 and the second not circuit n2 be under the conditions of same process manufacture there is mutually isostructural not circuit.The most more ensure that the concordance from the curent change trend measured by outside.
As shown in Figure 4, the positive output circuit 21 in output circuit 2 includes the first NAND gate circuit nand1, the second NAND gate circuit nand2 and a not circuit n；Wherein, the first input end of the first NAND gate circuit nand1 connects described sense amplifier 3 as the first input end of described positive output circuit 21, to receive the first output signal D in the output signal of the pair of complementation that described sense amplifier 3 sends；The first input end of the second NAND gate circuit nand2 connects the outfan of described first NAND gate circuit nand1, second input of the second NAND gate circuit nand2 connects described sense amplifier 3 as the second input of described positive output circuit 21, to receive the second output signal DX in the output signal of the pair of complementation that described sense amplifier 3 sends, 3rd input of the second NAND gate circuit nand2 is as the reset terminal of described positive output circuit 21, with often receive a pair complementation at described positive output circuit 21 output signal before receive described second reset signal reset2, the outfan of the second NAND gate circuit nand2 connects second input of described first NAND gate circuit nand1；The input of not circuit n connects the outfan of described second NAND gate circuit nand2, and the outfan of not circuit n, as the outfan of described positive output circuit 21, flows through the output signal of described positive output circuit 21 with output.
Anti-phase redundancy in output circuit 2 replicates output circuit 22 and includes that the first duplication NAND gate circuit r_nand1, the second duplication NAND gate circuit r_nand2 and replicate not circuit r_n；Wherein, the second input that the first first input end replicating NAND gate circuit r_nand1 replicates output circuit 22 as described anti-phase redundancy connects described sense amplifier 3, to receive the second output signal DX in the output signal of the pair of complementation；nullSecond first input end replicating NAND gate circuit r_nand2 connects the described first outfan replicating NAND gate circuit r_nand1，The first input end that second the second input replicating NAND gate circuit r_nand2 replicates output circuit 22 as described anti-phase redundancy connects described sense amplifier 3，With the first output signal D in the output signal of the pair of complementation of reception，Second replicates the 3rd input of NAND gate circuit r_nand2 replicates the reset terminal of output circuit 22 as described anti-phase redundancy，Before replicating, in described anti-phase redundancy, the output signal that output circuit 22 often receives a pair complementation，Receive described second reset signal reset2 with described positive output circuit 21 simultaneously，Second outfan replicating NAND gate circuit r_nand2 connects the described first the second input replicating NAND gate circuit r_nand1；The input replicating not circuit r_n connects the described second outfan replicating NAND gate circuit r_nand2, the outfan replicating not circuit r_n replicates the outfan of output circuit 22 as described anti-phase redundancy, flows through described anti-phase redundancy with output and replicates the output signal of output circuit 22.
Can be seen that in shown in described above and Fig. 4, the first NAND gate circuit nand1 and the second NAND gate circuit nand2 in described positive output circuit 21 have collectively constituted a rest-set flip-flop, and first NAND gate circuit nand1 first input end as described positive output circuit 21 first input end connect described sense amplifier 3, second input of the second NAND gate circuit nand2 as described positive output circuit 21 second input connect described sense amplifier 3；Correspond ground, described anti-phase redundancy replicates the first duplication NAND gate circuit r_nand1 in output circuit 22 and the second duplication NAND gate circuit r_nand2 and has collectively constituted the rest-set flip-flop of the duplication identical with the described rest-set flip-flop structure in positive output circuit 21, but the annexation contrast of rest-set flip-flop and described sense amplifier 3 in the annexation of the rest-set flip-flop of this duplication and described sense amplifier 3 and positive output circuit 21, it it is the first input end second input described sense amplifier 3 of connection as described anti-phase redundancy duplication output circuit 22 of the first duplication NAND gate circuit r_nand1；The first input end that second the second input replicating NAND gate circuit r_nand2 replicates output circuit 22 as described anti-phase redundancy connects described sense amplifier 3.Thus, when described sense amplifier 3 sends output signal to output circuit 2, flow through anti-phase redundancy and replicate signal and positive output circuit 21 contrast of output circuit 22.Output signal Q flowing through described positive output circuit 21 when the output of described positive output circuit 21outDuring for " 1 ", described anti-phase redundancy replicates the described anti-phase redundancy that flows through of output circuit 22 output and replicates output signal Q of output circuit 22out-For " 0 "；And when output signal Q flowing through described positive output circuit 21 of described positive output circuit 21 outputoutDuring for " 0 ", described anti-phase redundancy replicates the described anti-phase redundancy that flows through of output circuit 22 output and replicates output signal Q of output circuit 22out-For " 1 ".So, flow through the signal code of described positive output circuit 21 just to replicate output circuit 22 and compensated by flowing through described anti-phase redundancy, the frequency making " 0 " to " 1 " and " 1 " change to " 0 " is always consistent, and then just cannot analyze out its representative data from outside according only to the change of electric current.
Replicate on input circuit 12 architecture basics at above positive input circuit 11 and anti-phase redundancy, more preferably, described first replicate NAND gate circuit r_nand1 and the first NAND gate circuit nand1 be under the conditions of same process manufacture there is mutually isostructural NAND gate circuit；Described second replicate NAND gate circuit r_nand2 and the second NAND gate circuit nand2 be under the conditions of same process manufacture there is mutually isostructural NAND gate circuit；Described duplication not circuit r_n and not circuit n be under the conditions of same process manufacture there is mutually isostructural not circuit.The most more ensure that the concordance from the curent change trend measured by outside.
Additionally, similar to input circuit 1, the effect of the second reset signal reset2 makes positive output circuit 21 and anti-phase redundancy duplication output circuit 22 all be reset once before receiving the output signal of lower a pair complementation that sense amplifier 3 is sent, and the most not only ensure that signal and output signal Q of positive output circuit 21 flowing through positive output circuit 21outWith output signal Q that the signal and anti-phase redundancy flowing through anti-phase redundancy duplication output circuit 22 replicates output circuit 22out-Both keep consistent by the number of times of conversion between " 0 ", " 1 ", and more making the data signal that cannot judge to flow through described output circuit 2 from outside is to maintain or change.
Now by an instantiation, the work process of output circuit 2 is introduced.
Before lower a pair complementary output signal the first output signal D from sense amplifier 3 and the second output signal DX are arrived, first pass through the second reset signal reset2 and reset, then input lower a pair output signal D and DX.Such as, if currently carry out is the operation reading " 0 ", then the first output signal D through sensitive amplifier circuit is " 1 ", second output signal DX is " 0 ", after this rest-set flip-flop to NAND gate circuit composition of the first NAND gate circuit nand1 and the second NAND gate circuit nand2, latch signal is " 1 " again, eventually passes not circuit n(phase inverter) Q that exportsoutFor " 0 ".Simultaneously, first output signal D and the second output signal DX give the second duplication NAND gate circuit r_nand2 and first the most respectively and replicate NAND gate circuit r_nand1, after replicated the rest-set flip-flop of the duplication that NAND gate circuit r_nand2 and first duplication NAND gate circuit r_nand1 forms by second, latch signal is " 0 ", then is replicated not circuit rn(phase inverter) output Qout-For " 1 ".So, " 0 " occurred in this process is arrived " 1 " and " 1 " and is arrived the upset change of " 0 " the most once.In like manner can obtain, when reading " 1 " operation, be " 0 " via the first output signal D after sensitive amplifier circuit, the second output signal DX is " 1 ", final QoutIt is output as " 1 ", Qout-Being output as " 0 ", same " 0 " is arrived " 1 " and " 1 " and is arrived the upset change of " 0 " the most once.So; the upset change frequency of " 0 " to " 1 " and " 1 " to " 0 " is identical; and each time behaviour do all can occur " 0 " arrive " 1 " and " 1 " arrive " 0 " upset change; it is consistent from the curent change trend measured by outside, protects the data message flowing through output circuit to the full extent.
Be can be seen that by above-mentioned introduction, the I/O circuit of the SRAM of the present invention, the duplicate circuit of redundancy is both increased in input and output circuit part, and in the duplicate circuit of redundancy, the signal flowed through is carried out anti-phase process so that the signal flowing through the duplicate circuit of redundancy and original input and output circuit is contrary and then complementary.So, overall, the signal intensity trend flowing through I/O circuit is stable, or will not be captured to the change of " 0 " by outer bound pair signal by " 1 " by " 0 " to " 1 " because of signal, and then can effectively prevent the outside power consumption analysis attack to SRAM.Because the I/O circuit of the present invention uses the duplicate circuit of redundancy, the most compared with prior art it is also easy to realize, and increased cost is the least.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all within the spirit and principles in the present invention, any modification, equivalent substitution and improvement etc. done, within should be included in the scope of protection of the invention.
Claims (10)
1. an I/O circuit of SRAM, including input circuit and output circuit, it is characterised in that:
Described input circuit includes:
Positive input circuit, for receiving an input signal, and provides the input signal flowing through described positive input circuit；It includes input, outfan and reset terminal；Its input is used for receiving described input signal；Its outfan flows through the input signal of described positive input circuit for output；Its reset terminal is for receiving one first reset signal before often receiving an input signal, to reset；
Anti-phase redundancy replicates input circuit, for receiving described input signal with described positive input circuit and described input signal being carried out anti-phase process simultaneously；It includes input, outfan and reset terminal；Its input is used for receiving described input signal；Its outfan flows through described anti-phase redundancy for output and replicates the rp input signal of input circuit；Its reset terminal, for before often receiving an input signal, receives described first reset signal with described positive input circuit, to reset simultaneously；
Described output circuit includes:
Positive output circuit, for receiving the output signal of a pair complementation that sense amplifier sends, and exports the output signal flowing through described positive output circuit；It includes first input end, the second input, outfan and reset terminal；Its first input end and the second input are for receiving the output signal of the pair of complementation；Its outfan flows through the output signal of described positive output circuit for output；Its reset terminal is for receiving one second reset signal before often receiving the output signal of a pair complementation, to reset；
Anti-phase redundancy replicates output circuit, for receiving the output signal of the pair of complementation with described positive output circuit and carrying out anti-phase process simultaneously；It includes first input end, the second input, outfan and reset terminal；Its first input end and the second input are for receiving the output signal of the pair of complementation；Its outfan flows through described anti-phase redundancy for output and replicates the reversed-phase output signal of output circuit；Its reset terminal, for before often receiving the output signal of a pair complementation, receives described second reset signal with described positive output circuit, to reset simultaneously.
The I/O circuit of SRAM the most according to claim 1, it is characterised in that described positive input circuit includes:
First not circuit, its input as the input of described positive input circuit to receive described input signal；
Transmission gate circuit, its input connects the outfan of described first not circuit；
OR-NOT circuit, its first input end connects the outfan of described transmission gate circuit, its second input is as the reset terminal of described positive input circuit, receiving described first reset signal before often receiving an input signal at described positive input circuit, its outfan flows through the input signal of described positive input circuit as the outfan of described positive input circuit to provide；
Second not circuit, its input connects the outfan of described OR-NOT circuit, and its outfan connects the first input end of described OR-NOT circuit.
The I/O circuit of SRAM the most according to claim 2, it is characterised in that described anti-phase redundancy replicates input circuit and includes:
3rd not circuit, for receiving described input signal with described positive input circuit and described input signal being carried out anti-phase process simultaneously, its input replicates the input of input circuit to receive described input signal as described anti-phase redundancy；
First replicates not circuit, and its input connects the outfan of described 3rd not circuit；
Copy transmissions gate circuit, its input connects the described first outfan replicating not circuit；
Replicate OR-NOT circuit, its first input end connects the outfan of described copy transmissions gate circuit, its second input replicates the reset terminal of input circuit as described anti-phase redundancy, receiving described first reset signal to replicate before input circuit often receives an input signal in described anti-phase redundancy with described positive input circuit, its outfan replicates the outfan of input circuit as described anti-phase redundancy simultaneously；
Second replicates not circuit, and its input connects the outfan of described duplication OR-NOT circuit, and its outfan connects the first input end of described duplication OR-NOT circuit.
The I/O circuit of SRAM the most according to claim 3, it is characterised in that described transmission gate circuit includes:
One nmos pass transistor, its drain electrode connects the outfan of described first not circuit, and its source electrode connects the first input end of described OR-NOT circuit, and its grid receives one first clock control signal；
One PMOS transistor, its drain electrode connects the outfan of described first not circuit, and its source electrode connects the first input end of described OR-NOT circuit, and its grid receives a second clock control signal.
The I/O circuit of SRAM the most according to claim 4, it is characterised in that described copy transmissions gate circuit includes:
One replicates nmos pass transistor, and its drain electrode connects the described first outfan replicating not circuit, and its source electrode connects the first input end of described duplication OR-NOT circuit, and its grid receives described first clock control signal；
One replicates PMOS transistor, and its drain electrode connects the described first outfan replicating not circuit, and its source electrode connects the first input end of described duplication OR-NOT circuit, and its grid receives described second clock control signal.
6. according to the I/O circuit of the SRAM described in claim 4 or 5, it is characterised in that: described first clock control signal and second clock control signal are the clock control signal of a pair complementation.
The I/O circuit of SRAM the most according to claim 3, it is characterised in that:
Described first replicate not circuit and the first not circuit be manufacture under the conditions of same process there is mutually isostructural not circuit；
Described copy transmissions gate circuit and transmission gate circuit be manufacture under the conditions of same process there is mutually isostructural transmission gate circuit；
Described duplication OR-NOT circuit and OR-NOT circuit be manufacture under the conditions of same process there is mutually isostructural OR-NOT circuit；
Described second replicate not circuit and the second not circuit be manufacture under the conditions of same process there is mutually isostructural not circuit.
The I/O circuit of SRAM the most according to claim 1, it is characterised in that described positive output circuit includes:
First NAND gate circuit, its first input end connects described sense amplifier as the first input end of described positive output circuit, to receive the first output signal in the output signal of the pair of complementation；
Second NAND gate circuit, its first input end connects the outfan of described first NAND gate circuit, its second input connects described sense amplifier as the second input of described positive output circuit, with the second output signal in the output signal of the pair of complementation of reception, its the 3rd input is as the reset terminal of described positive output circuit, with often receive a pair complementation at described positive output circuit output signal before receive described second reset signal, its outfan connects the second input of described first NAND gate circuit；
Not circuit, its input connects the outfan of described second NAND gate circuit, and its outfan, as the outfan of described positive output circuit, flows through the output signal of described positive output circuit with output.
The I/O circuit of SRAM the most according to claim 8, it is characterised in that described anti-phase redundancy replicates output circuit and includes:
First replicates NAND gate circuit, and the second input that its first input end replicates output circuit as described anti-phase redundancy connects described sense amplifier, to receive the second output signal in the output signal of the pair of complementation；
Second replicates NAND gate circuit, its first input end connects the described first outfan replicating NAND gate circuit, the first input end that its second input replicates output circuit as described anti-phase redundancy connects described sense amplifier, with the first output signal in the output signal of the pair of complementation of reception, its the 3rd input replicates the reset terminal of output circuit as described anti-phase redundancy, before replicating, in described anti-phase redundancy, the output signal that output circuit often receives a pair complementation, receive described second reset signal with described positive output circuit simultaneously, its outfan connects the described first the second input replicating NAND gate circuit；
Replicating not circuit, its input connects the described second outfan replicating NAND gate circuit, and its outfan replicates the outfan of output circuit as described anti-phase redundancy, flows through described anti-phase redundancy with output and replicates the reversed-phase output signal of output circuit.
The I/O circuit of SRAM the most according to claim 9, it is characterised in that:
Described first replicate NAND gate circuit and the first NAND gate circuit be manufacture under the conditions of same process there is mutually isostructural NAND gate circuit；
Described second replicate NAND gate circuit and the second NAND gate circuit be manufacture under the conditions of same process there is mutually isostructural NAND gate circuit；
Described duplication not circuit and not circuit be manufacture under the conditions of same process there is mutually isostructural not circuit.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1614533A (en) * | 2003-11-04 | 2005-05-11 | 上海华虹集成电路有限责任公司 | Method for preventing simple power consumption analysis attack |
| US7577013B2 (en) * | 2005-06-27 | 2009-08-18 | Industrial Technology Research Institute | Storage units and register file using the same |
| CN102169719A (en) * | 2010-02-25 | 2011-08-31 | 复旦大学 | One time programmable (OTP) resistive random access memory (RRAM) as well as read-write circuit and programming method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1614533A (en) * | 2003-11-04 | 2005-05-11 | 上海华虹集成电路有限责任公司 | Method for preventing simple power consumption analysis attack |
| US7577013B2 (en) * | 2005-06-27 | 2009-08-18 | Industrial Technology Research Institute | Storage units and register file using the same |
| CN102169719A (en) * | 2010-02-25 | 2011-08-31 | 复旦大学 | One time programmable (OTP) resistive random access memory (RRAM) as well as read-write circuit and programming method thereof |
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