CN101882462A - Setting operation method of resistance random access memory - Google Patents
Setting operation method of resistance random access memory Download PDFInfo
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- CN101882462A CN101882462A CN2009100509453A CN200910050945A CN101882462A CN 101882462 A CN101882462 A CN 101882462A CN 2009100509453 A CN2009100509453 A CN 2009100509453A CN 200910050945 A CN200910050945 A CN 200910050945A CN 101882462 A CN101882462 A CN 101882462A
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- random access
- access memory
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Abstract
The invention belongs to the technical field of non-volatile memories, in particular to a setting operation method of a resistance random access memory. The method carries out once-through setting operation to the resistance random access memory through a plurality of pulses with the pulse amplitude growing in a stepping way, so that each resistance random access memory or each setting operation of each resistance random access memory is carried out under the most appropriate setting operation voltage, thereby preventing the 'over programming' phenomenon in the setting operation so as to improve the Ron value of the resistance random access memory after setting, and facilitate the reduction of the power consumption of follow-up reset operation.
Description
Technical field
The invention belongs to nonvolatile memory (Nonvolatile Memory) technical field, be specifically related to set (Set) method of operating of resistance random access memory (Resistive Random Access Memory), relate in particular to the method that a plurality of pulses of adopting the pulse height step-by-step movement to increase realize a set operation.
Background technology
Storer occupies an important position in semi-conductor market, because portable electric appts is constantly universal, the share of nonvolatile memory in whole storage market is also increasing.Nearest non-volatile resistance random access memory spare (Resistive Switching Memory) because its high density, low cost, the characteristics that can break through the technology generation development restriction cause is shown great attention to.But resistance random access memory utilizes the resistance of storage medium to come storage signal in the characteristic of inverse conversion under the electric signal effect, between high-impedance state and low resistance state, and storage medium can have a variety of, comprises binary or multi-element metal oxide, even organism, wherein, and Cu
xO (1＜x≤2) is shown great attention to owing to not containing characteristics such as the element that can pollute conventional cmos technology, low-power consumption.
Figure 1 shows that the characteristic synoptic diagram of I-V of the resistance random access memory that has been in the news.As shown in Figure 1, this resistance random access memory can adopt the different voltage scanning of polarity to carry out changing between high-impedance state and the low resistance state, signal has provided three reset operation (Reset of this resistance random access memory among Fig. 1, change to high-impedance state from low resistance state) and set operation (Set changes to low resistance state from high-impedance state). Curve 101a, 101b, 101c represented primary state be high-impedance state, voltage from 0 volt of I-V family curve that obtains to forward scan, set operation of every curve representation; Curve 100a, 100b, 100c have represented that primary state is that low resistance state, voltage are from 0 volt of I-V family curve that obtains to negative sense scanning, reset operation of every curve representation.With curve 101a is example, when voltage when 0 volt of forward increases progressively, gradually increase to V
T3The time, electric current can increase rapidly suddenly, shows that memory resistor is mutated into low resistance state from high-impedance state, wherein V
T3We are defined as set operation voltage; Carrying out reset operation, carry out set operation behind the reset operation more then by reverse voltage scanning.We can find by three set operation among curve 101a, 101b, the 101c, and its set operation voltage is respectively V
T3, V
T4, V
T5, set operation voltage and inequality, by repeatedly repeatedly Set operate us and can find that set operation voltage is to distribute in certain area coverage.Simultaneously, further we also recognize, because process fluctuation etc. therefore, to the different resistor random-access memory units of same storage array, its set operation voltage each other neither be unified, and also only distribute in certain area coverage.
Figure 2 shows that activation manipulation, reset operation, the read operation of the resistance random access memory of prior art, the pulse synoptic diagram of set operation.From Fig. 2, the voltage of the pulse of each operation, the electric current that in storer, produces and the relation between the time as can be seen, wherein the electric current of the pulse of reset operation is far longer than the pulse current of set operation, when calculating power consumption according to power consumption fundamental formular P=I2R, can find that the power consumption of reset operation is far longer than the power consumption of set operation.China applies for a patent CN200710043707.0 (title: a kind of resistance random access memory of reducing reset operation current), reduce the electric current of reset operation by the method that improves low resistance state resistance (Ron), thereby reduce its power consumption.
Characteristic according to the set operation voltage of above resistance random access memory, the setting operation method of the resistance random access memory of prior art is to realize a Set operation by the way that applies single Set pulse, the height of its Set potential pulse is generally greater than the distributive province thresholding of set operation voltage, for example, the height of Set potential pulse is certainly greater than V shown in Figure 1
T3, V
T4, V
T5, can guarantee so same resistance random access memory back and forth Set, the Rest operating process can both be successful.But such Set method of operating, its Set operation are applied to voltage on the memory unit greater than its set operation voltage (V
T), therefore, there is the phenomenon of " cross programming (over-programming) ", can judge to the mechanism of resistance random access memory that according to us it " crosses programming " and can cause low resistance state resistance (Ron) step-down after the Set operation.Therefore the Set method of operating of prior art has the advantages that to increase the resistance random access memory power consumption.
Summary of the invention
The technical problem to be solved in the present invention is the phenomenon that the resistance random access memory Ron that " crossing programming " of avoiding Set to operate brought reduces.
For solving above technical matters, the invention provides a kind of resistance random access memory setting operation method its may further comprise the steps:
When (1) described resistance random access memory is high-impedance state, apply initial set operation pulse in described resistance random access memory;
(2) apply the read operation signal in described resistance random access memory, if described resistance random access memory is a low resistance state, then set operation finishes; If described resistance random access memory is a high-impedance state, then enter next step;
(3) apply follow-up set operation pulse in described resistance random access memory, described follow-up set operation pulsion phase increases certain pulse height than it previous set operation pulse;
(4) finish until set operation repeating step (2) and (3).
According to setting operation method provided by the invention, wherein, described set operation pulse is a potential pulse.The pulse height scope of initial set operation pulse is 0.1V-0.6V in the step (1).Pulse height described in the step (3) is 0.1V.Described read operation signal is the read pulse voltage signal, and the pulse height of read pulse voltage signal is less than the set operation magnitude of voltage of resistance random access memory.
Among the present invention, in preferable embodiment, comprise step (3b) in the described step (3): whether the pulse height of judging described follow-up set operation pulse allows pulse height greater than maximum, if be judged as "Yes", described resistance random access memory set operation failure, be judged as "No", then enter step (4).According to setting operation method provided by the invention, wherein, described set operation pulse can be current impulse.According to setting operation method provided by the invention, wherein, described resistance random access memory is the one-time programmable resistance random access memory.
Useful technique effect of the present invention is, with a plurality of pulses that step-by-step movement increases resistance random access memory is carried out set operation one time by pulse height, the each set operation that is each resistance random access memory or each resistance random access memory is carried out on only set operation voltage, avoided the phenomenon of " crossing programming " in the set operation, thereby improve the Ron value after the resistance random access memory set, help reducing the power consumption of subsequent reset operation.
Description of drawings
Fig. 1 is the characteristic synoptic diagram of I-V of the resistance random access memory of prior art.
Fig. 2 is activation manipulation, reset operation, the read operation of the resistance random access memory of prior art, the pulse synoptic diagram of set operation;
Fig. 3 is the setting operation method synoptic diagram of resistance random access memory provided by the invention;
Fig. 4 is the another embodiment synoptic diagram of the setting operation method of resistance random access memory provided by the invention;
Fig. 5 is the set operation pulse synoptic diagram of set operation of the present invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
Embodiment 1
Figure 3 shows that the setting operation method synoptic diagram of resistance random access memory provided by the invention.The programming operation of resistance random access memory includes two kinds of current impulse information and voltage pulse signals, in this embodiment, all is the signal of set operation with the voltage pulse signal; The pulse width of set operation pulse is not limited by the present invention.As shown in Figure 3, this embodiment setting operation method may further comprise the steps.
Step S10 when resistance random access memory is high-impedance state, applies initial set operation pulse.
In this step, according to the characteristic of set operation, each set operation all is that high-impedance state is converted to low resistance state, so at first resistance random access memory should be high-impedance state; The pulse height scope of the initial set operation pulse that applies is 0.1V-0.6V, can determine according to the set operation voltage distribution range of concrete resistance random access memory, for example, choose the pulse height of the 0.3V of 20% energy set operation success as initial set operation pulse.
Step S20 applies the read operation signal.
In this step, the read operation signal is the read pulse voltage signal, and the pulse height of read pulse voltage signal is less than the set operation magnitude of voltage of resistance random access memory, and general range is 0.1V-0.5V, the less relatively read pulse voltage amplitude of general selection reduces and reads power consumption.
Step S30 judges whether set operation is successful.
In this step, if resistance random access memory is a low resistance state, represent that then resistance random access memory changed to low resistance state by high-impedance state, last set operation pulse successfully realizes set operation, then the set operation process finishes; If described resistance random access memory is a high-impedance state, then the last set operation pulse of expression does not successfully realize set operation entering step S40 because the pulse height of its set operation pulse does not reach the set operation magnitude of voltage.
Step S40, pulse increases pulse height, applies follow-up set operation pulse.
In this step, apply follow-up set operation pulse in resistance random access memory, follow-up set operation pulsion phase increases certain pulse height than it previous set operation pulse; The incremental change of pulse height can be according to the real needs setting, and in this embodiment, the incremental change of pulse height is 0.1V.
Step S40 enters step S20 after finishing, and circulation execution in step S20, S30, S40 are judged as successfully set operation until resistance random access memory.
Embodiment 2
Figure 4 shows that the another embodiment synoptic diagram of setting operation method of resistance random access memory provided by the invention.In conjunction with Fig. 3 and shown in Figure 4, the difference of this example and 3 illustrated embodiments is, also comprise step S41: whether the pulse height of judging follow-up set operation allows pulse height greater than maximum, if be judged as "Yes", described resistance random access memory set operation failure, be judged as "No", then enter step (20).By increasing this step, can prevent from successful set operation to cause the phenomenon of step S20, S30, S40 infinite loop to take place because of resistance random access memory itself.The maximum pulse height that allows can preestablish according to the resistance random access memory characteristic, for example can be to make the set operation magnitude of voltage that 99% resistance random access memory can both successful set.
Embodiment 3
Figure 5 shows that the set operation pulse synoptic diagram of this invention set operation.As shown in Figure 5,501 is initial set operation pulse, and 502,508,509 is follow-up set operation pulse, saves between 502 and 508 to have illustrated some set operation pulses, and each pulsion phase increases progressively with step-by-step system on amplitude for the pulse in front.Be defined as maximum with 509 simultaneously and allow pulse height.
Need to prove that further the setting operation method that this specific embodiment provides is particularly useful for using in disposable programmable (OTP) resistance random access memory.Because this setting operation method need be realized set operation by a plurality of pulses, therefore will inevitably sacrifice its velocity characteristic.And in the one-time programmable resistance random access memory, be not to pay close attention to very much to its velocity characteristic, and pay close attention to its power consumption characteristics emphatically, the setting operation method of this embodiment is applicable to the set operation of one-time programmable resistance random access memory fully.
Under situation without departing from the spirit and scope of the present invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the specific embodiment described in the instructions.
Claims (9)
1. the setting operation method of a resistance random access memory is characterized in that, may further comprise the steps:
When (1) described resistance random access memory is high-impedance state, apply initial set operation pulse in described resistance random access memory;
(2) apply the read operation signal in described resistance random access memory, if described resistance random access memory is a low resistance state, then set operation finishes; If described resistance random access memory is a high-impedance state, then enter next step;
(3) apply follow-up set operation pulse in described resistance random access memory, described follow-up set operation pulsion phase increases certain pulse height than it previous set operation pulse;
(4) finish until set operation repeating step (2) and (3).
2. the setting operation method of resistance random access memory according to claim 1 is characterized in that, the set operation pulse of described resistance random access memory is a potential pulse.
3. method according to claim 1 is characterized in that, the pulse height scope of initial set operation pulse is 0.1V-0.6V in the step (1).
4. method according to claim 1 is characterized in that, the pulse height described in the step (3) is 0.1V.
5. method according to claim 1 is characterized in that, the read operation signal of described step (2) is the read pulse voltage signal, and the pulse height of described read pulse voltage signal is less than the set operation magnitude of voltage of resistance random access memory.
6. method according to claim 1, it is characterized in that, comprise step (3b) in the described step (3): whether the pulse height of judging described follow-up set operation pulse allows pulse height greater than maximum, if be judged as "Yes", described resistance random access memory set operation failure, be judged as "No", then enter step (4).
7. method according to claim 6 is characterized in that, in the step (3b), the described maximum pulse height that allows preestablishes according to the resistance random access memory characteristic.
8. method according to claim 1 is characterized in that, the set operation pulse of described resistance random access memory is current impulse.
9. according to the arbitrary described method of claim 1 to 8,, it is characterized in that wherein said resistance random access memory is the one-time programmable resistance random access memory.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102592667A (en) * | 2011-01-13 | 2012-07-18 | 中国科学院微电子研究所 | Method and device for programming resistance storage unit |
| CN102945683A (en) * | 2012-11-05 | 2013-02-27 | 中国科学院上海微系统与信息技术研究所 | Quick erasing-writing operation method for phase change memory |
| CN104464801A (en) * | 2014-11-10 | 2015-03-25 | 中国科学院微电子研究所 | Method for effectively improving durability of high-resistance random access memory |
| CN105989876A (en) * | 2014-10-27 | 2016-10-05 | 财团法人工业技术研究院 | Resistive memory system, driving circuit thereof and impedance setting method thereof |
| CN106328197A (en) * | 2015-07-07 | 2017-01-11 | 华邦电子股份有限公司 | Memory writing apparatus and method |
| CN112270949A (en) * | 2020-10-27 | 2021-01-26 | 清华大学 | Method for testing transient stability of resistive random access memory |
| WO2022068125A1 (en) * | 2020-09-30 | 2022-04-07 | 中国科学院微电子研究所 | Memory circuit structure and method for operation thereof |
| WO2022068126A1 (en) * | 2020-09-30 | 2022-04-07 | 中国科学院微电子研究所 | Method for operating storage unit, method for operating resistive random access memory, and electronic device |
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| CN101118784A (en) * | 2007-09-06 | 2008-02-06 | 复旦大学 | Reset operation method of resistor stochastic memory |
| CN101136247A (en) * | 2006-08-28 | 2008-03-05 | 三星电子株式会社 | Methods of programming a resistive memory device |
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| CN101136247A (en) * | 2006-08-28 | 2008-03-05 | 三星电子株式会社 | Methods of programming a resistive memory device |
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102592667A (en) * | 2011-01-13 | 2012-07-18 | 中国科学院微电子研究所 | Method and device for programming resistance storage unit |
| CN102945683A (en) * | 2012-11-05 | 2013-02-27 | 中国科学院上海微系统与信息技术研究所 | Quick erasing-writing operation method for phase change memory |
| CN102945683B (en) * | 2012-11-05 | 2016-08-31 | 中国科学院上海微系统与信息技术研究所 | A kind of flash operational approach of phase change memory |
| CN105989876B (en) * | 2014-10-27 | 2019-04-26 | 财团法人工业技术研究院 | Resistive memory system, driving circuit thereof and impedance setting method thereof |
| CN105989876A (en) * | 2014-10-27 | 2016-10-05 | 财团法人工业技术研究院 | Resistive memory system, driving circuit thereof and impedance setting method thereof |
| CN104464801B (en) * | 2014-11-10 | 2018-01-09 | 中国科学院微电子研究所 | A kind of method for effectively improving resistance-variable storing device durability |
| CN104464801A (en) * | 2014-11-10 | 2015-03-25 | 中国科学院微电子研究所 | Method for effectively improving durability of high-resistance random access memory |
| CN106328197A (en) * | 2015-07-07 | 2017-01-11 | 华邦电子股份有限公司 | Memory writing apparatus and method |
| CN106328197B (en) * | 2015-07-07 | 2019-01-25 | 华邦电子股份有限公司 | Device for writing into memory and method |
| WO2022068125A1 (en) * | 2020-09-30 | 2022-04-07 | 中国科学院微电子研究所 | Memory circuit structure and method for operation thereof |
| WO2022068126A1 (en) * | 2020-09-30 | 2022-04-07 | 中国科学院微电子研究所 | Method for operating storage unit, method for operating resistive random access memory, and electronic device |
| CN112270949A (en) * | 2020-10-27 | 2021-01-26 | 清华大学 | Method for testing transient stability of resistive random access memory |
| CN112270949B (en) * | 2020-10-27 | 2022-11-15 | 清华大学 | Method for testing transient stability of resistive random access memory |
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Application publication date: 20101110 |