CN102945683A - Quick erasing-writing operation method for phase change memory - Google Patents

Abstract

The invention provides a fast erasing and writing operation method for phase change storage. The SET programming pulse for performing the erasing operation is a preprogramming pulse and a programming pulse in sequence. Less than the RESET pulse operation time of the write operation. The present invention also provides a fast erasing and writing operation method of a phase-change memory circuit, which includes a logic control circuit, a memory cell array, a drive circuit connected to the logic control circuit, a word line gate transistor, a bit line gate transistor, and a read circuit. circuit; when performing erasing operation SET programming, each channel is opened to form a pre-programming pulse, which flows into the bit line gating tube, and then flows into the selected phase-change memory cell to complete the pre-programming operation; then the large current channel is turned off, and the programming of the output The pulses program the selected phase change memory cells. The invention effectively reduces the SET programming time of the phase-change memory unit, thereby increasing the erasing operation speed of the phase-change memory and improving the low-resistance distribution after SET programming.

Description

A fast erasing and writing operation method for phase change storage

technical field

The invention belongs to the field of micro-nano electronics technology, and relates to a programming technology of an information memory, in particular to a fast erasing and writing operation method of a phase-change memory and a fast erasing and writing operation method of a phase-change memory circuit.

Background technique

Phase Change Memory (Phase Change Memory), as a new generation of non-volatile memory, is based on Ovshinsky in the late 1960s (Phys. Rev. Lett., 21, 1450-1453, 1968) and early 1970s (Appl. Phys . Lett., 18, 254～257, 1971) The phase-change thin film proposed by 1971) can be applied to the concept of phase-change storage media, and it is a storage device with low price and stable performance. Phase-change memory can be made on a silicon wafer substrate, and its key materials are recordable phase-change films, heating resistor materials, heat insulating materials and lead-out electrode materials.

Phase-change memory consists of an array of memory cells and an external drive circuit, and each memory cell has some phase-change material to store data. Depending on phase-change materials such as chalcogenides (e.g., GeTeAsSi, GeTe, GeSbTe (GST), GeTeBi, GeSbAg, etc.), this class of materials can stably and reversibly transition between crystalline and amorphous phases, where A typical representative material is a synthetic material (GST) containing germanium, antimony and tellurium. Incorporating phase-change materials into circuits can allow the memory cells to function as fast-switching programmable resistors. This programmable resistor can exhibit a dynamic range greater than 40 times the resistivity dynamic range between the crystalline state (low resistivity) and the amorphous state (high resistivity), and can present a Multiple stored intermediate states are carried out in the cell. Data stored in a memory cell is read out by measuring the cell resistivity.

The crystal phase of a substance is changed by providing energy, and the crystal phase change of a substance is determined by two factors: energy accumulation and cooling speed. Rapid cooling after the melting of the substance can transform the substance from the crystalline state to the amorphous state, and in the case of annealing, the substance can be transformed from the amorphous state to the crystalline state. According to this reversible transformation relationship, binary recording can be realized. The traditional technology of phase change memory cell programming is: apply voltage pulse or current pulse signal with different height and width on the phase change memory cell to make the phase change material undergo reversible phase transition between amorphous state and polycrystalline state to change its resistance By distinguishing the high resistance in the amorphous state and the low resistance in the polycrystalline state, the writing, erasing and reading operations of information can be realized. Figure 1 shows a conventional pulse sequence for programming phase-change memory. To achieve the change from low resistance to high resistance, that is, write operation, it is necessary to apply a RESET rectangular pulse with higher amplitude and shorter time, so that the phase change material in the memory cell quickly exceeds the threshold switch, and the temperature of the material rises above the melting temperature , and then the pulse signal is quickly removed, the material is cooled rapidly, and the long-range order of the polycrystalline is destroyed, thereby realizing the transformation from polycrystalline to amorphous, and keeping the material in an amorphous state. To realize the change from high resistance to low resistance, that is, wiping operation, it is necessary to apply a medium-amplitude and long-time SET rectangular pulse. The variable memory cell starts crystal nucleus growth after the condition greater than the switching threshold, and the resistance remains in a low resistance state after the pulse is removed. The magnitude of the SET operation is smaller than that of the RESET operation to prevent the phase-change memory cell from being converted to an amorphous state. Generally speaking, due to the influence of factors such as manufacturing process, ambient temperature and initial resistance of phase-change memory cells, the write operation (RESET) of phase-change memory cells in phase-change memory takes tens of nanoseconds to hundreds of nanoseconds. Current heating time, while the erasing operation (SET) of phase-change memory cells in phase-change memory requires hundreds of nanoseconds to several milliseconds of current heating time. Since SET programming is much longer than RESET programming time, the programming speed of the phase change memory is mainly determined by the SET programming time. Reducing the SET programming time is of great significance for improving the speed of the phase change memory.

Since the actual temperature of the phase-change material in a phase-change memory cell varies from cell to cell, this difference can inadvertently cause the material in one or more cells of the device to reach the melting temperature T when conventional SET pulses are applied. _m , causing these cells to remain in a high-impedance state. To avoid this problem, the traditional programming technology uses a SET pulse with a small amplitude to perform an erase operation, so as to ensure that the phase change material does not reach the melting temperature T _m when the SET pulse is applied to the phase change memory cell. This method makes the SET operation time much longer than the RESET operation time. In addition, there will be cells in the memory cell whose stable state is significantly lower than the optimal temperature, which reduces the range of SET and RESET resistance distribution in the memory cell.

Due to the OTS effect of the phase change resistance, when the voltage is applied to the phase change memory cell, when the voltage is higher than a certain switching threshold, the resistivity of the phase change memory cell will suddenly drop, but at this time the phase change resistance has not been actually programmed, if Remove the voltage, the phase change resistance will return to the original resistance. In the process of transitioning from a high-resistance state to a low-resistance state, a phase-change memory cell must first exceed the switching threshold of the material and enter a programming state. The traditional SET operation is to apply a low-amplitude rectangular pulse signal to the phase-change memory unit, and it takes a long time to enter the energy beyond the switching threshold. This part of the time is added to the crystallization induction time after entering the programming state, forming a phase-change memory cell. SET for the entire time of the wipe operation. Apparently, this lower amplitude pulse signal slows down the time for the phase-change memory cell to enter the programming state.

Contents of the invention

In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a phase-change memory flash erase operation method and a phase-change memory circuit flash erase operation method for reducing the phase-change memory unit SET programming time, thereby improving the phase change memory erasing operation speed, and improving the low resistance distribution after SET programming.

In order to achieve the above object and other related objects, the present invention provides a fast erasing and writing operation method for phase change storage. The SET programming pulse for erasing operation is sequentially a preprogramming pulse and a programming pulse, and the preprogramming pulse makes the phase change memory cell The switching threshold beyond the phase transition in the middle, the holding time is shorter than the RESET pulse operation time of the write operation, so that the memory cell can quickly enter the programming state, and then the programming pulse completes the erasing operation.

Preferably, the amplitude of the pre-programming pulse is equivalent to the amplitude of the RESET programming pulse.

Preferably, the SET programming pulse is composed of double rectangular pulses.

Preferably, the pulse width of the pre-programmed pulse is 10 ns to 100 ns, and the best pulse width is about 30 ns.

Preferably, the programming pulse is composed of a pulse with a falling edge of the decay rate.

Preferably, the decay rate of the pulse with a falling edge of the decay rate includes polynomial, logarithmic and exponential.

The present invention also provides a fast erasing and writing operation method of a phase-change storage circuit. The phase-change storage circuit for the fast erasing and writing operation includes a logic control circuit, a memory cell array, a drive circuit and a word line respectively communicated with the logic control circuit. A gating tube, a bit line gating tube and a read circuit; the word line gating tube and the bit line gating tube are respectively communicated with the memory cell array; the read circuit is communicated with the bit line gating tube; the drive circuit includes A number of current pulses of different sizes provided by the current mirror; the logic control module controls the switch and conduction time of each channel; when performing the erase operation SET programming, each channel is opened to form a pre-programmed pulse, which flows into the bit line gating tube , and then flow into the selected phase-change memory cell to complete the pre-programming operation; then turn off the large current path, and the output programming pulse programs the selected phase-change memory cell, and the pre-programming pulse makes the phase-change memory cell surpass the phase-change The switching threshold, the hold time is less than the RESET pulse operation time of the write operation.

Preferably, when performing SET programming, the amplitude of the pre-programmed pulse is equivalent to the amplitude of the RESET pulse, and its pulse width is 10 ns to 100 ns, and the pulse width is about 30 ns.

Preferably, after the pre-programming operation is completed, all current paths are sequentially turned off so as to form pulses with stepped falling edges.

Preferably, the word line gate transistor and the bit line gate transistor are selected from MOS transistors, triodes or diodes.

As mentioned above, a method for fast erasing and writing operation of phase-change storage and a method for quickly erasing and writing operation of phase-change memory circuit according to the present invention have the following beneficial effects:

In the present invention, before applying the ordinary SET pulse, a large-amplitude, short-time pre-programming pulse is first applied, so that all phase-change memory cells exceed the switching threshold of the phase-change and quickly enter the programming state, and the programming pulse applied subsequently can use a shorter Time will complete the transformation from high resistance to low resistance, and has a better low resistance distribution.

Description of drawings

FIG. 1 is a schematic diagram of a traditional erasing operation pulse wave for programming a traditional phase change memory in the prior art.

FIG. 2 is a schematic diagram of a dual rectangular SET pulse wave for the erasing operation of the phase change memory of the present invention.

FIG. 3 is a schematic diagram of a SET pulse wave with a falling edge of decay rate for the erasing operation of the phase-change memory of the present invention.

FIG. 4 is a circuit block diagram of the flash phase change memory of the present invention.

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

Due to the OTS effect of the phase change resistance, when the pulse is applied to the phase change resistance unit, when the voltage is higher than a certain switching threshold, the resistivity of the phase change resistance unit will suddenly drop, but at this time the phase change resistance has not been actually programmed, if When the voltage is removed, the phase change resistance will return to the original resistance value. The pulse operation after the threshold voltage is exceeded is the real programming pulse. We call the pulse used to exceed the threshold value a pre-programmed pulse.

The SET pulse used for erasing the phase-change memory can be divided into two parts, a pre-programming pulse and a programming pulse. The first is to apply a pre-programmed pulse: its pulse amplitude is equivalent to that of the RESET pulse, and the hold time is about tens of nanoseconds, which is less than the RESET operation time, so that the phase-change material in the device unit can quickly exceed the switching threshold in a short period of time and enter programming state. Then the SET pulse is converted into a programming pulse: its amplitude is low, and it is kept for a certain period of time, so that the device unit reaches a temperature near the crystallization temperature T _opt , and better crystallization occurs during this period, and the phase change unit is transformed into a low-resistance state.

We know that the important feature of the RESET write operation is that when a high-amplitude pulse signal is applied, the storage material first reaches the switching threshold, and after entering the RESET programming state, quickly removing the pulse signal can keep the memory cell in the amorphous state, as shown in Figure 1 RESET programming pulse is shown. Therefore, when the initial amplitude of the SET pulse is greater than that of the traditional SET pulse, the memory can reach the temperature above _Tm , exceed the switching threshold, and enter the programming state. time, and its subsequent pulse amplitude is attenuated to a lower pulse amplitude, so that the temperature of the phase change material is reduced to around the crystallization temperature T _opt , and directly enters the SET programming state.

As a preferred solution of the present invention, the SET programming pulse is composed of double rectangular pulses, as shown in FIG. 2 . Pulse 1 is a pre-programmed pulse, its amplitude is equivalent to the RESET pulse, the current reaches I ₁ , and the time is about 30ns, which is less than the RESET write operation time, so that the phase-change memory cell exceeds the switching threshold and enters the programming state. Pulse 2 is a programming pulse: its pulse amplitude is equivalent to that of traditional SET pulses, and its current is about I ₂ . Since it has exceeded the switching threshold, its time will be much shorter than the traditional SET heating time. Two pulses are applied to the phase-change memory cell to form a double-pulse fast SET erase operation.

As another preferred solution of the present invention, the SET programming pulse is composed of a pre-programming pulse and a programming pulse with a falling edge with a variable slope, as shown in FIG. 3 . After applying the pre-programming pulse, the phase-change unit quickly exceeds the switching threshold and enters the programming state. Applying a programming pulse with a variable slope on the falling edge can increase the range of crystallization temperature of the memory cell, and the current amplitude can be in as many phases as possible. The crystallization temperature T _opt is generated in variable cells in order to provide optimal SET operation resistance distribution for these cells. Wherein, the slope decay rate of the trailing edge part may include polynomial, logarithmic, exponential and so on.

The speed of the current phase change memory write operation (that is, the RESET programming process) is in the range of tens of nanoseconds to hundreds of nanoseconds, while the speed of the erasing operation (that is, the SET programming process) is on the order of milliseconds. The RESET and SET programming processes Both need to exceed the switching threshold of the phase-change memory cell first, and then enter the programming state. If the phase-change memory cell can be quickly exceeded its switching threshold during the SET programming process, the erasing operation time can be increased, and the programming speed of the phase-change memory will be greatly improved.

In one embodiment, the SET pulse used for erasing the phase change memory is divided into two parts, a pre-program pulse and a program pulse. The first is to apply a pre-programmed pulse: its pulse amplitude is equivalent to that of the RESET pulse, and the pulse width is about 10ns~100ns, preferably about 30ns, which is less than the RESET operation time, so that the phase change material in the memory cell can quickly surpass it in a short period of time. switch threshold, enter the programming state. Then turn the SET pulse into a programming pulse: its amplitude is low, and it is kept for a certain period of time, so that the memory cell reaches a temperature near the crystallization temperature Topt, and better crystallization occurs during this period, and the phase-change memory cell changes into a low-resistance state.

See Figures 1 through 4. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

Example 1

FIG. 4 is a block diagram of a flash phase-change memory circuit of the present invention, including a drive circuit, a memory array, a decoding circuit and a read circuit. Wherein, the driving circuit provides programming operation for the phase-change memory cell. The memory array is composed of phase-change memory cells connected in series with gate transistors, wherein the gate transistors can be MOS transistors, triodes, diodes, and the like. The switch of the gate transistor is controlled by the word line, and when the phase-change memory cell needs to be erased, a specific word line and bit line are selected by the word line gate circuit and the bit line gate circuit. The driving circuit generates an erase operation current pulse, which flows to the selected bit line, and the selected bit line is connected with the memory unit, so that the current can flow through the memory unit.

The design of the programming operation is completed by the drive circuit. The usual control circuit is: the current mirror provides several currents of different sizes, and the logic control module controls the switching and conduction time of each current. As shown in FIG. 2 , when performing RESET programming, the maximum current is generally selected, and the conduction time is tens of nanoseconds to hundreds of nanoseconds. When performing SET programming, firstly open all current paths, and the conduction time is controlled between 10ns and 100ns, preferably about 30ns, and the pre-programming operation is completed, and then the large current pulse path is turned off, and the small current pulse path is kept until the end of programming. Its current pulse flows to the gate phase-change memory cell through the bit line to complete the erasing operation. The preprogram and program pulses are double rectangles.

Example 2

As the second preferred embodiment of the present invention, for a phase-change memory with scattered low-resistance distribution caused by process manufacturing, temperature, materials, etc., when performing SET programming, as shown in Figure 3, first open all current paths and keep them turned on The time is between 10 ns and 100 ns, preferably about 30 ns, to complete the pre-programming operation, and then the programming pulse current path is controlled by the logic control circuit, which can be selected to be turned off sequentially to form a current pulse with a stepped falling edge. Different logic control operations can form current pulses with different falling edge forms, which flow into the phase-change memory cells. While increasing the SET programming speed, it also improves the consistency of resistance distribution.

Example 3

For the fast SET operation, different driving methods can be used to complete it, including a slightly modified logic control module, a driving circuit module, and the like. The fast SET operation can also be completed regardless of the circuit operation in the chip, and the fast erase operation can be performed by sending the above-mentioned SET pulse to the phase-change memory unit by an external device.

In summary, the present invention relates to a method of fast erasing and writing operation of a phase change memory using a phase change material as a phase change memory unit and a method of rapidly erasing and writing a phase change memory circuit, the purpose of which is to improve the performance of the phase change memory unit. SET programming speed. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. For example, the phase-change material can be a chalcogenide alloy or a phase-change material with other suitable structures that can be used as a programmable phase-change memory; the pulse signal can be a current pulse or a voltage pulse; the driving mode of the SET pulse can be determined by the chip It can be done by internal circuit or by external equipment. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of the present invention.

Claims (10)

1. A fast erasing and writing operation method of phase-change storage, characterized in that, the SET programming pulse for wiping operation is successively a pre-programming pulse and a programming pulse, and the pre-programming pulse makes the phase-change memory cell exceed the switching threshold of the phase-change , the hold time is less than the RESET pulse operation time of the write operation. 2 . The method for flash erasing and writing operation of phase change memory according to claim 1 , wherein the amplitude of the pre-programming pulse is equivalent to the amplitude of the RESET programming pulse. 3 . 3 . The method for fast erasing and writing operation of phase change memory according to claim 2 , wherein the SET programming pulse is composed of double rectangular pulses. 4 . 4 . The flash erasing and writing operation method of phase change memory according to claim 1 , wherein the pulse width of the preprogramming pulse is 10 ns to 100 ns. 5 . The flash erasing and writing operation method of phase change storage according to claim 1 , wherein the programming pulse is composed of a pulse with a falling edge of decay rate. 6 . 6 . The fast erasing and writing operation method of phase change storage according to claim 5 , wherein the decay rate of the pulse with a falling edge of the decay rate includes polynomial, logarithmic and exponential. 7 . 7. A quick erasing and writing operation method of a phase-change storage circuit, characterized in that: the phase-change storage circuit of the quick erasing and writing operation includes a logic control circuit, a memory cell array, and a drive circuit respectively communicated with the logic control circuit, A word line gating tube, a bit line gating tube and a read circuit; the word line gating tube and the bit line gating tube are respectively communicated with the memory cell array; the read circuit is connected with the bit line gating tube; the drive The circuit includes a number of current pulses with different sizes provided by the current mirror; the logic control module controls the switch and conduction time of each channel; when performing the erase operation SET programming, each channel is opened to form a pre-programmed pulse, which flows into the bit line selection The pass tube then flows into the selected phase-change memory cell to complete the pre-programming operation; then the large current path is turned off, and the output programming pulse programs the selected phase-change memory cell; the pre-programming pulse makes the phase-change memory cell surpass The switching threshold of the phase change, the holding time is less than the RESET pulse operation time of the write operation. 8 . The method for fast erasing and writing operation of a phase-change memory circuit according to claim 7 , wherein the amplitude of the preprogramming pulse is equivalent to the amplitude of the RESET pulse, and the pulse width is 10 ns to 100 ns. 9. The method for fast erasing and writing operation of a phase-change memory circuit according to claim 7, characterized in that: after the pre-programming operation is completed, all current paths are sequentially turned off to form pulses with stepped falling edges . 10 . The fast erasing and writing operation method of a phase change memory circuit according to claim 7 , wherein the word line gate transistor and the bit line gate transistor are selected from MOS transistors, triodes or diodes. 11 .

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