CN101359504A - High speed recording phase change memory and high speed recording method thereof - Google Patents

High speed recording phase change memory and high speed recording method thereof Download PDF

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Publication number
CN101359504A
CN101359504A CNA2008100414158A CN200810041415A CN101359504A CN 101359504 A CN101359504 A CN 101359504A CN A2008100414158 A CNA2008100414158 A CN A2008100414158A CN 200810041415 A CN200810041415 A CN 200810041415A CN 101359504 A CN101359504 A CN 101359504A
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phase change
change memory
address
data
high speed
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CN101359504B (en
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富聪
宋志棠
蔡道林
封松林
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Shanghai Institute of Microsystem and Information Technology of CAS
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Shanghai Institute of Microsystem and Information Technology of CAS
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Abstract

The invention relates to a high-speed write-in phase change memory and a high speed write-in method. The high-speed write-in phase change memory comprises at least two independent address registers, a date register, an SET drive circuit, a column gate, a phase change resistor memory array, a line address decoder and a column address encoder. The high-speed write-in phase change memory conducts write-in operation to a plurality of phase change storing units corresponding to different addresses, so the date write-in period is shorter than the write-in period of conventional phase change storing units, thus improving the write-in speed of the phase change memory.

Description

High speed recording phase change memory and high-speed writing method thereof
Technical field
The invention belongs to technical field of semiconductor memory, relate to a kind of storer, relate in particular to a kind of high speed recording phase change memory and high-speed writing method thereof.
Background technology
The phase transition storage technology is based on Ovshinsky at late 1960s (Phys.Rev.Lett., 21,1450～1453,1968) beginning of the seventies (Appl.Phys.Lett., 18,254～257,1971) phase-change thin film of Ti Chuing can be applied to that the conception of phase change memory medium sets up, and is the memory device of a kind of low price, stable performance.Phase transition storage can be made on the silicon wafer substrate, its critical material is that the research focus of recordable phase-change thin film, heating electrode material, thermal insulation material and extraction electrode material also just launches around its device technology: the physical mechanism research of device comprises how reducing device material etc.The ultimate principle of phase transition storage is to utilize electric impulse signal to act on the device cell, make phase-change material between amorphous state and polycrystalline attitude, reversible transition take place, low-resistance when high resistant during by the resolution amorphous state and polycrystalline attitude can realize writing, wipe and read operation of information.
Phase transition storage owing to have reads at a high speed, high erasable number of times, non-volatile, advantages such as component size is little, strong motion low in energy consumption, anti-and radioresistance, is thought flash memories that most possible replacement is present by international semiconductor TIA and becomes following storer main product and become the device of commercial product at first.
The reading and writing of phase transition storage, wiping operation apply the voltage or the current pulse signal of different in width and height exactly on device cell: wipe operation (RESET), after phase-change material temperature in adding a weak point and strong pulse enable signal device cell is elevated to more than the temperature of fusion, through thereby cooling realization phase-change material polycrystalline attitude is to amorphous conversion fast, promptly one state is to the conversion of " 0 " attitude again; Write operation (SET), when apply one long and pulse enable signal phase-change material temperature medium tenacity is raised under the temperature of fusion, on the Tc after, and keep a period of time to impel nucleus growth, thus realize the conversion of amorphous state to the polycrystalline attitude, promptly " 0 " attitude is to the conversion of one state; Read operation behind the pulse signal that adds a little less than in the of, is read its state by the resistance value of measuring element unit.
The problem that phase transition storage also exists self needs to solve.Owing to be written in the process of data at phase transition storage, the speed of RESET operation will be faster than the speed of SET operation, and as a rule the SET running time roughly is the twice of RESET running time.The ablation process of most phase transition storage, all be that long numeric data is written in parallel to, if long numeric data is different value, that is, need write " RESET " state with phase-splitting power transformation resistance unit, a write operation middle part, the partial phase change resistance unit need write " SET " state, RESET operation FEFO then can take place, after waiting for that the SET operation is finished, just the data parallel that can carry out next time writes, i.e. the mono-recordable angle of incidence of phase change cells was determined by the longest SET running time.
Summary of the invention
Technical matters to be solved by this invention provides a kind of high speed recording phase change memory, can carry out write operation to many groups corresponding to the phase-change memory cell under the different addresses simultaneously, make data write cycles less than traditional phase-change memory cell, thereby improve the writing speed of phase transition storage.
For addressing the above problem, the present invention adopts following technical scheme: a kind of high speed recording phase change memory, described high speed recording phase change memory comprise address register and
Data register is used to store long numeric data;
The SET driving circuit is used for driving simultaneously being written in parallel to of long numeric data;
Column gate is used for choosing simultaneously logical multiple bit lines;
Row address decoder;
Column address decoder;
The phase change resistor storage array; By described column gate, row address decoder and column address decoder control;
Read amplifying circuit;
The RESET driving circuit;
Logic control circuit; Be used to control the connection between each circuit;
Wherein, described high speed recording phase change memory comprises at least two separate address registers, data register, SET driving circuit, column gate, phase change resistor storage array, row address decoder and column address decoder.
As the described separate address register of one of preferred version of the present invention, data register, SET driving circuit, column gate, phase change resistor storage array, row address decoder and column address decoder number is three.
Comprise one or three separate RESET driving circuits as this high speed recording phase change memory of one of preferred version of the present invention.
The present invention further comprises a kind of method that high speed recording phase change memory realizes that high speed writes of using, and this method may further comprise the steps:
Step 1, CS signal controlling address and data register, the rising edge of CS signal triggers address and data register;
Step 2, first group of data that will write and corresponding address with it, be deposited with in first address and first data register, and through a bit of time delay, treat a SET driving circuit and RESET driving circuit behind the signal stabilization, work simultaneously, to by first row address decoder, first phase change memory array of first column address decoder and the control of first column gate carries out data and writes;
Step 3, after the RESET operation is finished, do not wait for that a SET driving circuit finishes write operation, second rising edge of CS signal triggers second address and second data register, with second group of data that will write and corresponding address with it, be deposited with in second address and second data register, and through a bit of time delay, after treating signal stabilization, the 2nd SET driving circuit and RESET driving circuit, work simultaneously, to by second row address decoder, second phase change memory array of secondary series address decoder and the control of secondary series gate carries out data and writes;
Step 4 by that analogy, continues to write continuously data.
The invention provides a kind of high speed recording phase change memory, can carry out write operation to many groups corresponding to the phase-change memory cell under the different addresses simultaneously, make data write cycles, thereby improve the writing speed of phase transition storage less than traditional phase-change memory cell.
Description of drawings
Fig. 1 high speed recording phase change memory structural representation of the present invention;
Fig. 2 high speed recording phase change memory of the present invention writes the sequential chart under the pattern;
Fig. 3 high speed recording phase change memory of the present invention writes the another kind of sequential chart under the pattern.
Embodiment
Be described in further detail below in conjunction with the enforcement of accompanying drawing technical scheme:
Present invention resides in and use a plurality of address registers in the high speed recording phase change memory, many sets of data register (wherein a sets of data register can be stored long numeric data), the separate set driving circuit of many covers (wherein a cover set driving circuit can drive being written in parallel to of long numeric data simultaneously), word line gate that many covers are separate or title column gate (wherein a cover column gate can be chosen logical multiple bit lines simultaneously), the phase change resistor storage array, many cover line decoders, many cover column decoders, logic control circuit, read amplifying circuit, one overlaps or overlaps more the reset driving circuit.
For further illustrating substantive distinguishing features of the present invention and obvious improvement, the present invention is described below by embodiment:
Please refer to shown in Figure 1, high speed recording phase change memory of the present invention uses three cover address registers, three sets of data registers, every sets of data register has 8, byte data that will the recording phase change storage array is deposited with wherein, three overlap independently set driving circuit, every cover driving circuit is supported being written in parallel to of 8 bit data at most, the separate word line gate of three covers, and wherein every cover column gate can be chosen logical 8 bit lines simultaneously and insert set driving circuit and reset driving circuit, the phase change resistor storage array, three cover line decoders, three cover column decoders, logic control circuit, read amplifying circuit, one overlaps or overlaps more the reset driving circuit.
High speed recording phase change memory 100 of the present invention, comprise row address decoder 101, (wherein D is meant the gating diode to the phase change cells storage array of being made up of 1D1R 102, R is meant the phase change resistor unit), column gate (word line gate) and column decoder 103, write the SET driving circuit 104 in the driving circuit, RESET driving circuit 105, read amplifying circuit 106, address and data register 107, logic control circuit 108, the principal feature of this circuit is, in data writing process, be written in parallel to the averaging time of 8 bit data in each address, less than the SET running time of phase-change memory cell.Storage unit of the present invention is not limited only to the 1D1R structure, also can be structures such as 1T1R.
Row address decoder 101 comprises row address decoder 1, row address decoder 2, row address decoder 3, three row address decoder are separate being controlled by logic control circuit 108, and in each row address decoder, when a word line is that low level is represented to choose, all the other word lines are high level, and expression is not chosen.The 102nd, the phase change cells storage array of forming by 1D1R (wherein D is meant the gating diode, and R is meant the phase change resistor unit).The 103rd, column gate 1 (word line gate) and column decoder 1, column gate 2 and column decoder 2, column gate 3 and column decoder 3, and column gate k is by column decoder k control, k=1,2,3.The 104th, SET driving circuit 1, SET driving circuit 2, SET driving circuit 3, three cover driving circuits are separate, behind the SET driving circuit k process column gate k, respectively the phase change cells storage array carried out SET operation, k=1,2,3.105 is the shared RESET driving circuit of high speed recording phase change memory, can carry out the RESET operation to the phase change resistor in the array, and among the present invention, the RESET driving circuit also can use independently a plurality of, is not limited in a cover.106 for high speed recording phase change memory shared read amplifying circuit.107 is three cover address and data registers, wherein address and data register k, and that corresponding is line decoder k, column decoder k and column gate k, the data that data register k deposits are will write in the address that address register k deposits, k=1 wherein, 2,3.Logic control circuit 108 is controlled the connection between above-mentioned the circuit.
Please be simultaneously with reference to shown in Figure 2, wherein WE is for writing enable signal, and high level is effective, and OE is for reading enable signal, and high level is effective.CS signal controlling address and data register, the rising edge of CS signal triggers address and data register, as seen from Figure 2, first CS signal rising edge triggers address and data register 1, first group of (8) data DATA1 that will write and corresponding address ADD1 with it, be deposited with in address and the data register 1, and through a bit of time delay, treat SET1 driving circuit and RESET driving circuit behind the signal stabilization, work simultaneously, to by row address decoder 1, the phase change memory array 1 of column address decoder 1 and column gate 1 control carries out data and writes; After the RESET operation is finished, do not wait for that SET1 drives and finish write operation, second rising edge trigger data of CS signal and address register 2, with second group of data DATA2 that will write and corresponding address ADD2 with it, be deposited with in data and the address register 2, and through a bit of time delay, after treating signal stabilization, SET2 driving circuit and RESET driving circuit, work simultaneously, to by row address decoder 2, the phase change memory array 2 of column address decoder 2 and column gate 2 controls carries out data and writes, and this moment, the SET1 driving circuit still might write in that phase change memory array 1 is carried out data; After the RESET operation is finished once more, do not wait for that SET2 drives and finish write operation, the 3rd rising edge trigger data of CS signal and address register 3, with the 3rd group of data DATA3 that will write and corresponding address ADD3 with it, be deposited with in data and the address register 3, and through a bit of time delay, treat SET3 driving circuit and RESET driving circuit behind the signal stabilization, work simultaneously, to by row address decoder 3, the phase change memory array 3 of column address decoder 3 and column gate 3 controls carries out data and writes, and this moment, the SET2 driving circuit still might write in that phase change memory array 2 is carried out data; After the RESET operation is finished once more, do not wait for that SET3 drives and finish write operation, the 4th rising edge trigger data of CS signal and address register 1, with the 4th group of data DATA4 that will write and corresponding address ADD4 with it, be deposited with in data and the address register 1, and through a bit of time delay, treat SET1 driving circuit and RESET driving circuit behind the signal stabilization, work simultaneously, to by row address decoder 1, the phase change memory array 1 of column address decoder 1 and column gate 1 control carries out data and writes; This moment, the SET3 driving circuit still might write in that phase change memory array 3 is carried out data.By that analogy, continue to write continuously data.As seen from Figure 2, the write time of one group of data of the present invention approximates the cycle that the CS signal faces rising edge mutually, and this cycle be less than the time of SET operation, be slightly larger than the RESET running time.That is, improved the writing speed of phase transition storage less than the SET running time averaging time that single group data write.
Please be simultaneously with reference to shown in Figure 3, difference on the work schedule of itself and Fig. 2 is, when first rising edge of CS comes, do not trigger SET driving circuit and RESET driving circuit, when second rising edge of CS comes, trigger SET circuit and RESET circuit, promptly SET driving circuit and RESET drive and compare the CS cycling that lags behind with Fig. 2.
Playback mode of the present invention can no longer be listed here with reference to traditional phase transition storage.
Above embodiment is the unrestricted technical scheme of the present invention in order to explanation only.As, the 3 cover address date registers that are not limited only to use in the example, 3 cover row address decoder, 3 cover SET driving circuits, the number of 3 cover column address decoder and column selection circuit passband, 2 covers or the above address date register of 2 covers, row address decoder, SET driving circuit, column address decoder and column selection circuit passband all are included in the scope of the present invention; If for specific phase change resistor, the SET running time may be much larger than 2 times of RESET running times, can suitably use features such as more cover address date registers, row address decoder, SET driving circuit, column address decoder and column selection circuit passband all not break away from spirit and scope of the invention, all should be encompassed in the middle of the patent claim of the present invention.

Claims (4)

1. high speed recording phase change memory, described high speed recording phase change memory comprises address register and data register, is used to store long numeric data and multidigit address;
The SET driving circuit is used for driving simultaneously being written in parallel to of long numeric data;
Column gate is used for choosing simultaneously logical multiple bit lines;
Row address decoder;
Column address decoder;
The phase change resistor storage array; By described column gate, row address decoder and column address decoder control;
Read amplifying circuit;
The RESET driving circuit;
Logic control circuit; Be used to control the connection between each circuit;
It is characterized in that: described high speed recording phase change memory comprises at least two separate address registers, data register, SET driving circuit, column gate, phase change resistor storage array, row address decoder and column address decoder.
2. high speed recording phase change memory as claimed in claim 1 is characterized in that: described separate address register, data register, SET driving circuit, column gate, phase change resistor storage array, row address decoder and column address decoder number are three.
3. high speed recording phase change memory as claimed in claim 2 is characterized in that: this high speed recording phase change memory comprises one or three separate RESET driving circuits.
4. an application rights requires 1 described high speed recording phase change memory to realize the method that writes at a high speed, it is characterized in that this method may further comprise the steps:
Step 1, CS signal controlling address and data register, the rising edge of CS signal triggers address and data register;
Step 2, first group of data that will write and corresponding address with it, be deposited with in first address and first data register, and through a bit of time delay, treat a SET driving circuit and RESET driving circuit behind the signal stabilization, work simultaneously, to by first row address decoder, first phase change memory array of first column address decoder and the control of first column gate carries out data and writes;
Step 3, after the RESET operation is finished, do not wait for that a SET driving circuit finishes write operation, second rising edge of CS signal triggers second address and second data register, with second group of data that will write and corresponding address with it, be deposited with in second address and second data register, and through a bit of time delay, after treating signal stabilization, the 2nd SET driving circuit and RESET driving circuit, work simultaneously, to by second row address decoder, second phase change memory array of secondary series address decoder and the control of secondary series gate carries out data and writes;
Step 4 by that analogy, continues to write continuously data.
CN2008100414158A 2008-08-05 2008-08-05 High speed recording phase change memory and high speed recording method thereof Active CN101359504B (en)

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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101783171B (en) * 2009-12-24 2012-07-04 中国科学院上海微系统与信息技术研究所 Burst write method for phase change memory
CN101783172B (en) * 2009-12-24 2012-07-04 中国科学院上海微系统与信息技术研究所 Phase change memory
CN102568573A (en) * 2010-12-31 2012-07-11 上海丽恒光微电子科技有限公司 Micro electro mechanical system (MEMS) nonvolatile memory and memory units
CN103295627A (en) * 2013-04-23 2013-09-11 华为技术有限公司 Phase change memory, data-parallel writing method and data reading method
CN104051009A (en) * 2014-06-20 2014-09-17 中国科学院微电子研究所 Gating circuit and gating method of resistive random access memory (RRAM)
CN105264608A (en) * 2014-04-30 2016-01-20 华为技术有限公司 Data storage method, memory controller and central processing unit
CN105453182A (en) * 2014-07-24 2016-03-30 华为技术有限公司 Data storage method and control device for phase-change memory
US10083749B2 (en) 2014-07-24 2018-09-25 Huawei Technologies Co., Ltd Data storage method and phase change memory
CN108616675A (en) * 2018-04-09 2018-10-02 中国科学院上海高等研究院 A kind of down-sampled circuit and down-sampled method
CN111627481A (en) * 2020-05-20 2020-09-04 中国科学院微电子研究所 Word line decoding circuit, word line gating method, memory and electronic equipment

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101783172B (en) * 2009-12-24 2012-07-04 中国科学院上海微系统与信息技术研究所 Phase change memory
CN101783171B (en) * 2009-12-24 2012-07-04 中国科学院上海微系统与信息技术研究所 Burst write method for phase change memory
CN102568573A (en) * 2010-12-31 2012-07-11 上海丽恒光微电子科技有限公司 Micro electro mechanical system (MEMS) nonvolatile memory and memory units
CN102568573B (en) * 2010-12-31 2014-11-05 张家港丽恒光微电子科技有限公司 Micro electro mechanical system (MEMS) nonvolatile memory and memory units
CN103295627B (en) * 2013-04-23 2016-08-31 华为技术有限公司 Phase transition storage, data parallel wiring method and method for reading data
CN103295627A (en) * 2013-04-23 2013-09-11 华为技术有限公司 Phase change memory, data-parallel writing method and data reading method
CN105264608A (en) * 2014-04-30 2016-01-20 华为技术有限公司 Data storage method, memory controller and central processing unit
CN105264608B (en) * 2014-04-30 2018-03-06 华为技术有限公司 Method, Memory Controller Hub and the central processing unit of data storage
CN104051009A (en) * 2014-06-20 2014-09-17 中国科学院微电子研究所 Gating circuit and gating method of resistive random access memory (RRAM)
CN104051009B (en) * 2014-06-20 2017-02-15 中国科学院微电子研究所 Gating circuit and gating method of resistive random access memory (RRAM)
CN105453182A (en) * 2014-07-24 2016-03-30 华为技术有限公司 Data storage method and control device for phase-change memory
US10083749B2 (en) 2014-07-24 2018-09-25 Huawei Technologies Co., Ltd Data storage method and phase change memory
CN108616675A (en) * 2018-04-09 2018-10-02 中国科学院上海高等研究院 A kind of down-sampled circuit and down-sampled method
CN108616675B (en) * 2018-04-09 2020-09-04 中国科学院上海高等研究院 Down-sampling circuit and down-sampling method
CN111627481A (en) * 2020-05-20 2020-09-04 中国科学院微电子研究所 Word line decoding circuit, word line gating method, memory and electronic equipment
CN111627481B (en) * 2020-05-20 2022-02-01 中国科学院微电子研究所 Word line decoding circuit, word line gating method, memory and electronic equipment

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