CN108616675A - A kind of down-sampled circuit and down-sampled method - Google Patents
A kind of down-sampled circuit and down-sampled method Download PDFInfo
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- CN108616675A CN108616675A CN201810312197.0A CN201810312197A CN108616675A CN 108616675 A CN108616675 A CN 108616675A CN 201810312197 A CN201810312197 A CN 201810312197A CN 108616675 A CN108616675 A CN 108616675A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0102—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving the resampling of the incoming video signal
Abstract
The present invention provides a kind of down-sampled circuit of resource-conserving and down-sampled method, and signal and row selects signal and two the first registers and the second register being configured to temporarily store are selected using position, can solve the problems, such as that input image data stream all caches.Fairly large input picture is reduced to a quarter of artwork size by the present invention, and output does not change the whole minutia of original image；The dimension that input picture can be reduced, compared to the input for preserving all data flows with intermediate storage, the present invention only needs two registers, reduces the consumption of memory；Distribute bright down-sampled method and improve calculating speed, can be realized on programmable logic device FPGA.So the present invention effectively overcomes various shortcoming in the prior art and has high industrial utilization.
Description
Technical field
The present invention relates to image data samples field of circuit technology, more particularly to a kind of down-sampled circuit and down-sampled side
Method.
Background technology
With the promotion of technique for taking, people have high-resolution image higher and higher demand, while adjoint
The development of artificial intelligence, the algorithm of image recognition has also obtained development energetically.Algorithm is being carried out to high-resolution image
In series of computation when, especially nowadays in the convolutional neural networks that field of target recognition has very good effect, reduce intermediate
The scale of layer result of calculation is a highly important operation.
In convolutional neural networks, pondization operation is often encountered, and pond layer passes through pond often behind convolutional layer
It reduces the feature vector of convolutional layer output, while improving over-fitting.Image has the attribute of a kind of " nature static ", this
It means that very likely equally applicable in another region in an image-region useful feature.Therefore, big in order to describe
Image, one naturally idea be exactly that aggregate statistics are carried out to the feature of different location, for example, people can calculate image
The average value (or maximum value) of some special characteristic on one region represents the feature in this region.
There are two notable advantages for pondization operation：1) after the feature for obtaining image by convolution operation, if directly using
This feature does the challenge that classification then faces calculation amount.And the result in pond can so that feature is reduced, parameter is reduced；2) pond
It can keep the rotation, translation, flexible invariance of image.
There are three types of modes for general pondization：1) average value pond is only averaging characteristic point in neighborhood, retain background
More preferably；2) maximum value pond takes maximum to characteristic point in neighborhood, more preferable to texture blending；3) random value pond, between the two
Between, by assigning probability according to numerical values recited to pixel, sub-sampling is carried out according still further to probability.The error of feature extraction is main
From two aspects：1) estimated value variance increases caused by Size of Neighborhood is limited；2) convolutional layer parameter error causes estimation mean value
Offset.In general, average value pondization can reduce the first error, more background informations for retaining image, maximum value pond
Change can reduce second of error, more retain texture information.It is approximate with average value pondization on average, in local meaning
In justice, then the criterion in maximum value pond is obeyed.
As image scale increases, the continuous increase of calculation amount, common CPU can not be in the time range that can be born
It is interior to complete this large-scale operation, therefore using hardware platforms such as GPU, FPGA, accelerated just to seem gesture must calculating
Row.
Algorithmically very simple is understandable for down-sampled process, but during the realization of hardware circuit, due to data be with
The form of data flow inputs the module, if design keeps in structure as intermediate storage, can be read by address after storage is completed
Go out and down-sampled, but this method excessively wastes storage resource.
Invention content
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of down-sampled circuits and down-sampled
Method, the calculation amount for solving the waste of sample circuit in the prior art memory space, being brought because sampled images are excessive increase with
And the problem of being difficult to go back original image entirety details.
To achieve the above object, the present invention uses following scheme：A kind of down-sampled circuit, the down-sampled circuit include：
First trigger element, the second trigger element, third trigger element, the 4th trigger element, the first register, the second register,
One comparator, the second comparator, third comparator and memory module；First trigger element, second trigger element,
The third trigger element and the 4th trigger element receives image data respectively, signal is selected in position and row selects signal, for point
Four image datas of different ranks in same sampling window are not exported；The input terminal connection described first of first register
The output end of trigger element, the output signal for depositing first trigger element；The input terminal of the first comparator point
The output end of first register and second trigger element is not connected, for first register and described the
The output signal of two trigger elements, and export the greater；The input terminal of second comparator connects the memory module and institute
State the output end of third trigger element, input signal and the third trigger element for the first comparator it is defeated
Go out signal, and exports the greater；Second register connects the output end of second comparator, for depositing described second
The output signal of comparator；The input terminal of the third comparator is separately connected second register and the 4th triggering is single
The output end of member for the output signal of second register and the 4th trigger element, and exports the greater；Institute
The output end that memory module is connected to the first comparator and the third comparator is stated, for storing the first comparator
Output signal, and finally show the output signal of the third comparator.
In an embodiment of the present invention, first trigger element include the first NOT gate, the second NOT gate, first with door and
First trigger；First NOT gate receives institute's rheme and selects signal；Second NOT gate receives the row selects signal；Described first
The output end of first NOT gate and second NOT gate is connect with the input terminal of door；The data input pin of first trigger
Reception described image data, control terminal connect the output end of described first and door.
In an embodiment of the present invention, second trigger element includes third NOT gate, second and door and the second triggering
Device；The third NOT gate receives the row selects signal；Described second connect the output end of the third NOT gate with the input terminal of door,
And it receives institute's rheme and selects signal；The data input pin of second trigger receives described in described image data, control terminal connection
Second with the output end of door.
In an embodiment of the present invention, the third trigger element includes that the 4th NOT gate, third and door and third trigger
Device；4th NOT gate receives institute's rheme and selects signal；The input terminal of the third and door connects the output end of the 4th NOT gate,
And receive the row selects signal；The data input pin of the third trigger receives described in described image data, control terminal connection
The output end of third and door.
In an embodiment of the present invention, the 4th trigger element includes the 4th and door and the 4th trigger；Described
Four receive institute's rheme with the input terminal of door selects signal and the row selects signal；The data input pin of 4th trigger receives institute
State image data, control terminal connects the output end of the described 4th and door.
In an embodiment of the present invention, first trigger, second trigger, the third trigger or institute
It is d type flip flop to state the 4th trigger.
The present invention also provides a kind of down-sampled method, the size of down-sampled window is 2*2, and the method includes following steps
Suddenly：Step 1), input image data, the image data for choosing the first row first row in down-sampled window are stored in the first register
In；Step 2), the image data for choosing the first row secondary series in down-sampled window, make ratio with the image data in the first register
Compared with, and choose image data larger in two image datas and be stored in memory module；Step 3) is chosen in down-sampled window
The image data of second row first row makes comparisons with the image data of storage in a storage module, and chooses two image datas
In larger image data be stored in the second register；Step 4), the image for choosing the second row secondary series in down-sampled window
Data are made comparisons with the image data being stored in the second register, and choose image data larger in two image datas
It is stored in memory module, as final output.
In an embodiment of the present invention, in the step 1), also input bit selects signal while input image data
And row selects signal, wherein it is 0 data for indicating odd column in down-sampled window that signal is selected in position, and it is that 1 expression is down-sampled that signal is selected in position
The data of even column in window；Row selects signal is 0 data for indicating odd-numbered line in down-sampled window, and row selects signal is that 1 expression is dropped
The data of even number line in sampling window.
In an embodiment of the present invention, the down-sampled method further includes that select signal and row selects signal to judge according to position defeated
The image data entered is located at the position in down-sampled window, and it is 0 to select signal when position, when row selects signal is 0, judges that input is adopted for drop
The image data of the first row first row in sample window；It is 1 to select signal when position, when row selects signal is 0, judges input for down-sampled window
The data of the first row secondary series in mouthful；It is 0 to select signal when position, when row selects signal is 1, second in judging input for down-sampled window
The data of row first row；It is 1 to select signal when position, when row selects signal is 1, the second row secondary series in judging input for down-sampled window
Data.
In an embodiment of the present invention, the down-sampled method further includes that the memory module is divided into N number of difference
Address location, and meet：N=M/4, N are the positive integer more than or equal to 1, wherein M is the image data in piece image
Number, M >=4.
In an embodiment of the present invention, the image data chosen in the step 4) is stored in the address of memory module
Unit is identical as the address location of memory module is stored in the middle image data chosen of the step 1).
In an embodiment of the present invention, the image data and the address in the memory module that are exported in the step 4)
Unit corresponds.
In an embodiment of the present invention, described image data are image feature value.
As described above, down-sampled circuit and the down-sampled method of the present invention, have the advantages that：
1) by fairly large input picture, it is reduced to a quarter of artwork size, output does not change the whole of original image
Body minutia；
2) dimension that input picture can be reduced, compared to the input for preserving all data flows with intermediate storage, originally
Invention only needs two registers, reduces the consumption of memory；
3) distribute bright down-sampled method and improve calculating speed, can be realized on programmable logic device FPGA.
Description of the drawings
Fig. 1 is the down-sampled circuit diagram that the present invention provides in embodiment one.
Fig. 2 is the down-sampled method flow diagram that the present invention provides in embodiment two.
Fig. 3 is the image feature value schematic diagram of down-sampled middle input.
Fig. 4 is down-sampled rear output result schematic diagram.
Component label instructions
1 first trigger element
11 first NOT gates
12 second NOT gates
13 first and door
14 first triggers
2 second trigger elements
21 third NOT gates
22 second and door
23 second triggers
3 third trigger elements
31 the 4th NOT gates
32 thirds and door
33 third triggers
4 the 4th trigger elements
41 the 4th and door
42 the 4th triggers
5 first registers
6 second registers
7 first comparators
8 second comparators
9 third comparators
10 memory modules
Date image datas
Pos are selected signal
Lval row selects signals
Data image datas
The first registers of Reg1
The second registers of Reg2
FM memory modules
S1~S16 steps
Specific implementation mode
Illustrate that embodiments of the present invention, those skilled in the art can be by this specification below by way of specific specific example
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.It should be noted that in the absence of conflict, following embodiment and implementation
Feature in example can be combined with each other.
It should be noted that the diagram provided in following embodiment only illustrates the basic structure of the present invention in a schematic way
Think, though component count, shape and size when only display is with related component in the present invention rather than according to actual implementation in diagram
Draw, when actual implementation kenel, quantity and the ratio of each component can be a kind of random change, and its assembly layout kenel
It is likely more complexity.
Embodiment one
Referring to Fig. 1, the present invention provides a kind of down-sampled circuit, the down-sampled circuit includes：First trigger element 1,
Second trigger element 2, third trigger element 3, the 4th trigger element 4, the first register 5, the second register 6, first comparator
7, the second comparator 8, third comparator 9 and memory module 10.
First trigger element 1, second trigger element 2, the third trigger element 3 and the 4th triggering are single
Member 4 receives image data respectively, signal and row selects signal are selected in position, and four for exporting different ranks in same sampling window respectively
A image data.
The input terminal of first register 5 connects the output end of first trigger element 1, for depositing described first
The output signal of trigger element 1；The input terminal of the first comparator 7 is separately connected first register 5 and described second
The output end of trigger element 2 for the output signal of first register 5 and second trigger element 2, and exports
The greater；The input terminal of second comparator 8 connects the output end of the memory module 10 and the third trigger element 3,
The output signal of input signal and the third trigger element 3 for the first comparator 7, and export the greater.
Second register 6 connects the output end of second comparator 8, for depositing second comparator 8
Output signal；The input terminal of the third comparator 9 is separately connected second register 6 and the 4th trigger element 4
Output end for the output signal of second register 6 and the 4th trigger element 4, and exports the greater.
The memory module 10 is connected to the output end of the first comparator 7 and the third comparator 9, for storing
The output signal of the first comparator 7, and finally show the output signal of the third comparator 9.
In this embodiment, first trigger element 1 include the first NOT gate 11, the second NOT gate 12, first and door 13 and
First trigger 14；First NOT gate 11 receives institute's rheme and selects signal；Second NOT gate 12 receives the row selects signal；Institute
State the first output end that first NOT gate 11 and second NOT gate 12 are connect with the input terminal of door 13；First trigger
14 data input pin receives described image data, control terminal connects the output end of described first and door 13.
In this embodiment, second trigger element 2 includes third NOT gate 21, second and door 22 and the second trigger
23；The third NOT gate 21 receives the row selects signal；Described second connect the third NOT gate 21 with the input terminal of door 22
Output end, and receive institute's rheme and select signal；The data input pin of second trigger 23 receives described image data, control terminal
Connect the output end of described second and door 22.
In this embodiment, the third trigger element 3 includes the 4th NOT gate 31, third and door 32 and third trigger
33；4th NOT gate 31 receives institute's rheme and selects signal；The third connect the 4th NOT gate 31 with the input terminal of door 32
Output end, and receive the row selects signal；The data input pin of the third trigger 33 receives described image data, control terminal
Connect the output end of the third and door 32.
In this embodiment, the 4th trigger element 4 includes the 4th and door 41 and the 4th trigger 42；Described 4th with
The input terminal of door 41 receives institute's rheme and selects signal and the row selects signal；The data input pin of 4th trigger 42 receives institute
State image data, control terminal connects the output end of the described 4th and door 41.
In this embodiment, the input terminal of first NOT gate 11, described second with the first input end of door 22, described the
The input terminal of four NOT gates 31 and the described 4th select signal Pos with the equal input bit of first input end of door 41；Second NOT gate 12
Input terminal, the input terminal of the third NOT gate 21, the second input terminal of the third and door 32 and the described 4th with door 41
Second input terminal inputs row selects signal Lval；The first input end of first trigger 14, second trigger 23
The first input end of first input end, the first input end of the third trigger 33 and the 4th trigger 42 inputs figure
As data Date.
In this embodiment, first trigger 14, second trigger 23, the third trigger 33 and described
4th trigger 42 is d type flip flop.
In this embodiment, described image data are image feature value.
Circuit operation principle：Position select signal Pos and row selects signal Lval by NOT gate and/or with the combination of door, obtain not
Same control signal, to enable trigger, when enable signal is high level, image data Date can just be effectively entered
Corresponding trigger.In this embodiment, when the position of input selects signal Pos and row selects signal Lval inputs to be 0, only the
One exports high level with door 13, to enable the first trigger 14, at this point, selecting signal Pos and row selects signal Lval defeated simultaneously with position
The image data Date entered is driven into the first trigger 14, and image data Date is stored in the first register 5 later；Work as input
When to select signal Pos be 1, row selects signal Lval is 0 for position, only second exports high level with door 22, to enable the second trigger
23, at this point, the image data Date of input is driven into the second trigger 23, then by the image data in the second trigger 23
Date is compared with the image data Date in the first register 5 by first comparator 7, and larger image data is selected
Date is stored in corresponding position in memory module 10.
When it is 0 to select signal Pos when the position of input, row selects signal Lval is 1, only third exports high level with door 32, comes
Enabled third trigger 33, at this point, the image data Date of input is driven into third trigger 33, and will be in third trigger 33
The image data Date and image data Date in memory module 10 be compared by the second comparator 8, select larger
Image data Date is stored in the second register 6；When it is 1 to select signal Pos when the position of input, row selects signal Lval is 1, the only the 4th
High level is exported with door 41, to enable the 4th trigger 42, at this point, the image data Date of input is driven into the 4th trigger
42, the image data Date in the image data Date and the second register 6 in the 4th trigger 42 is passed through into third comparator 9
It is compared, selects image data Date larger in the two, be stored in memory module 10 as the image data finally stored
Date.It should be noted that if the image data Date of last time deposit memory module 10 and the picture number being stored in before
It is inconsistent according to Date, then with the image data Date before the image data Date coverings of current (last time), because finally
The image data Date being once stored in is the maximum value of image data Date namely final image feature value in primary sampling.
Embodiment two
The present invention also provides a method of sampling, the size of down-sampled window is 2*2, i.e. two row, two row, four data are described
Method includes the following steps：
Step 1), input image data choose the image data of the first row first row in down-sampled window, by described image
Data are stored in the first register.
As an example, also input bit selects signal and row selects signal while input image data, wherein it is 0 that signal is selected in position
Indicate the data of odd column in down-sampled window, it is 1 data for indicating even column in down-sampled window that signal is selected in position；Row selects signal
The data for indicating odd-numbered line in down-sampled window for 0, row selects signal are 1 data for indicating even number line in down-sampled window.
Signal and row selects signal is selected to judge that the image data of input is located at the position in down-sampled window according to position, when position is selected
Signal is 0, when row selects signal is 0, the image data of the first row first row in judging input for down-sampled window.
Step 2), the image data for choosing the first row secondary series in down-sampled window, with the picture number in the first register
According to making comparisons, and chooses image data larger in two image datas and be stored in memory module；Wherein, selecting signal when position is
1, when row selects signal is 0, the data of the first row secondary series in judging input for down-sampled window.
Step 3), the image data for choosing the second row first row in down-sampled window, with the figure of storage in a storage module
As data are made comparisons, and chooses image data larger in two image datas and be stored in the second register；Wherein, when position is selected
Signal is 0, when row selects signal is 1, the data of the second row first row in judging input for down-sampled window.
Step 4), the image data for choosing the second row secondary series in down-sampled window, and are stored in the second register
Image data is made comparisons, and is chosen image data larger in two image datas and be stored in memory module, as final output
As a result.Wherein, it is 1 to select signal when position, when row selects signal is 1, the number of the second row secondary series in judging input for down-sampled window
According to.
As an example, the method for sampling further includes that the memory module is divided into N number of different address location, and it is full
Foot：N=M/4, N are the positive integer more than or equal to 1, wherein M is the number of the image data in piece image, M >=4.
As an example, the image data chosen in the step 4) be stored in the address location of memory module with described
The address location that the image data chosen in step 1) is stored in memory module is identical.
As an example, the image data exported in the step 4) and the address location one in the memory module are a pair of
It answers, described image data are image feature value.
Referring to Fig. 2, in a specific example, the detailed process of the method for sampling includes following：
S1) input image data data namely image feature value；
S2) judge that position selects whether signal is 0, if so, into S3), if it is not, then entering S4)；
S3) judge whether row selects signal is 0, if so, into S5), if it is not, then entering S6)；
S4) judge whether row selects signal is 0, if so, into S7), if it is not, then entering S8)；
S5) image feature value of input is stored in the first register Reg1；
S6) judge the image feature value whether image feature value currently inputted is more than in the first register Reg1, if so,
Then enter S9), if it is not, then entering S10)；
S7) judge the image feature value whether image feature value currently inputted is more than in the first register Reg1, if so,
Then enter S11), if it is not, then entering S12)；
S8) judge the image feature value whether image feature value currently inputted is more than in the second register Reg2, if so,
Then enter S13), if it is not, then entering S14)；
S9) present image characteristic value is stored in memory module FM, into S1)；
S10) image feature value in the first register Reg1 is stored in memory module FM, into S1)；
S11 present image characteristic value) is stored in the second register Reg2, into S1)；
S12) image feature value in the first register Reg1 is stored in the second register Reg2, into S1)；
S13) present image characteristic value is stored in memory module FM in corresponding storage unit；
S14) image feature value in the second register Reg2 is stored in memory module FM in corresponding storage unit；
S15 final image feature value) is exported, and is terminated.
As an example, referring to Fig. 3, being the image feature value schematic diagram of the down-sampled middle input of maximum value, by 16 images
Characteristic value is by the down-sampled window of 2*2 by four samplings, and Fig. 4 exports result schematic diagram after being sampled for four times, it is seen then that every time
Maximum value in sampling output sample, is stored on the corresponding position of output characteristic pattern.It should be noted that the image in Fig. 3 is special
Value indicative randomly selects, and does not limit.
In conclusion the present invention proposes a kind of down-sampled circuit of resource-conserving and down-sampled method, selected using position
Signal and row selects signal and two the first registers and the second register being configured to temporarily store, can solve input image data
The problem of stream all caches.Fairly large input picture is reduced to a quarter of artwork size by the present invention, and output does not change
Become the whole minutia of original image；The dimension that input picture can be reduced, compared to preserving all numbers with intermediate storage
According to the input of stream, the present invention only needs two registers, reduces the consumption of memory；Distribute bright down-sampled method to improve
Calculating speed, can realize on programmable logic device FPGA.So the present invention effectively overcome it is in the prior art various
Disadvantage and have high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology can all carry out modifications and changes to above-described embodiment without violating the spirit and scope of the present invention.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should by the present invention claim be covered.
Claims (13)
1. a kind of down-sampled circuit, which is characterized in that the down-sampled circuit includes：First trigger element, the second trigger element,
Third trigger element, the 4th trigger element, the first register, the second register, first comparator, the second comparator, third ratio
Compared with device and memory module；
First trigger element, second trigger element, the third trigger element and the 4th trigger element difference
Receive image data, signal and row selects signal are selected in position, four images for exporting different ranks in same sampling window respectively
Data；
The input terminal of first register connects the output end of first trigger element, single for depositing first triggering
The output signal of member；
The input terminal of the first comparator is separately connected the output end of first register and second trigger element, uses
In the output signal of first register and second trigger element, and export the greater；
The input terminal of second comparator connects the output end of the memory module and the third trigger element, for comparing
The output signal of the input signal of the first comparator and the third trigger element, and export the greater；
Second register connects the output end of second comparator, and the output for depositing second comparator is believed
Number；
The input terminal of the third comparator is separately connected the output end of second register and the 4th trigger element, uses
In the output signal of second register and the 4th trigger element, and export the greater；
The memory module is connected to the output end of the first comparator and the third comparator, for storing described first
The output signal of comparator, and finally show the output signal of the third comparator.
2. down-sampled circuit according to claim 1, which is characterized in that first trigger element include the first NOT gate,
Second NOT gate, first and door and the first trigger；
First NOT gate receives institute's rheme and selects signal；Second NOT gate receives the row selects signal；Described first with door
Input terminal connects the output end of first NOT gate and second NOT gate；The data input pin of first trigger receives institute
State image data, control terminal connects the output end of described first and door.
3. down-sampled circuit according to claim 1, which is characterized in that second trigger element include third NOT gate,
Second with door and the second trigger；
The third NOT gate receives the row selects signal；Described second connect the output of the third NOT gate with the input terminal of door
End, and receive institute's rheme and select signal；The data input pin of second trigger receives described image data, control terminal connects institute
State the output end of second and door.
4. down-sampled circuit according to claim 1, which is characterized in that the third trigger element include the 4th NOT gate,
Third and door and third trigger；
4th NOT gate receives institute's rheme and selects signal；The input terminal of the third and door connects the output of the 4th NOT gate
End, and receive the row selects signal；The data input pin of the third trigger receives described image data, control terminal connects institute
State the output end of third and door.
5. down-sampled circuit according to claim 1, which is characterized in that the 4th trigger element include the 4th with door and
4th trigger；
Described 4th receives institute's rheme with the input terminal of door selects signal and the row selects signal；The data of 4th trigger are defeated
Enter to hold reception described image data, control terminal to connect the output end of the described 4th and door.
6. the down-sampled circuit according to claim 2~5 any one, which is characterized in that first trigger, described
Second trigger, the third trigger or the 4th trigger are d type flip flop.
7. a kind of down-sampled method using the down-sampled circuit of claim 1-6 any one of them, the size of down-sampled window
For 2*2, which is characterized in that the described method comprises the following steps：
Step 1), input image data, the image data for choosing the first row first row in down-sampled window are stored in the first deposit
In device；
Step 2), the image data for choosing the first row secondary series in down-sampled window, make with the image data in the first register
Compare, and chooses image data larger in two image datas and be stored in memory module；
Step 3), the image data for choosing the second row first row in down-sampled window, with the picture number of storage in a storage module
According to making comparisons, and chooses image data larger in two image datas and be stored in the second register；
Step 4), the image data for choosing the second row secondary series in down-sampled window, with the image being stored in the second register
Data are made comparisons, and are chosen image data larger in two image datas and be stored in memory module, as final output.
8. down-sampled method according to claim 7, which is characterized in that in the step 1), input image data
Also input bit selects signal and row selects signal simultaneously, wherein it is 0 data for indicating odd column in down-sampled window, position that signal is selected in position
It is 1 data for indicating even column in down-sampled window to select signal；Row selects signal is 0 number for indicating odd-numbered line in down-sampled window
According to row selects signal is 1 data for indicating even number line in down-sampled window.
9. down-sampled method according to claim 8, which is characterized in that further include selecting signal and row selects signal to sentence according to position
The image data of disconnected input is located at the position in down-sampled window, and it is 0 to select signal when position, when row selects signal is 0, judges that input is
The image data of the first row first row in down-sampled window；It is 1 to select signal when position, when row selects signal is 0, judges that input is adopted for drop
The data of the first row secondary series in sample window；It is 0 to select signal when position, when row selects signal is 1, judges input in down-sampled window
The data of second row first row；It is 1 to select signal when position, when row selects signal is 1, the second row the in judging input for down-sampled window
The data of two row.
10. down-sampled method according to claim 9, which is characterized in that further include the memory module is divided into it is N number of
Different address locations, and meet：N=M/4, N are the positive integer more than or equal to 1, wherein M is the picture number in piece image
According to number, M >=4.
11. down-sampled method according to claim 10, which is characterized in that the image data chosen in the step 4)
The address location for being stored in memory module is stored in the address list of memory module with the image data chosen in the step 1)
Member is identical.
12. down-sampled method according to claim 11, which is characterized in that the image data exported in the step 4) with
Address location in the memory module corresponds.
13. according to the down-sampled method of claim 7-12 any one of them, which is characterized in that described image data are that image is special
Value indicative.
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