CN1297899C - Digital images matching chip - Google Patents
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- CN1297899C CN1297899C CN 03134554 CN03134554A CN1297899C CN 1297899 C CN1297899 C CN 1297899C CN 03134554 CN03134554 CN 03134554 CN 03134554 A CN03134554 A CN 03134554A CN 1297899 C CN1297899 C CN 1297899C
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Abstract
The present invention discloses a structure of a matching circuit for a digital picture. The circuit comprises an address generating module, a main and an auxiliary correlation processing modules, a comparing, positioning and controlling logic generating module, an FIFO, and an interface module of a peripheral control unit, wherein the address generating circuit provides a peripheral storing address and a read-in address for picture elements of a searching area and sends an interruption indicating signal to the peripheral control unit; the main and an auxiliary correlation processing modules simultaneously carry out two-stage caching for template data and store the input image data of the searching area in a shifting mode; an FIFO module stores the intermediate results of matching operation and accumulates the intermediate results; the comparing, positioning and controlling logic generating module compares and judges matching results to determine the position of a best matching point; an interface circuit of the peripheral control unit generates corresponding controlling signals and respectively outputs the controlling signals to each element circuit. The present invention has the advantages of simple structure and high speed of matching and searching calculation and realizes international universal SAD digital full matching and full searching; the present invention can be used for systems of pattern recognition, object detection, fire control, sequential image encoding, navigation and medical image processing and other systems needing accurate positioning on pictures.
Description
Technical field
The present invention relates to basic electronic component technology field, a kind of specifically chip structure that is used for the digital picture coupling.
Background technology
So-called images match is exactly a kind of position of a less image (being commonly referred to template image) in the big image (being commonly referred to field of search image) of another width of cloth that be used for determining.It is widely used in pattern-recognition, target detection, and firepower control, Sequence Image Coding, navigation, Medical Image Processing and other need carry out in the pinpoint system image.
Existing images match generally adopts digital signal processor DSP and adopts digital signal processor and the realization of field programmable gate array DSP+FPGA structure, and the maximum deficiency of this matching operation is that speed is slow, the cost height, and be unfavorable for expansion.External Ting-Pang Lin and Chaur-Heh Hsieh had once proposed a kind of flexible, images match hardware configuration (A Modular and Flexible Achitecture for Real-time Image Template Matching fast, IEEETRANSACTIONS ON CIRCUITS AND SYSTEMS-I:FUNDMENTAL THEORY ANDAPPLICATIONS VOL.41, NO.6, JUNE 1994:457-461).But when this structure is mated in 80 * 80 field of search image for desired 32 * 32 template in the practicality, then need 32 operation processing unit PU, and 32 hardware cells progressively use in earlier stage in computing, so just make and carrying out blank operation, causing the wasting of resources at computing many operation processing unit PU in early stage.Increasing of operation processing unit PU quantity must cause the resource of Operations Analysis PU also must increase in addition, and the complexity of control also increases.Therefore there is complex structure in this hardware configuration, takies the many shortcomings of resource, and can only go to enlarge the scope of the matching template and the field of search by the scale that increases hardware.
People such as domestic Zhang Suinan in 2002 and Huang Shitan are in " a kind of high-performance special IC design towards image matching algorithm ", Beijing Normal University's journal (natural science edition), in February, 2002, in the 38 volume first phase 48-52 articles, a kind of special IC design towards images match has been proposed again, but this design has only been finished the hardware of images match part algorithm and has been realized, and other computing still relies on digital signal processor (DSP) to realize, do not finish the hardware design of entire image matching operation device, the performance of images match device does not obtain substantial raising yet.
The content of invention
The objective of the invention is to overcome the deficiency of above-mentioned prior art, a kind of digital picture simple in structure coupling hardware configuration is provided, i.e. digital picture matching chip is to improve the service efficiency of hardware when improving arithmetic speed.
Realizing the technical scheme of the object of the invention, is with chip development instrument QUARUS II designed image match circuit on programmable gate array (FPGA) family chip at the scene, constitutes the digital picture matching chip.This images match circuit comprises:
One the output of this code translator is connected to the latch clock end of latch by a code translator, two latchs and the external control interface circuit that the bus-type triple gate constitutes, and the output of this bus-type triple gate is connected to the input end of latch;
One provides the order I/O Address by five counter C, D, E, F, G for the field of search video memory of outside, and produces the address production electric circuit that interrupts indicator signal to peripheral control unit, and these counters all are connected with the peripheral control unit data line;
One by trigger, inputted search district image shift register, subtemplate data buffer register subtemplate data operation register, arithmetic element, the parallel unit that adds up form from associated processing circuit, the input of this subtemplate data buffer register is connected with data line with the peripheral control unit address wire, and its output is connected with subtemplate data operation register;
One by trigger, inputted search district image shift register, subtemplate data buffer register, subtemplate data operation register, arithmetic element, the parallel unit that adds up, with add up from correlated results the unit and with first-in first-out storage circuit FIFO in the operation result principal phase pass treatment circuit that the unit forms that adds up, the input of this subtemplate data buffer register is connected with data line with the peripheral control unit address wire, and its output is connected with subtemplate operational data register;
One by input and latch module, comparison judge module, latch relatively location and the steering logic that update module, address latch module, address counting module, clock modular converter and total clock generating module, decoding module form and produce circuit; This input and latch module respectively with judge module relatively, latch updating block and be connected with the clock modular converter, the output of this comparison judge module with latch update module and be connected with the address counting module is two-way, the address latch module with latch that update module is two-way to be connected, the clock modular converter is connected with judge module relatively with the address counting module respectively; Total clock generating module and master slave related process module, first-in first-out storage circuit (FIFO) is connected; Decoding module is connected with peripheral control unit;
Described external control interface circuit with the address of peripheral control unit input and corresponding data export to respectively address production electric circuit, from associated processing circuit, principal phase close treatment circuit, relatively location and steering logic produce circuit and first-in first-out memory (FIFO); Address production electric circuit is connected to outside the sheet by counting generation four tunnel field of search pixel address and look-at-me the data of this external control interface circuit input; From interlock circuit the data of this external control interface circuit input are closed treatment circuit with the outside field of search pixel data of importing through exporting to principal phase after the computing; Principal phase is closed treatment circuit the data of this external control interface circuit input and data and field of search pixel data from associated processing circuit and first-in first-out memory (FIFO) input is carried out computing, and its operation result exported to first-in first-out memory (FIFO) respectively and relatively location and steering logic produce circuit, handle by the data that this is relatively located and steering logic generation circuit closes the treatment circuit input to principal phase, obtain best match position and export to the external control interface circuit again.
Above-mentioned images match device, wherein the PCI circuit mainly is made up of a code translator, a bus-type triple gate and two latchs, two gating signal clk1 of code translator output and clk2 import the latch clock end of two latchs respectively, the output of bus-type triple gate is connected with the input end of latch, all is connected to the peripheral control unit data line.
The various control signal of this PCI circuit output comprises:
Relatively switching signal (clean), matching result are read and are allowed signal (oe), address decoding to allow signal (cecoun), image resolution ratio control signal (selclk), total clock switch (conlk), searching image memory read write control signal (sel_r), all are connected to and relatively locate the input end that produces circuit with steering logic;
The template replacement signal (le) of PCI circuit output and template write useful signal (mce) and output to principal and subordinate's interlock circuit respectively;
The reset signal (fifors) of PCI circuit output and read useful signal (ren) and be connected to first-in first-out storage circuit (FIFO).
Above-mentioned images match device, wherein relatively positioning circuit mainly by input and latch module, comparison judge module, latch update module, address latch module, address counting module, clock modular converter and form, wherein:
The input and latch module is to latching with the represented matching degree value of 18 bits, guaranteeing data stabilization during the compare operation, the output of this module respectively with judge module relatively, latch updating block and the clock modular converter is connected;
Relatively judge module is used for the previous data of getting off that are latched of input and latch module input are compared, and it is latched to allow signal to be input to latch updating block, latch data is upgraded again;
The input of address counting module, output terminal are connected with the address latch module with the clock modular converter respectively, and this module is used to write down the number of the matching degree value that participation relatively judges, to determine the coordinate of the pairing field of search of matching degree value;
The address latch unit with latch that updating block is two-way to be connected, be used for the address count value of address counting module input is latched, note the new littler pairing address of matching degree value and export;
The clock modular converter is continuous input clock (CLK) to be converted to relatively judge and address counting clock (DCLK), and the address counting clock (DCLK) of this module output is input to the address counting module simultaneously and compares judge module.
Above-mentioned images match device, wherein steering logic generation circuit comprises total clock generating module and decoding module composition, total clock generating module produces principal and subordinate's related process module computing clock according to the pixel clock and the external clock control word of input, first-in first-out memory (FIFO) read-write clock, external search district video memory read-write and output allow control signal; Decoding module is the address decoding that peripheral control unit is sent, and produces corresponding address generator and puts initial value permission signal.
Above-mentioned images match device, wherein principal phase close circuit mainly by trigger, field of search image shift register, subtemplate data buffer register, subtemplate data operation register, arithmetic element, the parallel unit that adds up, from add up unit and form of correlated results with the interior operation result of first-in first-out memory (FIFO) unit that adds up; Enter field of search image shift register after trigger reads in view data synchronously and form data window, the output data of field of search image shift register and subtemplate data operation register enters the absolute difference output that arithmetic element obtains field of search image and template image jointly, the gray scale difference that this output valve obtains search graph and subtemplate figure through the parallel unit that the adds up back of adding up walks abreast with the operation result of coming from interlock circuit and adds up, and this parallel accumulation result walks abreast to add up with the preceding result who falls generation several times who reads from first-in first-out memory (FIFO) again and obtains this and fall for the result and export.
Above-mentioned images match device, wherein from interlock circuit mainly by trigger, field of search image shift register, the subtemplate data buffer register, subtemplate data operation register, arithmetic element, the parallel unit that adds up is formed, enter field of search shift map after trigger reads in view data synchronously and form data window as register, the output data of field of search image shift register and subtemplate data operation register enters the absolute difference output that arithmetic element obtains field of search image and template image jointly, and this output valve obtains the gray scale difference of search graph and subtemplate figure through parallel the adding up of two-way operation result.
Above-mentioned images match device, address production electric circuit wherein is made up of five counters, four counters are used to outside field of search video memory that the order I/O Address is provided, another counter is used for the process of statistical dependence computing, when a sub-template matches finishes, send a high level and interrupt indicator signal, five counter shared address generator clock signals (addresclk) and peripheral control unit data line.
Above-mentioned images match device, wherein pushup storage (FIFO) directly adopts the module in parametrization million function modules grounds (LPMs) that chip development instrument QUARUS II provides to realize.
The present invention is owing to be development platform with FPGA (Field Programmable Gate Array) (FPGA), adopt high-efficiency stream line structure and large-scale parallel processing technique, the utilization factor of its functional unit is 100%, single processing module is under the condition of 20M clock, can finish coupling and the search arithmetic of template image in 80 * 80 pixel coverages of 32 * 32 pixel sizes in the 2ms, template and hunting zone are variable, and provide the Matching Location result who is not less than the pixel level precision in real time.This hardware configuration has been realized international absolute difference and the full search of the full coupling of tolerance (SAD) numeral, can be applicable to infrared/video frequency object tracking device, finishes object matching in real time and follow the tracks of computing in 20ms.If adopt application-specific IC (ASIC) technology, performance index also can improve a lot, and system architecture will be more compact, and can satisfy moving image encoding, improve motion estimation and compensation and otherwise needs, more help the large-scale application of military affairs and industrial circle.
Description of drawings:
Fig. 1 is an integrated circuit structured flowchart of the present invention
Fig. 2 is that principal phase of the present invention is closed the treatment circuit structured flowchart
Fig. 3 is of the present invention from the associated processing circuit structured flowchart
Fig. 4 is a relatively positioning circuit structured flowchart of the present invention
Fig. 5 is that steering logic of the present invention produces the circuit structure block diagram
Fig. 6 is an address production electric circuit graph structure block diagram of the present invention
Fig. 7 is an external control interface circuit structure block diagram of the present invention
Fig. 8 is the outside block diagram that connects of the present invention
Embodiment:
Below the structure that present invention will be described in detail with reference to the accompanying.
With reference to Fig. 1, hardware configuration of the present invention is a design circuit on the scale programmable logic device EP20K300EBC652-3 of ALTERA company, constitutes with being connected by specific modules collocation.This circuit comprises address production electric circuit, and principal phase is closed treatment circuit, and from associated processing circuit, relatively location and steering logic produce circuit, first-in first-out memory (FIFO) and PCI circuit.Wherein:
Address production electric circuit provides the exterior storage address and reads in the address for field of search pixel, and produces the interruption indicator signal to peripheral control unit.Principal phase is closed treatment circuit and from interlock circuit three functions is arranged, and the one, the parallel pipeline processes of finishing every little template; The 2nd, every little template data is carried out two-level cache, realize the parallel work-flow of each subtemplate; The 3rd, the field of search view data of input is carried out shift LD, with simulated templates image moving in the field of search.First-in first-out memory (FIFO) is used for storing the intermediate result of matching operation, and this result read out when calculating next piece subtemplate adds up; Relatively location and control logic module are finished three functions, and the one, matching result is compared judgement to determine the optimal match point position; The 2nd, the read-write that the clock signal that producing has the strict sequential order relation is come read-write, streamline and the first-in first-out memory (FIFO) of synchronous external search district image memory bank; The 3rd, the resolution of image and the size of image template are controlled.The PCI circuit mainly is to produce control signal corresponding according to the controller address of outside input and data, this control signal comprises the comparison switching signal, matching result is read the permission signal, address decoding allows signal, image resolution ratio control signal, total clock switch, searching image memory read write control signal, the template replacement signal of PCI circuit output, template writes useful signal, the reset signal of PCI circuit output and read useful signal.
The annexation and the course of work of each modular circuit are as follows:
Principal phase is closed treatment circuit and is connected with four tunnel field of search pixel digital signals from associated processing circuit, and promptly two-way field of search pixel numeral is input to principal phase and closes treatment circuit, and two-way field of search pixel numeral is input to from the processing module circuit in addition.
The peripheral control unit address wire is connected with the input end of peripheral control unit data line with the PCI circuit, simultaneously, the peripheral control unit address wire is also with master and slave associated processing circuit, relatively location and steering logic produce circuit and be connected, and the peripheral control unit data line also is connected with master and slave associated processing circuit, address production electric circuit.The various control signals of PCI circuit output are the address and the corresponding data of peripheral control unit input, are connected respectively to principal and subordinate's associated processing circuit, address production electric circuit, and relatively location and steering logic produce circuit, pushup storage (FIFO).Input to principal phase pass treatment circuit from the operation result of associated processing circuit output, the intermediate results of operations that principal phase is closed treatment circuit output inputs to pushup storage (FIFO), and the output of pushup storage (FIFO) is connected with the input that principal phase is closed treatment circuit.The operation result that principal phase is closed treatment circuit output also produces circuit with relatively location and steering logic and is connected.Relatively the output of location and steering logic generation circuit is connected with the external control interface circuit.
With reference to Fig. 2, principal phase of the present invention is closed circuit mainly by trigger, inputted search district image shift register, the subtemplate data buffer register, subtemplate data operation register, arithmetic element, the parallel unit that adds up, with add up from correlated results the unit and with first-in first-out storage circuit FIFO in the operation result unit that adds up form.The view data of coming out from field of search video memory enters the data window of shift register formation 2 * 32 after trigger reads in synchronously.The subtemplate data write the subtemplate data buffer register by peripheral control unit address wire and data line simultaneously, and before an interative computation begins the template data in the subtemplate data buffer register are inserted the subtemplate arithmetic register.The output data of field of search pixel shift register and subtemplate arithmetic register enters the absolute value that arithmetic element obtains the difference of field of search image and template image jointly.This value obtains the gray scale difference of this 2 * 32 search graph and subtemplate figure through the parallel unit that adds up, after adding up with the operation result that comes from correlation module after this difference adds up, the preceding result of iteration several times who reads from first-in first-out storage circuit FIFO obtains this iteration result again.
With reference to Fig. 3, texture ratio principal phase from associated processing circuit of the present invention is closed the last less two-stage totalizer of treatment circuit, promptly by trigger, inputted search district image shift register, subtemplate data buffer register, subtemplate data operation register, arithmetic element, the parallel unit that adds up is formed, and each unit connection relation is identical with principal phase pass treatment circuit, and the operation result of exporting from associated processing circuit inputs to principal phase pass treatment circuit.
With reference to Fig. 2, principal phase of the present invention is closed circuit mainly by trigger, inputted search district image shift register, the subtemplate data buffer register, subtemplate data operation register, arithmetic element, the parallel unit that adds up, with add up from correlated results the unit and with first-in first-out storage circuit FIFO in the operation result unit that adds up form.The view data of coming out from field of search video memory enters the data window of shift register formation 2 * 32 after trigger reads in synchronously.The subtemplate data write the subtemplate data buffer register by peripheral control unit address wire and data line simultaneously, and before an interative computation begins the template data in the subtemplate data buffer register are inserted the subtemplate arithmetic register.The output data of field of search pixel shift register and subtemplate arithmetic register enters the absolute value that arithmetic element obtains the difference of field of search image and template image jointly.This value obtains the gray scale difference of this 2 * 32 search graph and subtemplate figure through the parallel unit that adds up, after adding up with the operation result of coming from correlation module after this difference adds up, the result of the preceding iteration several times of reading from first-in first-out storage circuit FIFO obtains this iteration result again.
With reference to Fig. 3, texture ratio principal phase from associated processing circuit of the present invention is closed the last less two-stage totalizer of treatment circuit, promptly by trigger, inputted search district image shift register, subtemplate data buffer register, subtemplate data operation register, arithmetic element, the parallel unit that adds up is formed, and each unit connection relation is identical with principal phase pass treatment circuit, and the operation result of exporting from associated processing circuit inputs to principal phase pass treatment circuit.
With reference to Fig. 4, relatively positioning circuit of the present invention mainly by input and latch module, comparison judge module, latch update module, address latch module, address counting module, clock modular converter and form, wherein:
The input and latch module is to latching with the represented matching degree value of 18 bits, guaranteeing data stabilization during the compare operation, the output of this module respectively with judge module relatively, latch updating block and the clock modular converter is connected;
Relatively the output of judge module with latch update module and be connected with the address counting module is two-way, this module compares input data and the previous matching degree magnitude data of getting off that is latched, if the input data are littler than being latched the data of getting off, it will provide one and latch the permission signal, latch after updating block receives this signal, latch data is upgraded, new data latching is got off use for relatively judge next time; If the input data are bigger than being latched the data of getting off, latch updating block and continue to keep former latch data, these data continue to participate in comparing next time;
The input of address counting module, output terminal are connected with the address latch module with the clock modular converter respectively, this module is responsible for writing down the number of the matching degree value that participation relatively judges, can determine the coordinate of the pairing field of search of matching degree value by this numerical value;
After the address latch unit is received and is latched the permission signal, address count value to this moment latchs, note the new littler pairing address of matching degree value, when all matching degree values all through after relatively judging, what remained in the address latch is exactly the position of smallest match metric in whole matching degree value sequence.
The clock modular converter is continuous input clock (CLK) to be converted to relatively judge and address counting clock (DCLK).When relatively switching signal (clean) was high, comparison module was started working; Read when matching result and to allow signal (oe) when high, the address of reading optimal match point.
With reference to Fig. 5, steering logic produces part and is made up of total clock generating module and decoding module.Total clock generating module produces principal and subordinate's related process module computing clock according to the pixel clock and the external clock control word of input, and first-in first-out memory FIFO reads and writes clock, and external search district video memory read-write and output allow control signal; Decoding module is the address decoding that peripheral control unit is sent, and produces corresponding address generating module and inserts initial value and put the permission signal.When address decoding allows signal (Cecoun) low, to the address decoding of peripheral control unit input, produce address generator insert initial value allow signal (decode0, decode1, decode2, decode3 decode4) is connected to address generating module.
Total clock generating module is made up of clock selection module, clock generating module, field of search video memory control signal generating module.
Clock selection module mainly is to use pixel clock (clk100) when storing at field of search image, and uses 20M external clock (clk50) during computing and design.Realize selection by data selector, when searching image memory read write control signal (sel_r) is selected outside 20M clock when high, select pixel clock when low two kinds of clocks.Owing to when computing, also need to use 2 frequency-dividing clocks of this two clock, a data selector switch and one 2 frequency divider have been used again respectively at pixel clock and external clock part.When image resolution ratio control signal (selclk) when being high, select pixel clock, address counting clock and the pixel of generation are synchronous, realize the pointwise of pixel is stored; When low, 2 sub-frequency clock signals of selecting pixel clock are realized the dot interlace access to pixel as the address counting clock.The logical combination of gate signal field and pixel clock part can be realized the control to inputted search district image range, as gate signal field when being high, opens the pixel clock input, when low, closes the pixel clock input.Why the external clock importation is provided with 2 frequency dividers mainly is because when carrying out matching operation, and the first seven time iteration is used the 20M clock, and uses the 10M clock owing to will compare computing for the last time.When relatively switching signal Clean was low, the 20M clock was directly exported; As Clean when being high, the 20M clock is exported with the 10M clock behind 2 frequency divisions.
Field of search video memory control signal generating module mainly is to realize searching image memory read write control signal (sel_r), pixel clock (clk100), the clock signal of address generator (addresclk), gate signal (field), total clock switch (conclk), fifo writes clock (fifowclk), fifo reads clock (fiforclk) output to field of search image is allowed jointly controlling of signal (dpsramoe) and external search district video memory read-write (dpsramrw).The output of field of search image allows signal (dpsramoe) to be high level when external search district video memory writes data, external search district video memory read-write (dpsramrw) high-low level substitutes, when its low level with the pixel data write store.When sense data, the output of field of search image allows signal (dpsramoe) to be low level, and external search district video memory read-write (dpsramrw) is high level, relies on the address that changes that pixel data is read.
The clock generating module mainly is to open fifo when being implemented in total clock switch signal (conclk) for high level to read clock (addresclk), the matching operation clock (Corclk) that clock (fiforclk), fifo are write clock (fifowclk), address generator.When being high, group template matches computing end interrupt indicator signal (int) closes above each time clock feature.This module realizes that also address generator clock (addresclk), matching operation clock Corclk hysteresis fifo read clock period of clock (fiforclk), leading fifo writes clock period of clock (fifowclk), strict corresponding relationship between the corresponding data during with the realization interative computation.Matching operation clock (Corclk) is connected to principal and subordinate's correlator.The clock signal of address generator (addresclk) is connected to address generating module.
With reference to Fig. 6, address production electric circuit module of the present invention is made up of five counter C, D, E, F, G, and counter C, D, E, F provide the order I/O Address for the field of search video memory of outside.The process of counter G statistical dependence computing is sent a high level and is interrupted indicator signal when a sub-template matches finishes.Five counter shared address generator clock signals (addresclk) and peripheral control unit data line.The course of work of this address module is:
Peripheral control unit address and data corresponding different before computing begins produce the corresponding counter value of putting permission signal, and the address initial value on the data line is write counter; The clock signal (addresclk) that begins the back address generator in computing is come, counter C, D, E, F satisfy the sequence address that produces corresponding to different addresses initial value, make writing fashionable field of search image and can and be advanced into field of search video memory in identical address, and the four lines field of search pixel data of address initial value that can be corresponding different when reading and be advanced into the digital picture adaptation.The principle of work of counter G is with above-mentioned four-counter, and the output of the most significant digit data of counter is as output.
The address and the look-at-me of four field of search pixels of address production electric circuit device output are connected to outside the sheet.
With reference to Fig. 7, peripheral control unit module interface circuit of the present invention is made up of a code translator and data latches.This interface circuit is used to finish two kinds of functions, and one provides two-way inputoutput data interface, to save resource; The 2nd, lock the control corresponding word according to corresponding address.
The realization of bi-directional data inputoutput data interface is to be realized by the triple gate of one group of bus-type, the data of input directly are connected to each module, and export through triple gate the address of the optimal match point of output, and the control of three everys has the read-write of peripheral control unit input to realize.
Control word produces part and is made up of code translator and two latchs.
Peripheral control unit data strobe signal (iocs) is connected to the Enable Pin (G2AN) of code translator; Peripheral control unit address wire ca[10] be connected to another Enable Pin of code translator;
Peripheral control unit address wire ca[7], ca[8], ca[9] be connected to three input ends of code translator respectively;
Peripheral control unit address wire ca[7], ca[8], ca[9], ca[10] Different Logic combination can produce corresponding matching result and read and allow signal (oe), conce address decoding to allow signal (cecoun), template to write useful signal (mce) and two latches clock signal clk1 and clk2;
Two latches clock signal clk1 and clk2 are connected to the latch clock signal clk end of latch respectively, at the rising edge of different latch signal clk, lock different control words, produce corresponding signal;
Comparison switching signal (clean), the matching result of PCI circuit output read and allowed signal (oe), address decoding to allow signal (cecoun), image resolution ratio control signal (selclk), total clock switch (conlk), searching image memory read write control signal (sel_r), all is connected to and relatively locatees the input end that produces circuit with steering logic.
Pushup storage (FIFO) is read useful signal (ren), reset signal (fifors) is connected to pushup storage (FIFO);
Template replacement signal (le), template write useful signal (mce) and are connected to principal and subordinate's interlock circuit device; Searching image memory read write control signal (sel_r) also exports to outside the sheet simultaneously.
With reference to Fig. 8, use to be aided with external storage and controller when of the present invention.Two dual-port static storeies are field of search video memory, all have the view data of the whole field of search in each sheet.74245 mainly is when matching operation is carried out, in order to reading of isolating exterior video data and field of search storer interior pixel data.Controller is mainly finished the write operation control (range size, field of search image that main contents comprise the resolution of determining field of search image, field of search image in storer deposit reference position) of dual-ported memory, the initialization (mainly comprise address counter and interrupt counter zero clearing, each subtemplate register zero clearing, each level production line zero clearing, the zero clearing of matched position register, push-up storage are resetted) of each unit hardware of adaptation; The content of controller also comprises the initial value that each address counter and interrupt counter are set, and determines the duty of push-up storage, determines that whether matching unit is opened, and determines the frequency of computing clock.Will participate in the subtemplate of computing and pour arithmetic register into, determine the time that subtemplate is carried out computing from the buffering register.After interrupting coming, all clocks of closing the matching operation unit to guarantee the strict synchronism between the clock that each device adopted, correctly are provided with the initial value of interrupt counter.
Be provided with four groups 8 field of search image input interfaces in the adaptation external terminal, four group searching district pixel corresponding address interfaces, the read-write interface of field of search video memory, the output of field of search image allows signaling interface, the read-write control output interface of field of search video memory, the related operation interruption indicator signal that finishes, the external clock input interface, the pixel clock input interface, peripheral control unit reading and writing data signal input interface, the external control address interface, peripheral control unit data-interface gating signal and field of search image range ripple door indicator signal.
Claims (9)
1. digital picture adaptation comprises:
An intermediate result that is used to store matching operation, and this result read out the first-in first-out memory (FIFO) that adds up when calculating next piece subtemplate;
One the output of this code translator is connected to the latch clock end of latch by a code translator, two latchs and the external control interface circuit that the bus-type triple gate constitutes, and the output of this bus-type triple gate is connected to the input end of latch;
One provides the order I/O Address by five counters (C, D, E, F, G) for the field of search video memory of outside, and produces the address production electric circuit that interrupts indicator signal to peripheral control unit, and these counters all are connected with the peripheral control unit data line;
One by trigger, inputted search district image shift register, subtemplate data buffer register subtemplate data operation register, arithmetic element, the parallel unit that adds up form from associated processing circuit, the input of this subtemplate data buffer register is connected with data line with the peripheral control unit address wire, and its output is connected with subtemplate data operation register;
One by trigger, inputted search district image shift register, subtemplate data buffer register, subtemplate data operation register, arithmetic element, the parallel unit that adds up, with add up from correlated results the unit and with interior the operation result of first-in first-out storage circuit (FIFO) the principal phase pass treatment circuit that the unit forms that adds up, the input of this subtemplate data buffer register is connected with data line with the peripheral control unit address wire, and its output is connected with subtemplate operational data register;
One by input and latch module, comparison judge module, latch relatively location and the steering logic that update module, address latch module, address counting module, clock modular converter and total clock generating module, decoding module form and produce circuit; This input and latch module respectively with judge module relatively, latch updating block and be connected with the clock modular converter, the output of this comparison judge module with latch update module and be connected with the address counting module is two-way, the address latch module with latch that update module is two-way to be connected, the clock modular converter is connected with judge module relatively with the address counting module respectively; Total clock generating module and master slave related process module, first-in first-out storage circuit (FIFO) connection; Decoding module is connected with peripheral control unit;
Described external control interface circuit with the address of peripheral control unit input and corresponding data export to respectively address production electric circuit, from associated processing circuit, principal phase close treatment circuit, relatively location and steering logic produce circuit and first-in first-out memory (FIFO); This address production electric circuit is connected to outside the sheet by counting generation four tunnel field of search pixel address and look-at-me the data of this external control interface circuit input; From interlock circuit the data of this external control interface circuit input are closed treatment circuit with the outside field of search pixel data of importing through exporting to principal phase after the computing; This principal phase is closed treatment circuit the data of this external control interface circuit input and data and field of search pixel data from associated processing circuit and first-in first-out memory (FIFO) input is carried out computing, and its operation result exported to first-in first-out memory (FIFO) respectively and relatively location and steering logic produce circuit, handle by the data that this is relatively located and steering logic generation circuit closes the treatment circuit input to principal phase, obtain best match position and export to the external control interface circuit again.
2. images match device according to claim 1, it is characterized in that the external control interface circuit mainly is made up of a code translator, a bus-type triple gate and two latchs, the latch clock end that first gating signal (clk1) of code translator output and second gating signal (clk2) are input to two latchs respectively, the output of bus-type triple gate is connected with the input end of latch, all is connected to the peripheral control unit data line.
3. images match device according to claim 1 and 2 is characterized in that the various control signal of external control interface circuit output comprises:
Relatively switching signal (clean), matching result are read and are allowed signal (oe), address decoding to allow signal (cecoun), image resolution ratio control signal (selclk), total clock switch (conlk), searching image memory read write control signal (sel_r), all are connected to and relatively locate the input end that produces circuit with steering logic;
The template replacement signal (le) of PCI circuit output and template write useful signal (mce) and output to master and slave associated processing circuit respectively;
The reset signal (fifors) of PCI circuit output and read useful signal (ren) and be connected to first-in first-out storage circuit (FIFO).
4. images match device according to claim 1, it is characterized in that the comparison positioning circuit mainly by input and latch module, comparison judge module, latch updating block, clock modular converter, address counting module and address latch unit and form, wherein:
The input and latch module adopts the represented matching degree value of 18 bits to latch, and the output of this module is input to the comparison judge module simultaneously, latchs updating block and clock modular converter;
Relatively the output of judge module with latch update module and be connected with the address counting module is two-way, this module compares input data and the previous matching degree magnitude data of getting off that is latched, and latchs optimum matching metric and best match position according to comparative result;
The address counting module is used to write down the number of the matching degree value that participation relatively judges, and number is input to the address latch unit;
The address latch unit with latch that updating block is two-way to be connected, be used for the address count value of address counting module input is latched, note the new littler pairing address of matching degree value and export;
The clock modular converter is used for continuous input clock (CLK) is converted to relatively judgement and address counting clock (DCLK), and the address counting clock (DCLK) of this module output is input to the address counting module simultaneously and compares judge module.
5. images match device according to claim 1, it is characterized in that steering logic produces circuit and is made up of total clock generating module and decoding module, total clock generating module produces master slave related process module computing clock according to the pixel clock and the external clock control figure of input, first-in first-out storage circuit (FIFO) read-write clock, external search district video memory read-write and output allow control signal; Decoding module is the address decoding that peripheral control unit is sent, and produces the corresponding address generating module that produces and puts initial value permission signal.
6. images match device according to claim 1, it is characterized in that principal phase close circuit mainly by trigger, field of search image shift register, subtemplate data buffer register, subtemplate data operation register, arithmetic element, the parallel unit that adds up, from add up unit and form of correlated results with the interior operation result of first-in first-out memory (FIFO) unit that adds up, the input of subtemplate data buffer register is connected with data line with the peripheral control unit address wire, and its output is connected with subtemplate operational data register; Enter field of search image shift register after trigger reads in view data synchronously and form data window, the output data of field of search image shift register and subtemplate operational data register enters the absolute difference output that arithmetic element obtains field of search image and template image jointly, add up with the operation result of coming from interlock circuit is parallel after the gray scale difference that this output valve obtains search graph and subtemplate figure through the parallel unit that adds up adds up, this parallel accumulation result obtains this iteration result output with parallel the adding up of the result of the preceding iteration several times of reading from first-in first-out memory (FIFO) again.
7. images match device according to claim 1, it is characterized in that from interlock circuit mainly by trigger, field of search image shift register, the subtemplate data buffer register, subtemplate data operation register, arithmetic element, the parallel unit that adds up is formed, the input of subtemplate data buffer register is connected with data line with the peripheral control unit address wire, its output is connected with subtemplate data operation register, enter field of search image shift register after trigger reads in view data synchronously and form data window, the output data of field of search image shift register and subtemplate data operation register enters the absolute difference output that arithmetic element obtains field of search image and template image jointly, and this output valve obtains the gray scale difference of search graph and subtemplate figure through parallel the adding up of two-way operation result.
8. images match device according to claim 1, it is characterized in that address production electric circuit is by first counter (C), second counter (D), the 3rd counter (E), four-counter (F), the 5th counter (G) is formed, first counter, second counter, the 3rd counter, four-counter provides the order I/O Address for the field of search video memory of outside, the process of the 5th counters count related operation, when a sub-template matches finishes, send a high level and interrupt indicator signal, these counter shared address generator clock signal (addresclk) and peripheral control unit data lines.
9. images match device according to claim 1 is characterized in that the interior module of parametrization million function modules grounds (LPMs) that pushup storage (FIFO) directly adopts chip development instrument QUARUS II to provide realizes.
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| CN 03134554 CN1297899C (en) | 2003-09-08 | 2003-09-08 | Digital images matching chip |
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| CN 03134554 CN1297899C (en) | 2003-09-08 | 2003-09-08 | Digital images matching chip |
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| CN102682282B (en) * | 2012-04-05 | 2014-03-26 | 北京航空航天大学 | Online model identification instrument based on DaVinci framework and embedded type image detection technology |
| CN102802038A (en) * | 2012-07-25 | 2012-11-28 | 华中科技大学 | Binary image template matching system based on parallel bit stream processor |
| CN103839219B (en) * | 2012-11-26 | 2017-04-26 | 中国航天科工集团第三研究院第八三五七研究所 | High performance parallel multiplying-adding circuit applied to 8-bit grayscale image matching |
| CN104835116B (en) * | 2015-04-10 | 2018-11-20 | 山东师范大学 | A kind of two-dimentional fragments mosaicing method based on profile |
| US10599566B2 (en) * | 2016-11-29 | 2020-03-24 | Qualcomm Incorporated | Multi-mode cache invalidation |
| US11349782B2 (en) * | 2018-01-15 | 2022-05-31 | Shenzhen Corerain Technologies Co., Ltd. | Stream processing interface structure, electronic device and electronic apparatus |
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