CN108616675B - Down-sampling circuit and down-sampling method - Google Patents
Down-sampling circuit and down-sampling method Download PDFInfo
- Publication number
- CN108616675B CN108616675B CN201810312197.0A CN201810312197A CN108616675B CN 108616675 B CN108616675 B CN 108616675B CN 201810312197 A CN201810312197 A CN 201810312197A CN 108616675 B CN108616675 B CN 108616675B
- Authority
- CN
- China
- Prior art keywords
- image data
- gate
- selection signal
- output
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0102—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving the resampling of the incoming video signal
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Image Processing (AREA)
Abstract
The invention provides a resource-saving down-sampling circuit and a down-sampling method, which can solve the problem of full caching of an input image data stream by utilizing a bit selection signal, a row selection signal, a first register and a second register for temporary storage. The invention reduces the large-scale input image to one fourth of the original image size, and the output does not change the overall detail characteristics of the original image; the dimensionality of an input image can be reduced, and compared with the method of storing the input of all data streams by using intermediate storage, the method only needs two registers, so that the consumption of a memory is reduced; the down-sampling method improves the calculation speed and can be realized on a programmable logic device FPGA. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
Description
Technical Field
The invention relates to the technical field of image data sampling circuits, in particular to a down-sampling circuit and a down-sampling method.
Background
With the improvement of shooting technology, people have higher and higher requirements on high-resolution images, and simultaneously along with the development of artificial intelligence, an algorithm of image recognition is also vigorously developed. Reducing the size of the intermediate layer calculation results is a very important operation when performing a series of calculations in an algorithm on high resolution images, especially in convolutional neural networks which today have a good effect in the field of object recognition.
In convolutional neural networks, pooling is often encountered, and a pooling layer often follows the convolutional layer to reduce the eigenvectors output by the convolutional layer by pooling, while improving the overfitting phenomenon. Images have a "static" property, which means that features useful in one image area are most likely to be equally useful in another area. Therefore, in order to describe a large image, a natural idea is to aggregate statistics of features at different positions, for example, one can calculate an average (or maximum) value of a specific feature on a region of the image to represent the feature of the region.
The pooling operation has two significant advantages: 1) after the features of the image are obtained by convolution operation, the computational challenge is faced if the features are directly used for classification. And the pooling results may result in reduced features and reduced parameters; 2) pooling can preserve rotational, translational, and telescopic invariance of the image.
There are three general ways of pooling: 1) pooling the average values, namely, only averaging the feature points in the neighborhood, and better retaining the background; 2) the maximum value pooling means that the feature point in the neighborhood is maximized, and the texture extraction is better; 3) and pooling random values, namely assigning probability to the pixel points according to the numerical value and then performing sub-sampling according to the probability. The error of feature extraction mainly comes from two aspects: 1) the variance of the estimated value is increased due to the limited size of the neighborhood; 2) convolutional layer parameter errors cause a shift in the estimated mean. In general, mean pooling can reduce the first error, more preserving background information of the image, and maximum pooling can reduce the second error, more preserving texture information. In the average sense, similar to the average pooling, in the local sense, the criterion of maximum pooling is followed.
With the increase of image scale and the continuous increase of calculation amount, a common CPU can not finish the large-scale operation within a tolerable time range, so that the calculation is accelerated by utilizing hardware platforms such as a GPU, an FPGA and the like.
The down-sampling process is quite simple and easy to understand in algorithm, but in the implementation process of a hardware circuit, because data is input into the module in a data stream mode, if a temporary storage structure is designed to be stored in the middle, the data can be read out and down-sampled according to addresses after the storage is finished, but the method wastes storage resources too much.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a down-sampling circuit and a down-sampling method, which are used to solve the problems of the prior art that the sampling circuit wastes memory space, the amount of computation is increased due to the oversize sampled image, and it is difficult to restore the overall details of the image.
In order to achieve the purpose, the invention adopts the following scheme: a down-sampling circuit, the down-sampling circuit comprising: the trigger comprises a first trigger unit, a second trigger unit, a third trigger unit, a fourth trigger unit, a first register, a second register, a first comparator, a second comparator, a third comparator and a storage module; the first trigger unit, the second trigger unit, the third trigger unit and the fourth trigger unit respectively receive image data, a bit selection signal and a row selection signal and are used for respectively outputting four image data of different rows and columns in the same sampling window; the input end of the first register is connected with the output end of the first trigger unit and is used for registering the output signal of the first trigger unit; the input end of the first comparator is respectively connected with the output ends of the first register and the second trigger unit, and is used for comparing the output signals of the first register and the second trigger unit and outputting the larger output signal; the input end of the second comparator is connected with the storage module and the output end of the third trigger unit, and is used for comparing the output signal of the first comparator with the output signal of the third trigger unit and outputting the larger of the output signals; the second register is connected with the output end of the second comparator and used for registering the output signal of the second comparator; the input end of the third comparator is respectively connected with the output ends of the second register and the fourth trigger unit, and is used for comparing the output signals of the second register and the fourth trigger unit and outputting the larger output signal; the storage module is connected to the output ends of the first comparator and the third comparator, and is used for storing the output signal of the first comparator and finally storing the output signal of the third comparator.
In an embodiment of the present invention, the first trigger unit includes a first not gate, a second not gate, a first and gate, and a first trigger; the first NOT gate receives the bit selection signal; the second NOT gate receives the row selection signal; the input end of the first AND gate is connected with the output ends of the first NOT gate and the second NOT gate; the data input end of the first trigger receives the image data, and the control end of the first trigger is connected with the output end of the first AND gate.
In an embodiment of the present invention, the second triggering unit includes a third not gate, a second and gate, and a second trigger; the third NOT gate receives the row selection signal; the input end of the second AND gate is connected with the output end of the third NOT gate and receives the bit selection signal; and the data input end of the second trigger receives the image data, and the control end of the second trigger is connected with the output end of the second AND gate.
In an embodiment of the present invention, the third triggering unit includes a fourth not gate, a third and gate, and a third trigger; the fourth not gate receives the bit select signal; the input end of the third AND gate is connected with the output end of the fourth NOT gate and receives the row selection signal; and the data input end of the third trigger receives the image data, and the control end of the third trigger is connected with the output end of the third AND gate.
In an embodiment of the present invention, the fourth triggering unit includes a fourth and gate and a fourth trigger; the input end of the fourth AND gate receives the bit selection signal and the row selection signal; and the data input end of the fourth trigger receives the image data, and the control end of the fourth trigger is connected with the output end of the fourth AND gate.
In an embodiment of the present invention, the first flip-flop, the second flip-flop, the third flip-flop or the fourth flip-flop is a D flip-flop.
The invention also provides a down-sampling method, the size of a down-sampling window is 2 x 2, and the method comprises the following steps: step 1), inputting image data, selecting image data of a first row and a first column in a down-sampling window, and storing the image data in a first register; step 2), selecting image data of a first row and a second column in a down-sampling window, comparing the image data with image data in a first register, and selecting larger image data of the two image data to be stored in a storage module; step 3), selecting image data of a second row and a first column in the down-sampling window, comparing the image data with image data stored in the storage module, and selecting the larger image data of the two image data to store in a second register; and 4) selecting the image data of the second row and the second column in the down-sampling window, comparing the image data with the image data stored in the second register, and selecting the larger image data of the two image data to be stored in the storage module as a final output result.
In an embodiment of the present invention, in the step 1), a bit selection signal and a row selection signal are input while inputting the image data, wherein the bit selection signal is 0 to indicate data in odd columns in the down-sampling window, and the bit selection signal is 1 to indicate data in even columns in the down-sampling window; the row select signal is 0 to indicate data of odd rows in the down-sampling window, and the row select signal is 1 to indicate data of even rows in the down-sampling window.
In an embodiment of the present invention, the down-sampling method further includes determining a position of the input image data in the down-sampling window according to the bit selection signal and the row selection signal, and determining the input image data as the image data in the first row and the first column in the down-sampling window when the bit selection signal is 0 and the row selection signal is 0; when the bit selection signal is 1 and the row selection signal is 0, judging that the input is data of a first row and a second column in a down sampling window; when the bit selection signal is 0 and the row selection signal is 1, judging that the input is data of a second row and a first column in the down sampling window; and when the bit selection signal is 1 and the row selection signal is 1, judging that the input is data of a second row and a second column in the down sampling window.
In an embodiment of the present invention, the down-sampling method further includes dividing the memory module into N different address units, and satisfying: and N is a positive integer which is greater than or equal to 1, wherein M is the number of image data in one image, and M is greater than or equal to 4.
In an embodiment of the invention, the address unit of the image data selected in the step 4) stored in the storage module is the same as the address unit of the image data selected in the step 1) stored in the storage module.
In an embodiment of the present invention, the image data output in the step 4) corresponds to address units in the storage module one to one.
In an embodiment of the present invention, the image data is an image feature value.
As described above, the down-sampling circuit and the down-sampling method of the present invention have the following advantageous effects:
1) reducing the input image with a larger scale to one fourth of the size of the original image, and outputting the input image without changing the overall detail characteristics of the original image;
2) the dimensionality of an input image can be reduced, and compared with the method of storing the input of all data streams by using intermediate storage, the method only needs two registers, so that the consumption of a memory is reduced;
3) the down-sampling method improves the calculation speed and can be realized on a programmable logic device FPGA.
Drawings
Fig. 1 is a circuit diagram of a down-sampling circuit according to a first embodiment of the present invention.
Fig. 2 is a flowchart of a down-sampling method according to a second embodiment of the present invention.
Fig. 3 is a schematic diagram of image feature values input in down-sampling.
Fig. 4 is a schematic diagram of an output result after down-sampling.
Description of the element reference numerals
1 first trigger unit
11 first not gate
12 second not gate
13 first and gate
14 first flip-flop
2 second trigger unit
21 third not gate
22 second and gate
23 second flip-flop
3 third trigger Unit
31 fourth not gate
32 third and gate
33 third flip-flop
4 fourth trigger unit
41 fourth and gate
42 fourth flip-flop
5 first register
6 second register
7 first comparator
8 second comparator
9 third comparator
10 memory module
Data image Data
Pos bit selection signal
Lval row selection signal
data image data
Reg1 first register
Reg2 second register
FM storage module
S1-S16
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in the actual implementation, the type, quantity and proportion of the components in the actual implementation can be changed freely, and the layout of the components can be more complicated.
Example one
Referring to fig. 1, the present invention provides a down-sampling circuit, which includes: the trigger comprises a first trigger unit 1, a second trigger unit 2, a third trigger unit 3, a fourth trigger unit 4, a first register 5, a second register 6, a first comparator 7, a second comparator 8, a third comparator 9 and a storage module 10.
The first trigger unit 1, the second trigger unit 2, the third trigger unit 3, and the fourth trigger unit 4 respectively receive image data, a bit selection signal, and a row selection signal, and are configured to respectively output four image data of different rows and columns in the same sampling window.
The input end of the first register 5 is connected with the output end of the first trigger unit 1 and is used for registering the output signal of the first trigger unit 1; the input end of the first comparator 7 is connected to the output ends of the first register 5 and the second trigger unit 2, and is configured to compare the output signals of the first register 5 and the second trigger unit 2 and output the greater output signal; the input end of the second comparator 8 is connected to the storage module 10 and the output end of the third trigger unit 3, and is configured to compare the output signal of the first comparator 7 with the output signal of the third trigger unit 3, and output the greater of the output signals.
The second register 6 is connected to the output end of the second comparator 8, and is used for registering the output signal of the second comparator 8; the input end of the third comparator 9 is connected to the output ends of the second register 6 and the fourth trigger unit 4, respectively, and is configured to compare the output signals of the second register 6 and the fourth trigger unit 4 and output the greater output signal.
The storage module 10 is connected to the output ends of the first comparator 7 and the third comparator 9, and is configured to store the output signal of the first comparator 7, and finally store the output signal of the third comparator 9.
In this embodiment, the first trigger unit 1 includes a first not gate 11, a second not gate 12, a first and gate 13, and a first flip-flop 14; the first not gate 11 receives the bit select signal; the second not gate 12 receives the row selection signal; the input end of the first and gate 13 is connected with the output ends of the first not gate 11 and the second not gate 12; the data input end of the first flip-flop 14 receives the image data, and the control end is connected to the output end of the first and gate 13.
In this embodiment, the second trigger unit 2 includes a third not gate 21, a second and gate 22, and a second flip-flop 23; the third not gate 21 receives the row selection signal; the input end of the second and gate 22 is connected to the output end of the third not gate 21 and receives the bit selection signal; the data input end of the second flip-flop 23 receives the image data, and the control end is connected to the output end of the second and gate 22.
In this embodiment, the third trigger unit 3 includes a fourth not gate 31, a third and gate 32, and a third flip-flop 33; the fourth not gate 31 receives the bit select signal; the input end of the third and gate 32 is connected to the output end of the fourth not gate 31, and receives the row selection signal; the data input end of the third flip-flop 33 receives the image data, and the control end is connected to the output end of the third and gate 32.
In this embodiment, the fourth trigger unit 4 includes a fourth and gate 41 and a fourth flip-flop 42; the input end of the fourth and gate 41 receives the bit selection signal and the row selection signal; the data input end of the fourth flip-flop 42 receives the image data, and the control end is connected to the output end of the fourth and gate 41.
In this embodiment, the input terminal of the first not gate 11, the first input terminal of the second and gate 22, the input terminal of the fourth not gate 31, and the first input terminal of the fourth and gate 41 all input the bit selection signal Pos; row selection signals Lval are input to the input end of the second NOT gate 12, the input end of the third NOT gate 21, the second input end of the third AND gate 32 and the second input end of the fourth AND gate 41; the first input terminal of the first flip-flop 14, the first input terminal of the second flip-flop 23, the first input terminal of the third flip-flop 33, and the first input terminal of the fourth flip-flop 42 each input image Data.
In this embodiment, the first flip-flop 14, the second flip-flop 23, the third flip-flop 33, and the fourth flip-flop 42 are all D flip-flops.
In this embodiment, the image data is an image feature value.
The working principle of the circuit is as follows: the bit selection signal Pos and the row selection signal Lval are combined by a not gate and/or an and gate to obtain different control signals to enable the flip-flops, and when the enable signal is at a high level, the image Data can effectively enter the corresponding flip-flops. In this embodiment, when the input of the bit selection signal Pos and the row selection signal Lval are both 0, only the first and gate 13 outputs a high level to enable the first flip-flop 14, and at this time, the image Data input simultaneously with the bit selection signal Pos and the row selection signal Lval is driven into the first flip-flop 14, and then the image Data is stored in the first register 5; when the input bit selection signal Pos is 1 and the row selection signal Lval is 0, only the second and gate 22 outputs a high level to enable the second flip-flop 23, at this time, the input image Data is input into the second flip-flop 23, and then the image Data in the second flip-flop 23 and the image Data in the first register 5 are compared by the first comparator 7, and a larger image Data is selected and stored in a corresponding position in the storage module 10.
When the input bit selection signal Pos is 0 and the row selection signal Lval is 1, only the third and gate 32 outputs a high level to enable the third flip-flop 33, at this time, the input image Data is input into the third flip-flop 33, the image Data in the third flip-flop 33 and the image Data in the storage module 10 are compared by the second comparator 8, and a larger image Data is selected and stored in the second register 6; when the input bit selection signal Pos is 1 and the line selection signal Lval is 1, only the fourth and gate 41 outputs a high level to enable the fourth flip-flop 42, at this time, the input image Data is input into the fourth flip-flop 42, the image Data in the fourth flip-flop 42 and the image Data in the second register 6 are compared by the third comparator 9, the larger image Data of the two is selected, and the selected image Data is stored in the storage block 10 as the finally stored image Data. It should be noted that if the image Data stored last in the storage module 10 does not coincide with the image Data stored before, the previous image Data is overwritten with the current (last) image Data because the last stored image Data is the maximum value of the image Data in one sampling, that is, the final image characteristic value.
Example two
The invention also provides a sampling method, the size of a down-sampling window is 2 x 2, namely two rows and two columns of four data, and the method comprises the following steps:
step 1), inputting image data, selecting the image data of a first row and a first column in a down-sampling window, and storing the image data in a first register.
As an example, the image data is input while a bit selection signal and a row selection signal are input, wherein the bit selection signal is 0 to represent data of odd columns in the down-sampling window, and the bit selection signal is 1 to represent data of even columns in the down-sampling window; the row select signal is 0 to indicate data of odd rows in the down-sampling window, and the row select signal is 1 to indicate data of even rows in the down-sampling window.
And judging the position of the input image data in the down-sampling window according to the bit selection signal and the row selection signal, and judging the input image data as the image data of the first row and the first column in the down-sampling window when the bit selection signal is 0 and the row selection signal is 0.
Step 2), selecting image data of a first row and a second column in a down-sampling window, comparing the image data with image data in a first register, and selecting larger image data of the two image data to be stored in a storage module; when the bit selection signal is 1 and the row selection signal is 0, the data input into the first row and the second column in the down sampling window is judged.
Step 3), selecting image data of a second row and a first column in the down-sampling window, comparing the image data with image data stored in the storage module, and selecting the larger image data of the two image data to store in a second register; when the bit selection signal is 0 and the row selection signal is 1, the data input into the second row and the first column in the down sampling window is judged.
And 4) selecting the image data of the second row and the second column in the down-sampling window, comparing the image data with the image data stored in the second register, and selecting the larger image data of the two image data to be stored in the storage module as a final output result. When the bit selection signal is 1 and the row selection signal is 1, the data input into the second row and the second column in the down sampling window is judged.
As an example, the sampling method further comprises dividing the memory module into N different address units, and satisfying: and N is a positive integer which is greater than or equal to 1, wherein M is the number of image data in one image, and M is greater than or equal to 4.
As an example, the address unit in which the image data selected in the step 4) is stored in the storage module is the same as the address unit in which the image data selected in the step 1) is stored in the storage module.
As an example, the image data output in step 4) is in one-to-one correspondence with address units in the storage module, and the image data is an image feature value.
Referring to fig. 2, in a specific example, the specific flow of the sampling method includes the following steps:
s1) inputting image data, i.e., image feature values;
s2) determining whether the bit selection signal is 0, if yes, proceeding to S3), and if no, proceeding to S4);
s3) determining whether the row selection signal is 0, if yes, proceeding to S5), and if no, proceeding to S6);
s4) determining whether the row selection signal is 0, if yes, proceeding to S7), and if no, proceeding to S8);
s5) storing the input image feature value in a first register Reg 1;
s6) determining whether the currently input image feature value is greater than the image feature value in the first register Reg1, if so, proceeding to S9), and if not, proceeding to S10);
s7) determining whether the currently input image feature value is greater than the image feature value in the first register Reg1, if so, proceeding to S11), and if not, proceeding to S12);
s8) determining whether the currently input image feature value is greater than the image feature value in the second register Reg2, if so, entering S13), and if not, entering S14);
s9) storing the current image characteristic value into a storage module FM, and entering S1);
s10) storing the image feature value in the first register Reg1 into the storage module FM, and proceeding to S1);
s11) storing the current image feature value in the second register Reg2, proceeding to S1);
s12) the image feature value in the first register Reg1 is stored in the second register Reg2, and the process proceeds to S1);
s13) storing the current image characteristic value in a corresponding storage unit in a storage module FM;
s14) storing the image feature values in the second register Reg2 in corresponding storage cells in the storage module FM;
s15) outputs the final image feature value, and ends.
As an example, please refer to fig. 3, which is a schematic diagram of image feature values input in maximum value down-sampling, 16 image feature values are subjected to four times of sampling through a 2 × 2 down-sampling window, and fig. 4 is a schematic diagram of output results after four times of sampling, and it can be seen that the maximum value in the output sample of each time of sampling is stored in the corresponding position of the output feature map. It should be noted that the image feature values in fig. 3 are randomly selected, and are not limited.
In summary, the present invention provides a resource-saving down-sampling circuit and a down-sampling method, which can solve the problem of buffering all input image data streams by using a bit selection signal and a row selection signal, and two first registers and two second registers for temporary storage. The invention reduces the large-scale input image to one fourth of the original image size, and the output does not change the overall detail characteristics of the original image; the dimensionality of an input image can be reduced, and compared with the method of storing the input of all data streams by using intermediate storage, the method only needs two registers, so that the consumption of a memory is reduced; the down-sampling method improves the calculation speed and can be realized on a programmable logic device FPGA. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (11)
1. A down-sampling circuit, comprising: the trigger comprises a first trigger unit, a second trigger unit, a third trigger unit, a fourth trigger unit, a first register, a second register, a first comparator, a second comparator, a third comparator and a storage module;
the first trigger unit, the second trigger unit, the third trigger unit and the fourth trigger unit respectively receive image data, a bit selection signal and a row selection signal and are used for respectively outputting four image data of different rows and columns in the same sampling window;
the input end of the first register is connected with the output end of the first trigger unit and is used for registering the output signal of the first trigger unit;
the input end of the first comparator is respectively connected with the output ends of the first register and the second trigger unit, and is used for comparing the output signals of the first register and the second trigger unit and outputting the larger output signal;
the input end of the second comparator is connected with the storage module and the output end of the third trigger unit, and is used for comparing the output signal of the first comparator with the output signal of the third trigger unit and outputting the larger of the output signals;
the second register is connected with the output end of the second comparator and used for registering the output signal of the second comparator;
the input end of the third comparator is respectively connected with the output ends of the second register and the fourth trigger unit, and is used for comparing the output signals of the second register and the fourth trigger unit and outputting the larger output signal;
the storage module is connected to the output ends of the first comparator and the third comparator, and is configured to store the output signal of the first comparator and finally store the output signal of the third comparator, and if the output signal of the third comparator is inconsistent with the output signal of the first comparator, the output signal of the third comparator covers the output signal of the first comparator.
2. The down-sampling circuit of claim 1, wherein the first trigger unit comprises a first not gate, a second not gate, a first and gate, and a first flip-flop;
the first NOT gate receives the bit selection signal; the second NOT gate receives the row selection signal; the input end of the first AND gate is connected with the output ends of the first NOT gate and the second NOT gate; the data input end of the first trigger receives the image data, and the control end of the first trigger is connected with the output end of the first AND gate.
3. The down-sampling circuit of claim 1, wherein the second trigger unit comprises a third not gate, a second and gate, and a second flip-flop;
the third NOT gate receives the row selection signal; the input end of the second AND gate is connected with the output end of the third NOT gate and receives the bit selection signal; and the data input end of the second trigger receives the image data, and the control end of the second trigger is connected with the output end of the second AND gate.
4. The down-sampling circuit of claim 1, wherein the third trigger unit comprises a fourth not gate, a third and gate, and a third flip-flop;
the fourth not gate receives the bit select signal; the input end of the third AND gate is connected with the output end of the fourth NOT gate and receives the row selection signal; and the data input end of the third trigger receives the image data, and the control end of the third trigger is connected with the output end of the third AND gate.
5. The down-sampling circuit of claim 1, wherein the fourth trigger unit comprises a fourth and gate and a fourth flip-flop;
the input end of the fourth AND gate receives the bit selection signal and the row selection signal; and the data input end of the fourth trigger receives the image data, and the control end of the fourth trigger is connected with the output end of the fourth AND gate.
6. A down-sampling method using the down-sampling circuit of any one of claims 1 to 5, the down-sampling window having a size of 2 x 2, the method comprising the steps of:
step 1), inputting image data, selecting image data of a first row and a first column in a down-sampling window, and storing the image data in a first register;
step 2), selecting image data of a first row and a second column in a down-sampling window, comparing the image data with image data in a first register, and selecting larger image data of the two image data to be stored in a storage module;
step 3), selecting image data of a second row and a first column in the down-sampling window, comparing the image data with image data stored in the storage module, and selecting the larger image data of the two image data to store in a second register;
and 4) selecting the image data of the second row and the second column in the down-sampling window, comparing the image data with the image data stored in the second register, and selecting the larger image data of the two image data to be stored in the storage module as a final output result.
7. The down-sampling method according to claim 6, wherein in the step 1), the image data is inputted with a bit selection signal and a row selection signal, wherein the bit selection signal is 0 to indicate data of odd columns in the down-sampling window, and the bit selection signal is 1 to indicate data of even columns in the down-sampling window; the row select signal is 0 to indicate data of odd rows in the down-sampling window, and the row select signal is 1 to indicate data of even rows in the down-sampling window.
8. The down-sampling method according to claim 7, further comprising determining a position of the input image data in the down-sampling window according to the bit selection signal and the row selection signal, and determining the input image data as the image data in the first row and the first column in the down-sampling window when the bit selection signal is 0 and the row selection signal is 0; when the bit selection signal is 1 and the row selection signal is 0, judging that the input is data of a first row and a second column in a down sampling window; when the bit selection signal is 0 and the row selection signal is 1, judging that the input is data of a second row and a first column in the down sampling window; and when the bit selection signal is 1 and the row selection signal is 1, judging that the input is data of a second row and a second column in the down sampling window.
9. The method of claim 8, further comprising partitioning the memory module into N different address units and satisfying: and N is a positive integer which is greater than or equal to 1, wherein M is the number of image data in one image, and M is greater than or equal to 4.
10. The method according to claim 9, wherein the image data selected in step 4) is stored in the same address location of the memory module as the image data selected in step 1).
11. The down-sampling method according to claim 10, wherein the image data output in step 4) has a one-to-one correspondence with address locations in the storage module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810312197.0A CN108616675B (en) | 2018-04-09 | 2018-04-09 | Down-sampling circuit and down-sampling method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810312197.0A CN108616675B (en) | 2018-04-09 | 2018-04-09 | Down-sampling circuit and down-sampling method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108616675A CN108616675A (en) | 2018-10-02 |
| CN108616675B true CN108616675B (en) | 2020-09-04 |
Family
ID=63659878
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810312197.0A Active CN108616675B (en) | 2018-04-09 | 2018-04-09 | Down-sampling circuit and down-sampling method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108616675B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20200111939A (en) * | 2019-03-20 | 2020-10-05 | 에스케이하이닉스 주식회사 | accelerating Appratus of neural network and operating method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101359504A (en) * | 2008-08-05 | 2009-02-04 | 中国科学院上海微系统与信息技术研究所 | High speed recording phase change memory and high speed recording method thereof |
| CN101715040A (en) * | 2008-09-30 | 2010-05-26 | 佳能株式会社 | Driving method of solid-state imaging apparatus |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006222708A (en) * | 2005-02-10 | 2006-08-24 | Matsushita Electric Ind Co Ltd | Dark-area-gradation deterioration correction circuit and solid-state imaging device |
| US10178329B2 (en) * | 2014-05-27 | 2019-01-08 | Rambus Inc. | Oversampled high dynamic-range image sensor |
-
2018
- 2018-04-09 CN CN201810312197.0A patent/CN108616675B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101359504A (en) * | 2008-08-05 | 2009-02-04 | 中国科学院上海微系统与信息技术研究所 | High speed recording phase change memory and high speed recording method thereof |
| CN101715040A (en) * | 2008-09-30 | 2010-05-26 | 佳能株式会社 | Driving method of solid-state imaging apparatus |
Non-Patent Citations (1)
| Title |
|---|
| GPU上基本图像处理算法性能优化关键技术研究;范梦然;《中国优秀硕士学位论文全文数据库 信息科技辑》;20171015;I138-234 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108616675A (en) | 2018-10-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110991311B (en) | Target detection method based on dense connection deep network | |
| US10621446B2 (en) | Handling perspective magnification in optical flow processing | |
| US20130083581A1 (en) | Nearest neighbor serial content addressable memory | |
| US11182908B2 (en) | Dense optical flow processing in a computer vision system | |
| CN110674742B (en) | Remote sensing image road extraction method based on DLinkNet | |
| CN109671042B (en) | Gray level image processing system and method based on FPGA morphological operator | |
| CN111768458A (en) | Sparse image processing method based on convolutional neural network | |
| CN108616675B (en) | Down-sampling circuit and down-sampling method | |
| CN104899835A (en) | Super-resolution processing method for image based on blind fuzzy estimation and anchoring space mapping | |
| JP2002511984A (en) | Apparatus and method for reducing systolic array memory bandwidth requirements | |
| CN111753962B (en) | Adder, multiplier, convolution layer structure, processor and accelerator | |
| US20230135109A1 (en) | Method for processing signal, electronic device, and storage medium | |
| CN111192279B (en) | Object segmentation method based on edge detection, electronic terminal and storage medium | |
| CN109727187B (en) | Method and device for adjusting storage position of multiple region of interest data | |
| CN108876701B (en) | Run-length-based single-scanning connected domain marking method and hardware structure thereof | |
| CN111310115A (en) | Data processing method, device and chip, electronic equipment and storage medium | |
| CN112419372B (en) | Image processing method, device, electronic equipment and storage medium | |
| CN113743587A (en) | Convolutional neural network pooling calculation method, system and storage medium | |
| CN105427235A (en) | Image browsing method and system | |
| CN111047026A (en) | Memory chip capable of executing artificial intelligence operation and operation method thereof | |
| CN111563580B (en) | Convolutional neural network implementation device and method | |
| CN110569684B (en) | Image binarization method for small-capacity cache | |
| CN113051901A (en) | Identification card text recognition method, system, medium and electronic terminal | |
| Li et al. | FPGA based mixture Gaussian background modeling and motion detection | |
| Lin et al. | The mesh with hybrid buses: an efficient parallel architecture for digital geometry |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |