CN104347113A - Read-out circuit and read-out method for phase change memory - Google Patents
Read-out circuit and read-out method for phase change memory Download PDFInfo
- Publication number
- CN104347113A CN104347113A CN201410675312.2A CN201410675312A CN104347113A CN 104347113 A CN104347113 A CN 104347113A CN 201410675312 A CN201410675312 A CN 201410675312A CN 104347113 A CN104347113 A CN 104347113A
- Authority
- CN
- China
- Prior art keywords
- read
- change memory
- memory cell
- target phase
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The invention provides a read-out circuit and a read-out method for a phase change memory. The read-out circuit comprises a target phase change storage unit, a reading circuit and a comparing circuit, wherein the target phase change storage unit is used for storing data; the reading circuit is used for generating a reading current according to a current state of the target phase change storage unit; the comparing unit is used for comparing the reading current with a reference reading current and generating a read-out voltage signal. When the phase change memory carries out read-out operation, a word line of the target phase change storage unit is set to a word line reading voltage; when read enabling is effective, a bit line where the target phase change storage unit is positioned can generate the corresponding reading current; by comparing the reading current with the reference reading current, the read-out voltage signal is obtained. According to the invention, a bit line voltage does not need to be limited in a clamping manner, and thus, the reading process can be effectively quickened; the read-out circuit and the read-out method are particularly suitable for the condition that when a Diode and the like are used as gate tubes, the array bi line of the phase change memory has a high voltage drop; read-out time delay caused by the bit line clamping manner and the like is avoided; the read-out circuit and the read-out method are beneficial for implementing a high-speed phase change memory product.
Description
Technical field
The present invention relates to microelectronics domain, particularly relate to a kind of sensing circuit and reading method of phase transition storage.
Background technology
Phase transition storage, it is a kind of novel resistive formula nonvolatile semiconductor memory, it for storage medium with chalcogenide compound material, utilizes and is worked into the phase-change material of the nano-scale resistance states different from time amorphous state (material is high-impedance state) in polycrystalline state (material is low resistive state) to realize the storage of data.
Phase transition storage is the storer of the Ao Fuxinsiji electronic effect proposed in late 1960s based on Ovshinsky, and it generally refers to chalcogenide compound random access memory, also referred to as Ao Fuxinsiji electrical effect Unified Memory.Phase transition storage is as a kind of new storer, because its read or write speed is fast, erasable permanance is high, keep information time long, low-power consumption, the characteristic such as non-volatile, particularly along with these characteristics of phase transition storage when size of process technology and storage unit narrows down to nanometer scale also become more and more outstanding, therefore it is thought by industry the storer of future generation having development potentiality most.
The basic unit of storage of phase transition storage is made up of phase-change material media units and gating switch unit.Wherein, phase transition storage gating device realizes storage array particular memory location by the switching manipulation function selecting to carry out reading and writing, and the gating device be employed at present comprises BJT, mosfet transistor and vertical Diode (diode).Wherein Diode as during gate tube because of the 4F of the technique upper limit (UL) achieved by its high current density
2cellar area, has application potential.
The data that store in phase transition storage (i.e. the crystalline state of phase change cells or amorphous state) will be read by sensing circuit, consider that its intuitive nature presented is low-resistance or high-impedance state, therefore, phase transition storage is all by under the control of reading enable signal and reading circuit, to electric current or the voltage of the less value of phase-change memory storage unit input, the magnitude of voltage then in measurement storage unit or current value realize.
Sensing circuit passes through the extremely low current value (magnitude of voltage) of transmission one to phase-change memory cell, the now voltage (electric current) of reading bit line, if bit-line voltage higher (electric current is less), expression phase change cells is high-impedance state, i.e. " 1 "; If bit-line voltage lower (electric current is larger), expression phase change cells is low resistance state, i.e. " 0 ".But in the process read, when there being electric current to flow through phase-change memory cell, phase-change memory cell can produce Joule heat, when the power of Joule heat is greater than the radiating efficiency of unit, this thermal effect can affect the basic status of phase-change memory cell; Meanwhile, when phase-change memory cell both end voltage difference exceedes some threshold values, can there is punch-through effect in the inner charge carrier of phase-change material, charge carrier increases suddenly, thus shows the characteristic of low-resistance, and now material itself does not undergo phase transition.Above-mentioned two phenomenons and so-calledly read breakoff phenomenon.In order to overcome above shortcoming, when sensing circuit forces read operation by the mode of clamper usually, the voltage of selected storage unit place bit line is less than the threshold voltage of phase-change material, thus avoids the generation of reading breakoff phenomenon.
For the phase transition storage based on BJT, MOSFET gating, usually very little owing to reading electric current on the one hand, gate tube produces pressure drop hardly when opening, and bit-line voltage is less, and is almost determined by the pressure drop in phase change cells; On the other hand, this phase-change memory cell based on three end gating devices its electric current when operating does not flow through word line path, but is flowed directly to publicly.Therefore, the general mode of bit line clamper that uses controls bit-line voltage when reading to overcome above-mentioned shortcoming.But for the phase transition storage based on Diode gating, due to the pressure drop of Diode self, during reading, bit-line voltage is lifted to (V
gST+ V
tHDiode), wherein V
tHDiodefor the unlatching threshold value of Diode.Thus cause bit-line voltage too high, quick clamper cannot be completed.
Therefore, the phase transition storage how effectively solved based on Diode gating limits by clamper mode that the bit-line voltage that bit-line voltage brings is too high, cannot to complete quick clamper problem be those skilled in the art's problem demanding prompt solutions.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of sensing circuit and reading method of phase transition storage, for solve be elevated based on the bit-line voltage of the phase transition storage of Diode gating in prior art and produce the speed affecting phase transition storage, read a character with two or more ways of pronunciation the problems such as bad.
For achieving the above object and other relevant objects, the invention provides a kind of sensing circuit of phase transition storage, the sensing circuit of described phase transition storage at least comprises:
Target phase-change memory cell, for storing data;
Reading circuit, is connected to described target phase-change memory cell, for providing voltage to described target phase-change memory cell, and produces read current according to the current state of described target phase-change memory cell;
Comparator circuit, is connected to described reading circuit, compares for described read current and one are read reference current, to produce the read-out voltage signal of described target phase-change memory cell.
Preferably, described target phase-change memory cell comprises phase change resistor and diode, and wherein, the positive pole that described phase change resistor one end connects described reading circuit, the other end connects described diode, the negative pole of described diode connects wordline and reads voltage.
Preferably, described reading circuit comprises the first transmission gate and one group of current mirror, and described current mirror comprises the first PMOS and the second PMOS; Wherein, one end of described first transmission gate connects the bit line of described target phase-change memory cell, the drain terminal of described first PMOS of other end connection; The source of described first PMOS connects power supply, and the grid end of described first PMOS is connected with the grid end of described second PMOS and is connected to the drain terminal of described first PMOS; The source of described second PMOS connects electric source and drain and connects described comparator circuit.
Preferably, described comparator circuit comprises one group of current mirror, described current mirror comprises the first NMOS tube and the second NMOS tube, wherein, the drain terminal of described first NMOS tube connects the output terminal of described reading circuit, the source ground connection of described first NMOS tube, the grid end of described first NMOS tube is connected with the grid end of described second NMOS tube and is connected to the drain terminal of described first NMOS tube, reads reference current described in the source ground connection of described second NMOS tube, drain terminal connect.
More preferably, described reference current of reading is provided by reference signal generation circuit, described reference signal generation circuit comprises reference unit, second transmission gate, 3rd PMOS and the 4th PMOS, wherein, one end of described reference unit connects the wordline of described target phase-change memory cell, the other end of described reference unit connects described second transmission gate, the other end of described second transmission gate connects the drain terminal of described 3rd PMOS, the source of described 3rd PMOS connects power supply, the grid end of described 3rd PMOS connects the grid end of described 4th PMOS and is connected to the drain terminal of described 3rd PMOS, the source of described 4th PMOS connects electric source and drain and connects described comparator circuit.
More preferably, described reference unit comprises reference resistance and reference diode, wherein, the positive pole that one end connects described second transmission gate, the other end connects described reference diode of described reference resistance, the negative pole of described reference diode connects the wordline of described target phase-change memory cell.
For achieving the above object and other relevant objects, the present invention also provides a kind of reading method of the sensing circuit based on above-mentioned phase transition storage, and the reading method of described phase transition storage at least comprises:
When described phase transition storage carries out read operation, the wordline of described target phase-change memory cell is set to described wordline and reads voltage;
When read enable effective time, the bit line at described target phase-change memory cell place produces corresponding read current by according to the state of described target phase-change memory cell, and is read by described reading circuit;
By described comparator circuit to described read current with read reference current and compare, to tell the state of described target phase-change memory cell and to obtain read-out voltage signal.
Preferably, the pressure drop of reading when voltage makes to read on described target phase-change memory cell of described wordline is less than the threshold voltage of described target phase-change memory cell.
Preferably, the state that described read current reads voltage and described target phase-change memory cell by described wordline is determined, described read current meets following relational expression:
I
rd＝V
GST/R
GST
Wherein, I
rdfor described read current, V
gSTfor the pressure drop on described target phase-change memory cell, described R
gSTfor the resistance of described phase change resistor.
Preferably, described read the state that reference current reads voltage and described target phase-change memory cell by described wordline and determine, described in read reference current and meet following relational expression:
I
rd_0<I
rdf<I
rd_1
Wherein, I
rd_0for read current during described target phase-change memory cell high resistant, I
rd_1for read current during described target phase-change memory cell low-resistance.
Preferably, described read-out voltage signal and chip internal operating voltage match.
As mentioned above, the sensing circuit of phase transition storage of the present invention and reading method, have following beneficial effect:
The sensing circuit of phase transition storage of the present invention and reading method do not need to limit bit-line voltage by the mode of clamper, therefore reading process can effectively be accelerated, be specially adapted to use Diode etc. to have the situation of higher pressure drop as phase transition storage array bitline during gate tube, avoid the reading time delay that the modes such as bit line clamper are brought, be conducive to the realization of high-speed phase change memory product.
Accompanying drawing explanation
Fig. 1 is shown as the sensing circuit principle schematic of phase transition storage of the present invention.
Fig. 2 is shown as the reading circuit structure schematic diagram of phase transition storage of the present invention.
Fig. 3 is shown as sensing circuit and the course of work schematic diagram of reading method when reading high resistant (amorphous state) of phase transition storage of the present invention.
Fig. 4 is shown as sensing circuit and the course of work schematic diagram of reading method when reading low-resistance (polycrystalline state) of phase transition storage of the present invention.
Element numbers explanation
1 target phase-change memory cell
2 reading circuits
21 first transmission gates
3 comparator circuits
4 reference signal generation circuits
41 reference units
42 second transmission gates
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this instructions can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this instructions also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to Fig. 1 ~ Fig. 4.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
Embodiment one
As shown in Figure 1, the invention provides a kind of sensing circuit of phase transition storage, the sensing circuit of described phase transition storage at least comprises:
Target phase-change memory cell 1, for storing data;
Reading circuit 2, is connected to described target phase-change memory cell 1, for providing voltage to described target phase-change memory cell 1, and produces read current I according to the current state of described target phase-change memory cell 1
rd;
Comparator circuit 3, is connected to described reading circuit 2, for by described read current I
rdreference current I is read with one
rdfcompare, to produce the read-out voltage signal D of described target phase-change memory cell 1
sA.
Particularly, as shown in Figure 1, in the present embodiment, described target phase-change memory cell 1 comprises phase change resistor R
gSTwith diode D1, wherein, described phase change resistor R
gSTthe positive pole that one end connects described reading circuit 2, the other end connects described diode D1, the negative pole of described diode D1 connects wordline and reads voltage V
wL.
As shown in Figure 1, described phase change resistor R
gSTthe one end be connected with described reading circuit 2 is as the bit line BL of described target phase-change memory cell 1, and described diode D1 and described wordline read voltage V
wLthe one end be connected is as the wordline WL of described target phase-change memory cell 1.As shown in Figure 1, in the present embodiment, described wordline reads voltage V
wLby power supply V
dd, described first PMOS PM1 threshold voltage V
thp, described diode D1 threshold value V
thdand from described power supply V
ddvoltage V is read to described wordline
wLother device pressure drops on path determine, described wordline reads voltage V
wLamplitude should make read time described target phase-change memory cell 1 on pressure drop V
gSTbe less than the threshold voltage V of described target phase-change memory cell 1
tHG, read a character with two or more ways of pronunciation bad to avoid described target phase-change memory cell 1.
Particularly, as shown in Figure 1, described reading circuit 2 comprises the first transmission gate 21 and one group of current mirror, and described current mirror comprises the first PMOS PM1 and the second PMOS PM2.Wherein, the drain terminal that one end of described first transmission gate 21 connects the bit line BL of described target phase-change memory cell 1, the other end connects described first PMOS PM1, the control end of described first transmission gate 21 connects one group and anti-phase reads enable signal RE and RE_.The source of described first PMOS PM1 connects described power supply V
dd, the grid end of described first PMOS PM1 is connected with the grid end of described second PMOS PM2 and is connected to the drain terminal of described first PMOS PM1; The source of described second PMOS PM2 connects described power supply V
dd, drain terminal connects described comparator circuit 3.
As shown in Figure 1, in the present embodiment, when described read enable signal RE and RE_ onset time, described first transmission gate 21 is opened, and the bit line BL of described target phase-change memory cell 1 produces the described read current I corresponding with the current state of described target phase-change memory cell 1
rd, described read current I
rdwith the drain terminal being mirrored to described second PMOS PM2 through described first PMOS PM1.
Particularly, as shown in Figure 1, described comparator circuit 3 is current comparator, has two input ends and an output terminal, the described read current I that described reading circuit 2 exports by described comparator circuit 3
rdreference current I is read with described
rdfcompare, and export the read-out voltage signal D of described target phase-change memory cell 1
sA, described read-out voltage signal D
sAmatch with chip internal operating voltage, described read-out voltage signal D
sAfor " 0 " or " 1 ".
Embodiment two
As shown in Figure 2, as another embodiment of the sensing circuit of phase transition storage of the present invention, the principle of the present embodiment is consistent with embodiment one, comprising:
Target phase-change memory cell 1, for storing data;
Reading circuit 2, is connected to described target phase-change memory cell 1, for providing voltage to described target phase-change memory cell 1, and produces read current I according to the current state of described target phase-change memory cell 1
rd;
Comparator circuit 3, is connected to described reading circuit 2, for by described read current I
rdreference current I is read with one
rdfcompare, to produce the read-out voltage signal D of described target phase-change memory cell 1
sA.
Consistent with embodiment one of the structure of described target phase-change memory cell 1 and described reading circuit 2 and principle, does described comparator circuit 3 and describes more specifically.
Particularly, as shown in Figure 2, described comparator circuit 3 comprises one group of current mirror, and described current mirror comprises the first NMOS tube NM1 and the second NMOS tube NM2.Wherein, the drain terminal of described first NMOS tube NM1 connects the output terminal of described reading circuit 2, i.e. the drain terminal of described second PMOS PM2; The source ground connection Gnd of described first NMOS tube NM1, the grid end of described first NMOS tube NM1 is connected with the grid end of described second NMOS tube NM2 and is connected to the drain terminal of described first NMOS tube NM1, reads reference current I described in the source ground connection Gnd of described second NMOS tube NM2, drain terminal connect
rdf.
More specifically, as shown in Figure 2, reference current I is read described in
rdfthered is provided by reference signal generation circuit 4, described reference signal generation circuit 4 comprises reference unit 41, second transmission gate 42, the 3rd PMOS PM3 and the 4th PMOS PM4.Wherein, described reference unit 41 comprises reference resistance R
0and reference diode D2, described reference resistance R
0one end connect the positive pole that described second transmission gate 42, the other end connect described reference diode D2, the negative pole of described reference diode D2 connects the wordline WL of described target phase-change memory cell 1.The other end of described second transmission gate 42 connects the drain terminal of described 3rd PMOS PM3, and the source of described 3rd PMOS PM3 connects power supply V
dd, the grid end of described 3rd PMOS PM3 connects the grid end of described 4th PMOS PM4 and is connected to the drain terminal of described 3rd PMOS PM3; The source of described 4th PMOS PM4 connects power supply V
dd, drain terminal connects described comparator circuit 3.
Described first PMOS PM1 and described second PMOS PM2 is by described read current I
rdbe mirrored to the drain terminal of described first NMOS tube NM1, described 3rd PMOS PM3 and described 4th PMOS PM4 reads reference current I by described
rdfbe mirrored to the drain terminal of described second NMOS tube NM2, and exported in the form of voltage by comparative result, described comparative result is described read-out voltage signal D
sA.
As shown in Fig. 1 ~ Fig. 2, the present invention also provides a kind of reading method of the sensing circuit based on above-mentioned phase transition storage, and the reading method of described phase transition storage at least comprises:
When described phase transition storage carries out read operation, the wordline WL of described target phase-change memory cell 1 is set to described wordline and reads voltage V
wL.
Particularly, described wordline reads voltage V
wLpressure drop V when making to read on described target phase-change memory cell 1
gSTbe less than the threshold voltage V of described target phase-change memory cell 1
tHG, read a character with two or more ways of pronunciation bad to avoid described target phase-change memory cell 1.
When reading enable RE and RE_ and being effective, described first transmission gate 21 is opened, and the bit line BL at described target phase-change memory cell 1 place produces corresponding read current I by according to the state of described target phase-change memory cell 1
rd, and read by described reading circuit 2.
Particularly, described read current I
rdvoltage V is read by described wordline
wLand the state of described target phase-change memory cell 1 is determined, described read current I
rdmeet following relational expression:
I
rd＝V
GST/R
GST
Wherein, I
rdfor described read current, V
gSTfor the pressure drop on described target phase-change memory cell, described R
gSTfor the resistance of described phase change resistor.
By described comparator circuit 3 to described read current I
rdwith read reference current I
rdfcompare, to tell the state of described target phase-change memory cell 1 and to obtain read-out voltage signal D
sA.
Particularly, described in read enable RE and RE_ effective, described second transmission gate 42 is opened, described in the state of described reference unit 41 obtains, read reference current I
rdf, described 3rd PMOS PM3 and described 4th PMOS PM4 reads reference current I by described
rdfbe mirrored to described comparator circuit 3, and with described read current I
rdafter export described read-out voltage signal D
sA.Described reads reference current I
rdfvoltage V is read by described wordline
wLand the state of described target phase-change memory cell 1 is determined, described in read reference current I
rdfmeet following relational expression:
I
rd_0<I
rdf<I
rd_1
Wherein, I
rd_0for read current during described target phase-change memory cell high resistant, I
rd_1for read current during described target phase-change memory cell low-resistance.
As shown in Figure 3, be sensing circuit and the simulation result of reading method when reading high resistant (amorphous state) of phase transition storage of the present invention, wherein, high resistant is set to 200K Ω, described reference resistance R
0be set to 100K Ω.Read, described wordline reads voltage V
wLbe set to 0.6V, supply voltage V
ddbe set to 2.5V, described in read enable signal RE effective, the bit-line voltage V produced with this understanding
bLslowly rise to 1.7V, and the pressure drop V on described target phase-change memory cell 1
gSTbe less than 0.5V, thus effectively prevent and read a character with two or more ways of pronunciation bad effect.Meanwhile, the sensing circuit of phase transition storage of the present invention and the readout time of reading method by Time dependent when reading high resistant, described read-out voltage signal D
sAafter 50ns, carry out saltus step, visible, the reading time effectively accelerates.
As shown in Figure 4, be sensing circuit and the simulation result of reading method when reading low-resistance (polycrystalline state) of phase transition storage of the present invention, wherein, low-resistance is set to 50K Ω, described reference resistance R
0be set to 100K Ω.Read, described wordline reads voltage V
wLbe set to 0.6V, supply voltage V
ddbe set to 2.5V, described in read enable signal RE effective, institute bitline voltage V with this understanding
bLslowly rise to 1.7V, and the pressure drop V on described target phase-change memory cell 1
gSTbe less than 0.5V, thus effectively prevent and read a character with two or more ways of pronunciation bad effect.
The sensing circuit of phase transition storage of the present invention and reading method, when phase transition storage carries out read operation, the wordline of target phase-change memory cell is set to readout word line voltage, thus make the pressure drop on target phase-change memory cell in read procedure, be less than the threshold voltage of target phase-change memory cell, and then target phase-change memory cell is avoided to read the generation of breakoff phenomenon; When read enable effective time, the bit line at target phase-change memory cell place produces corresponding read current by according to the state of target phase-change memory cell; By comparing read current and reading the size of reference current, the voltage signal " 1 " that the state obtaining just can telling target phase-change memory cell reads or " 0 ".Because the method does not need to limit bit-line voltage by the mode of clamper, therefore reading process can effectively be accelerated, be specially adapted to use Diode etc. to have the situation of higher pressure drop as phase transition storage array bitline during gate tube, avoid the reading time delay that the modes such as bit line clamper are brought, be conducive to the realization of high-speed phase change memory product.
In sum, the invention provides a kind of sensing circuit of phase transition storage, comprising the target phase-change memory cell for storing data; The reading circuit of read current is produced according to the current state of target phase-change memory cell; By read current with read reference current and compare, and produce the comparator circuit of read-out voltage signal.When phase transition storage carries out read operation, the wordline of target phase-change memory cell is set to readout word line voltage, thus make the pressure drop on target phase-change memory cell in read procedure, be less than the threshold voltage of target phase-change memory cell, and then target phase-change memory cell is avoided to read the generation of breakoff phenomenon; When read enable effective time, the bit line at target phase-change memory cell place produces corresponding read current by according to the state of target phase-change memory cell; By comparing read current and reading the size of reference current, the voltage signal that the state obtaining just can telling target phase-change memory cell reads.The sensing circuit of phase transition storage of the present invention and reading method do not need to limit bit-line voltage by the mode of clamper, therefore reading process can effectively be accelerated, be specially adapted to use Diode etc. to have the situation of higher pressure drop as phase transition storage array bitline during gate tube, avoid the reading time delay that the modes such as bit line clamper are brought, be conducive to the realization of high-speed phase change memory product.So the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (11)
1. a sensing circuit for phase transition storage, is characterized in that, the sensing circuit of described phase transition storage at least comprises:
Target phase-change memory cell, for storing data;
Reading circuit, is connected to described target phase-change memory cell, for providing voltage to described target phase-change memory cell, and produces read current according to the current state of described target phase-change memory cell;
Comparator circuit, is connected to described reading circuit, for by described read current with read reference signal and compare, to produce the read-out voltage signal of described target phase-change memory cell.
2. the sensing circuit of phase transition storage according to claim 1, it is characterized in that: described target phase-change memory cell comprises phase change resistor and diode, wherein, the positive pole that described phase change resistor one end connects described reading circuit, the other end connects described diode, the negative pole of described diode connects wordline and reads voltage.
3. the sensing circuit of phase transition storage according to claim 1, is characterized in that: described reading circuit comprises the first transmission gate and one group of current mirror, and described current mirror comprises the first PMOS and the second PMOS; Wherein, one end of described first transmission gate connects the bit line of described target phase-change memory cell, the drain terminal of described first PMOS of other end connection; The source of described first PMOS connects power supply, and the grid end of described first PMOS is connected with the grid end of described second PMOS and is connected to the drain terminal of described first PMOS; The source of described second PMOS connects electric source and drain and connects described comparator circuit.
4. the sensing circuit of phase transition storage according to claim 1, it is characterized in that: described comparator circuit comprises one group of current mirror, described current mirror comprises the first NMOS tube and the second NMOS tube, wherein, the drain terminal of described first NMOS tube connects the output terminal of described reading circuit, the source ground connection of described first NMOS tube, the grid end of described first NMOS tube is connected with the grid end of described second NMOS tube and is connected to the drain terminal of described first NMOS tube, reads reference current described in the source ground connection of described second NMOS tube, drain terminal connect.
5. the sensing circuit of the phase transition storage according to claim 1 or 4, it is characterized in that: described in read reference current and provided by reference signal generation circuit, described reference signal generation circuit comprises reference unit, second transmission gate, 3rd PMOS and the 4th PMOS, wherein, one end of described reference unit connects the wordline of described target phase-change memory cell, the other end of described reference unit connects described second transmission gate, the other end of described second transmission gate connects the drain terminal of described 3rd PMOS, the source of described 3rd PMOS connects power supply, the grid end of described 3rd PMOS connects the grid end of described 4th PMOS and is connected to the drain terminal of described 3rd PMOS, the source of described 4th PMOS connects electric source and drain and connects described comparator circuit.
6. the sensing circuit of phase transition storage according to claim 5, it is characterized in that: described reference unit comprises reference resistance and reference diode, wherein, the positive pole that one end connects described second transmission gate, the other end connects described reference diode of described reference resistance, the negative pole of described reference diode connects the wordline of described target phase-change memory cell.
7. the reading method of the sensing circuit of the phase transition storage as described in claim 1 ~ 6 any one, is characterized in that, the reading method of described phase transition storage at least comprises:
When described phase transition storage carries out read operation, the wordline of described target phase-change memory cell is set to described wordline and reads voltage;
When read enable effective time, the bit line at described target phase-change memory cell place produces corresponding read current by according to the state of described target phase-change memory cell, and is read by described reading circuit;
By described comparator circuit to described read current with read reference current and compare, to tell the state of described target phase-change memory cell and to obtain read-out voltage signal.
8. the reading method of phase transition storage according to claim 7, is characterized in that: the pressure drop of reading when voltage makes to read on described target phase-change memory cell of described wordline is less than the threshold voltage of described target phase-change memory cell.
9. the reading method of phase transition storage according to claim 7, is characterized in that: the state that described read current reads voltage and described target phase-change memory cell by described wordline is determined, described read current meets following relational expression:
I
rd＝V
GST/R
GST
Wherein, I
rdfor described read current, V
gSTfor the pressure drop on described target phase-change memory cell, described R
gSTfor the resistance of described phase change resistor.
10. the reading method of phase transition storage according to claim 7, is characterized in that: described read the state that reference current reads voltage and described target phase-change memory cell by described wordline and determine, described in read reference current and meet following relational expression:
I
rd_0<I
rdf<I
rd_1
Wherein, I
rd_0for read current during described target phase-change memory cell high resistant, I
rd_1for read current during described target phase-change memory cell low-resistance.
The sensing circuit of 11. phase transition storages according to claim 7, is characterized in that: described read-out voltage signal and chip internal operating voltage match.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410675312.2A CN104347113B (en) | 2014-11-21 | 2014-11-21 | The reading circuit and reading method of a kind of phase transition storage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410675312.2A CN104347113B (en) | 2014-11-21 | 2014-11-21 | The reading circuit and reading method of a kind of phase transition storage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104347113A true CN104347113A (en) | 2015-02-11 |
| CN104347113B CN104347113B (en) | 2017-10-27 |
Family
ID=52502554
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410675312.2A Active CN104347113B (en) | 2014-11-21 | 2014-11-21 | The reading circuit and reading method of a kind of phase transition storage |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104347113B (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104778963A (en) * | 2015-04-01 | 2015-07-15 | 山东华芯半导体有限公司 | RRAM sensitive amplifier |
| CN105931665A (en) * | 2016-04-19 | 2016-09-07 | 中国科学院上海微系统与信息技术研究所 | Readout circuit and method for phase change memory |
| CN106098098A (en) * | 2016-06-22 | 2016-11-09 | 上海华虹宏力半导体制造有限公司 | Current comparison circuit, memorizer and electric current comparative approach |
| CN106875963A (en) * | 2017-02-21 | 2017-06-20 | 中国科学院上海微系统与信息技术研究所 | A kind of three-dimensional storage reading circuit and reading method |
| WO2017215119A1 (en) * | 2016-06-17 | 2017-12-21 | Shanghai Institute Of Microsystem And Information Technology, Chinese Academy Of Sciences | Read circuit of storage class memory |
| CN108922574A (en) * | 2018-06-20 | 2018-11-30 | 中国科学院上海微系统与信息技术研究所 | The high-speed data reading circuit and reading method of phase transition storage |
| CN109840047A (en) * | 2017-11-27 | 2019-06-04 | 华为技术有限公司 | It is a kind of to reduce the method and device for reading delay |
| CN111653299A (en) * | 2020-04-27 | 2020-09-11 | 中国科学院微电子研究所 | Sense amplifier and memory |
| CN111653304A (en) * | 2020-04-27 | 2020-09-11 | 中国科学院微电子研究所 | Memory and current-limiting protection circuit thereof |
| CN111653303A (en) * | 2020-04-27 | 2020-09-11 | 中国科学院微电子研究所 | Memory and reading circuit thereof |
| CN111755036A (en) * | 2019-03-27 | 2020-10-09 | 中芯国际集成电路制造(上海)有限公司 | Frequency comparison type reading amplification circuit |
| CN112086113A (en) * | 2019-06-14 | 2020-12-15 | 中电海康集团有限公司 | Reading circuit for reading the resistance state of a memory cell |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102820056B (en) * | 2011-06-07 | 2015-05-20 | 中国科学院上海微系统与信息技术研究所 | Data readout circuit for phase change memorizer |
| CN102820055B (en) * | 2011-06-07 | 2015-03-25 | 中国科学院上海微系统与信息技术研究所 | Data readout circuit for phase change memorizer |
| CN104318955B (en) * | 2014-11-11 | 2017-05-24 | 中国科学院上海微系统与信息技术研究所 | Data reading circuit and data reading method of phase change memory based on diode gating |
-
2014
- 2014-11-21 CN CN201410675312.2A patent/CN104347113B/en active Active
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104778963B (en) * | 2015-04-01 | 2017-04-12 | 山东华芯半导体有限公司 | RRAM sensitive amplifier |
| CN104778963A (en) * | 2015-04-01 | 2015-07-15 | 山东华芯半导体有限公司 | RRAM sensitive amplifier |
| CN105931665A (en) * | 2016-04-19 | 2016-09-07 | 中国科学院上海微系统与信息技术研究所 | Readout circuit and method for phase change memory |
| CN105931665B (en) * | 2016-04-19 | 2020-06-09 | 中国科学院上海微系统与信息技术研究所 | Phase change memory reading circuit and method |
| US10679697B2 (en) | 2016-06-17 | 2020-06-09 | Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Science | Read circuit of storage class memory with a read reference circuit, having same bit line parasitic parameters and same read transmission gate parasitic parameters as memory |
| WO2017215119A1 (en) * | 2016-06-17 | 2017-12-21 | Shanghai Institute Of Microsystem And Information Technology, Chinese Academy Of Sciences | Read circuit of storage class memory |
| CN106098098A (en) * | 2016-06-22 | 2016-11-09 | 上海华虹宏力半导体制造有限公司 | Current comparison circuit, memorizer and electric current comparative approach |
| CN106875963A (en) * | 2017-02-21 | 2017-06-20 | 中国科学院上海微系统与信息技术研究所 | A kind of three-dimensional storage reading circuit and reading method |
| CN109840047A (en) * | 2017-11-27 | 2019-06-04 | 华为技术有限公司 | It is a kind of to reduce the method and device for reading delay |
| US11210210B2 (en) | 2017-11-27 | 2021-12-28 | Huawei Technologies Co., Ltd. | Read latency reduction method and apparatus |
| CN108922574A (en) * | 2018-06-20 | 2018-11-30 | 中国科学院上海微系统与信息技术研究所 | The high-speed data reading circuit and reading method of phase transition storage |
| CN108922574B (en) * | 2018-06-20 | 2020-11-13 | 中国科学院上海微系统与信息技术研究所 | High-speed data reading circuit and method of phase change memory |
| CN111755036A (en) * | 2019-03-27 | 2020-10-09 | 中芯国际集成电路制造(上海)有限公司 | Frequency comparison type reading amplification circuit |
| CN112086113A (en) * | 2019-06-14 | 2020-12-15 | 中电海康集团有限公司 | Reading circuit for reading the resistance state of a memory cell |
| CN111653299A (en) * | 2020-04-27 | 2020-09-11 | 中国科学院微电子研究所 | Sense amplifier and memory |
| CN111653304A (en) * | 2020-04-27 | 2020-09-11 | 中国科学院微电子研究所 | Memory and current-limiting protection circuit thereof |
| CN111653303A (en) * | 2020-04-27 | 2020-09-11 | 中国科学院微电子研究所 | Memory and reading circuit thereof |
| CN111653299B (en) * | 2020-04-27 | 2022-07-01 | 中国科学院微电子研究所 | Sense amplifier and memory |
| CN111653304B (en) * | 2020-04-27 | 2022-07-08 | 中国科学院微电子研究所 | Memory and current-limiting protection circuit thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104347113B (en) | 2017-10-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104347113A (en) | Read-out circuit and read-out method for phase change memory | |
| CN102820056B (en) | Data readout circuit for phase change memorizer | |
| Xu et al. | Design implications of memristor-based RRAM cross-point structures | |
| Mohammad et al. | Robust hybrid memristor-CMOS memory: Modeling and design | |
| CN101976578B (en) | Data readout circuit and readout method of phase-change storage unit | |
| CN106875963B (en) | A kind of three-dimensional storage reading circuit and reading method | |
| CN106205684B (en) | A kind of phase transition storage reading circuit and reading method | |
| CN106356090B (en) | Phase transition storage reading circuit and its method for reading data | |
| CN105849809A (en) | Non-volatile sram with multiple storage states | |
| CN105931665B (en) | Phase change memory reading circuit and method | |
| CN104318955A (en) | Data reading circuit and data reading method of phase change memory based on diode gating | |
| CN103646668B (en) | Disposable programmable memory and programmed method thereof and read method | |
| CN101833992B (en) | Phase-change random access memory system with redundant storage unit | |
| CN101419836B (en) | Phase change RAM | |
| CN104134461A (en) | Reading circuit structure of HMC | |
| CN109903801A (en) | The data reading circuit and method of phase transition storage | |
| CN209843258U (en) | Non-volatile memory sensitive amplifier and phase change memory | |
| CN102842340B (en) | Based on SRAM circuit and the reading/writing method thereof of PNPN structure | |
| Indaco et al. | On the impact of process variability and aging on the reliability of emerging memories (Embedded tutorial) | |
| CN110164497B (en) | Nonvolatile memory sense amplifier and phase change memory | |
| CN108922574B (en) | High-speed data reading circuit and method of phase change memory | |
| CN101958148B (en) | Phase change random access memory unit structure capable of eliminating interference and phase change random access memory formed by same | |
| Lei et al. | Enhanced read performance for phase change memory using a reference column | |
| CN201655330U (en) | Phase-change random memory | |
| Zhang et al. | Fast Low Power 4 Transistor 4 Memristor Sense Amplifier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |