CN111653304A - Memory and current-limiting protection circuit thereof - Google Patents
Memory and current-limiting protection circuit thereof Download PDFInfo
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- CN111653304A CN111653304A CN202010345423.2A CN202010345423A CN111653304A CN 111653304 A CN111653304 A CN 111653304A CN 202010345423 A CN202010345423 A CN 202010345423A CN 111653304 A CN111653304 A CN 111653304A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
- G11C13/0026—Bit-line or column circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0059—Security or protection circuits or methods
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Abstract
The invention discloses a memory and a current-limiting protection circuit thereof, wherein the current-limiting protection circuit comprises: a bit line voltage generating circuit for generating a bit line voltage required for a set operation of a target memory cell and outputting a bit line current; the current sampling circuit is used for sampling the bit line current and outputting a sampling current; the comparison control circuit is used for generating a first control signal when the sampling current is smaller than the reference current and generating a second control signal when the sampling current is not smaller than the reference current; and the switch circuit is used for transmitting the bit line voltage to the target storage unit when receiving the first control signal and isolating the bit line voltage generation circuit and the target storage unit when receiving the second control signal. The memory and the current-limiting protection circuit thereof can save current-limiting protection measures of test equipment during setting operation and simplify high-voltage signals provided by the test equipment.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a memory and a current-limiting protection circuit thereof.
Background
Resistive Random Access Memories (RRAMs) are a new type of non-volatile memory that has a wide range of applications in embedded applications and in stand-alone applications. After the memory cell of the resistive random access memory is initialized, basic operations of the memory cell include a set operation, a reset operation and a resistance state reading operation, wherein the set operation is to change the memory cell from a high resistance state to a low resistance state, the reset operation is to change the memory cell from the low resistance state to the high resistance state, the resistance state reading operation is to read the resistance value of the memory cell, and the memory cell is judged to be in the high resistance state or the low resistance state. In the setting operation process, the magnitude of the current flowing through the memory unit must be controlled in a current limiting mode, and the situation that the device is subjected to unrecoverable breakdown due to the fact that the current is too large is avoided.
In the prior art, a high-voltage pulse signal required by the resistive random access memory unit in the setting operation process is provided by test equipment outside a chip. The test equipment outside the chip has a current-limiting protection function, and after the limiting current is set, the resistive random access memory unit can be ensured not to have a large current to pass through in the setting operation process. However, the above-mentioned techniques have the following technical drawbacks: the high-voltage pulse signal and the current-limiting protection function are provided by test equipment outside the chip, on-chip integration cannot be performed, and the high-voltage pulse signal and the current-limiting protection function are not suitable for high-capacity and high-density resistive random access memory chips and embedded applications.
Disclosure of Invention
The invention aims to solve the problem that a high-voltage pulse signal and a current-limiting protection function required by a resistive random access memory unit in the setting operation process are provided by test equipment outside a chip and cannot be integrated on the chip.
The invention is realized by the following technical scheme:
a current limiting protection circuit for a memory, comprising:
the bit line voltage generating circuit is used for generating bit line voltage required by setting operation on a target memory cell according to voltage provided by an external high-voltage power supply and outputting bit line current when the target memory cell is set;
the current sampling circuit is used for sampling the bit line current and outputting a sampling current;
the comparison control circuit is used for comparing the sampling current with a reference current, generating a first control signal when the sampling current is smaller than the reference current, generating a second control signal when the sampling current is not smaller than the reference current, and latching the second control signal;
and the switch circuit is used for transmitting the bit line voltage to the target storage unit when receiving the first control signal and isolating the bit line voltage generation circuit and the target storage unit when receiving the second control signal.
Optionally, the bit line voltage generating circuit includes an operational amplifier, a first resistor, a second resistor, and a first transistor;
the non-inverting input end of the operational amplifier is used for receiving a reference voltage, the inverting input end of the operational amplifier is connected with one end of the first resistor and one end of the second resistor, the output end of the operational amplifier is connected with the control end of the first transistor, and the power supply end of the operational amplifier is connected with the external high-voltage power supply;
the other end of the first resistor is grounded, and the other end of the second resistor is connected with one end of the first transistor and used for generating the bit line voltage;
the other end of the first transistor is used for outputting the bit line current.
Optionally, the first transistor is an NMOS transistor, the control end of the first transistor is a gate of the NMOS transistor, one end of the first transistor is a source of the NMOS transistor, and the other end of the first transistor is a drain of the NMOS transistor.
Optionally, the current sampling circuit includes a second transistor and a third transistor;
one end of the second transistor is connected with the control end of the second transistor and the control end of the third transistor and used for receiving the bit line current, one end of the third transistor is used for outputting the sampling current, and the other end of the second transistor and the other end of the third transistor are used for being connected with the external high-voltage power supply.
Optionally, the second transistor and the third transistor are PMOS transistors, one end of the second transistor and one end of the third transistor are drains of the PMOS transistors, the other end of the second transistor and the other end of the third transistor are sources of the PMOS transistors, and a control end of the second transistor and a control end of the third transistor are gates of the PMOS transistors.
Optionally, the comparison control circuit includes a comparison node, a latch, and a reference current source, and the reference current source is configured to provide the reference current;
the comparison node is used for receiving the sampling current and comparing the sampling current with the reference current to obtain a comparison voltage;
the input end of the latch is used for receiving the comparison voltage, and the output end of the latch is used as the output end of the comparison control circuit.
Optionally, the switching circuit comprises a fourth transistor;
one end of the fourth transistor is connected with the target storage unit, the other end of the fourth transistor is used for receiving the bit line voltage, and the control end of the fourth transistor is connected with the output end of the comparison control circuit.
Optionally, the fourth transistor is a PMOS transistor, the control end of the fourth transistor is a gate of the PMOS transistor, one end of the fourth transistor is a drain of the PMOS transistor, and the other end of the fourth transistor is a source of the PMOS transistor.
Optionally, the target memory cell includes a gating transistor and a variable resistor;
the control end of the gating transistor is used for receiving word line voltage, one end of the gating transistor is used for receiving source line voltage, the other end of the gating transistor is connected with one end of the variable resistor, and the other end of the variable resistor is used for receiving bit line voltage.
Based on the same inventive concept, the invention also provides a memory, which comprises the current limiting protection circuit.
Compared with the prior art, the invention has the following advantages and beneficial effects:
the invention provides a memory and a current-limiting protection circuit thereof, wherein the current-limiting protection circuit comprises a bit line voltage generating circuit, a current sampling circuit, a comparison control circuit and a switch circuit, wherein the bit line voltage generating circuit generates bit line voltage required by setting operation of a target storage unit according to voltage provided by an external high-voltage power supply and outputs bit line current when the target storage unit is set; the current sampling circuit samples the bit line current and outputs a sampling current; the comparison control circuit compares the sampling current with a reference current, generates a first control signal when the sampling current is smaller than the reference current, and generates a second control signal when the sampling current is not smaller than the reference current; the switch circuit transmits the bit line voltage to the target memory cell when receiving the first control signal, and isolates the bit line voltage generation circuit from the target memory cell when receiving the second control signal.
In the process of setting the target memory cell, the resistance of the resistive switching device is gradually reduced, and the current flowing through the target memory cell is gradually increased. When the target memory cell is just started to be set, the bit line current is small, correspondingly, the sampling current is smaller than the reference current, the comparison control circuit outputs the first control signal, controls the switch circuit to be conducted, and transmits the bit line voltage to the target memory cell; after a period of setting operation, the bit line current is gradually increased, and when the sampling current is not less than the reference current, the comparison control circuit latches and outputs the second control signal to control the switch circuit to be switched off, so that the bit line voltage generating circuit is isolated from the target storage unit, the bit line current is not increased any more, and the next setting operation is waited to arrive.
The memory and the current-limiting protection circuit thereof can save the current-limiting protection measure of the test equipment during setting operation and simplify the high-voltage signal provided by the test equipment; the current-limiting protection circuit can be integrated on a chip, so that the chip design and embedded application of the high-capacity and high-density resistive random access memory are facilitated; the width of the high voltage pulse required for the set operation can be accurately controlled.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
fig. 1 is a circuit diagram of a current-limiting protection circuit according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.
The embodiment of the invention provides a current-limiting protection circuit of a memory, wherein the memory can be a Resistive Random Access Memory (RRAM), a phase change memory (PRAM), a Magnetic Random Access Memory (MRAM) or the like. Fig. 1 is a circuit diagram of the current limiting protection circuit, which includes a bit line voltage generation circuit 11, a current sampling circuit 12, a comparison control circuit 13, and a switch circuit 15.
Specifically, the bit line voltage generating circuit 11 is configured to generate a bit line voltage required for a set operation on the target memory cell 10 according to a voltage provided by an external high voltage power supply VPUMP, and output a bit line current when the set operation is performed on the target memory cell 10, where the bit line current is a current flowing through the target memory cell 10. The target memory cell 10 is a memory cell that needs to be set, i.e., a memory cell that needs to be changed from a high resistance state to a low resistance state. Taking the memory as a resistive random access memory as an example, the target memory cell 10 includes a gating transistor M0 and a variable resistor R0. The control end of the gating transistor M0 is connected with a word line WL and is used for receiving word line voltage; one end of the gating transistor M0 is connected with a source line SL and is used for receiving source line voltage; the other end of the gating transistor M0 is connected to one end of the variable resistor R0, and the other end of the variable resistor R0 is used for receiving the bit line voltage.
The current sampling circuit 12 is configured to sample the bit line current, that is, sample a current flowing through the target memory cell 10, and output a sampling current.
The comparison control circuit 13 is configured to compare the sampling current with a reference current, generate a first control signal when the sampling current is smaller than the reference current, generate a second control signal when the sampling current is not smaller than the reference current, and latch the second control signal. The reference current is set according to the current that the target memory cell 10 can bear when the target memory cell 10 is set, and the current sampling ratio of the current sampling circuit 12, which is not limited in this embodiment.
The switch circuit 14 is configured to be turned on when receiving the first control signal, and transmit the bit line voltage to the target memory cell 10, that is, apply the bit line voltage to the target memory cell; the switch circuit 14 is turned off upon receiving the second control signal, and isolates the bit line voltage generation circuit 11 from the target memory cell 10, i.e., stops applying the bit line voltage to the target memory cell.
In the process of setting the target memory cell 10, since the resistance of the resistive switching device is gradually decreased, the current flowing through the target memory cell 10 is gradually increased. When the set operation is just started on the target memory cell 10, the bit line current is small, accordingly, the sampling current is smaller than the reference current, the comparison control circuit 13 outputs the first control signal, controls the switch circuit 14 to be turned on, and transmits the bit line voltage to the target memory cell 10; after a period of setting operation, the bit line current is gradually increased, and when the sampling current is increased to be not less than the reference current, the comparison control circuit 13 latches and outputs the second control signal to control the switch circuit 14 to be switched off, so that the bit line voltage generation circuit 11 is isolated from the target memory cell 10, the bit line current is not increased any more, and the next setting operation is waited for.
Different from the prior art, with the current-limiting protection circuit provided in this embodiment, when performing a set operation on the target memory cell 10, the test equipment only needs to provide the high-voltage power supply VPUMP, and the bit line high voltage required by the set operation is generated by the bit line voltage generation circuit 11. Meanwhile, the current-limiting protection circuit provided by this embodiment collects the bit line current for feedback, and controls the on and off of the switch circuit 14 through this feedback mechanism, so that the width of the high-voltage pulse required by the setting operation can be accurately controlled. Therefore, the current-limiting protection circuit provided by the embodiment can save current-limiting protection measures of the test equipment during setting operation, and simplify high-voltage signals provided by the test equipment; the current-limiting protection circuit can be integrated on a chip, so that the chip design and embedded application of the high-capacity and high-density resistive random access memory are facilitated; the width of the high voltage pulse required for the set operation can be accurately controlled.
As an alternative implementation, the bit line voltage generating circuit 11 includes an operational amplifier OP, a first resistor R1, a second resistor R2, and a first transistor M1. The non-inverting input end of the operational amplifier OP is used for receiving a reference voltage VREF, the inverting input end of the operational amplifier OP is connected with one end of the first resistor R1 and one end of the second resistor R2, the output end of the operational amplifier OP is connected with the control end of the first transistor M1, and the power supply end of the operational amplifier OP is connected with the external high-voltage power supply VPUMP. The other end of the first resistor R1 is grounded, and the other end of the second resistor R2 is connected to one end of the first transistor M1 and is used for generating the bit line voltage. The other end of the first transistor M1 is used for outputting the bit line current.
In this embodiment, the bit line voltage is generated by the operational amplifier OP through a negative feedback manner, and a corresponding bit line voltage can be obtained at a point a by adjusting the resistance of the first resistor R1, the resistance of the second resistor R2, and the voltage value of the reference voltage VREF. Further, the first transistor M1 may be an NMOS transistor, the control terminal of the first transistor M1 is the gate of the NMOS transistor, one terminal of the first transistor M1 is the source of the NMOS transistor, and the other terminal of the first transistor M1 is the drain of the NMOS transistor.
As an alternative implementation, the current sampling circuit 12 is a current mirror circuit including a second transistor M2 and a third transistor M3. One end of the second transistor M2 is connected to the control end of the second transistor M2 and the control end of the third transistor M3, and is used for receiving the bit line current, that is, connected to the other end of the first transistor M1, one end of the third transistor M3 is used for outputting the sampling current, and the other end of the second transistor M2 and the other end of the third transistor M3 are used for connecting the external high voltage power supply VPUMP.
In this embodiment, the sampling current is obtained by mirroring the bit line current through a current mirror formed by the second transistor M2 and the third transistor M3. Further, the second transistor M2 and the third transistor M3 may be PMOS transistors, one end of the second transistor M2 and one end of the third transistor M3 may be drains of the PMOS transistors, the other end of the second transistor M2 and the other end of the third transistor M3 may be sources of the PMOS transistors, and a control end of the second transistor M2 and a control end of the third transistor M3 may be gates of the PMOS transistors.
As an alternative implementation, the comparison control circuit 13 includes a comparison node B, a latch 15, and a reference current source IREF for providing the reference current. And the comparison node B is used for receiving the sampling current and comparing the sampling current with the reference current to obtain a comparison voltage. That is, the comparison node B is connected to one end of the third transistor M3 and one end of the reference current source IREF, and the other end of the reference current source IREF is grounded. The input end of the latch 15 is used for receiving the comparison voltage, and the output end of the latch 15 is used as the output end of the comparison control circuit 13. That is, the input terminal of the latch 15 is connected to the comparison node B, and the output terminal of the latch 15 is used for outputting the first control signal or the second control signal. When the sampling current is smaller than the reference current, the potential of the comparison node B is at a low level, and the latch 15 outputs the first control signal; when the sampling current is not less than the reference current, the potential of the comparison node B is at a high level, and the latch 15 outputs the second control signal and latches the second control signal. The latch 15 may be implemented as a conventional latch structure, for example, the latch 15 may include two inverters connected in series.
As an alternative implementation, the switching circuit 14 includes a fourth transistor M4. One end of the fourth transistor M4 is connected to the target memory cell 10, and taking the target memory cell 10 as a resistive memory cell as an example, one end of the fourth transistor M4 is connected to the other end of the variable resistor R0; the other terminal of the fourth transistor M4 is for receiving the bit line voltage, i.e. connected to one terminal of the first transistor M1, and the control terminal of the fourth transistor M4 is connected to the output terminal of the comparison control circuit 14, i.e. to the output terminal of the latch 15, for receiving the first control signal or the second control signal. Further, the fourth transistor M4 is a PMOS transistor, the control terminal of the fourth transistor M4 is the gate of the PMOS transistor, one terminal of the fourth transistor M4 is the drain of the PMOS transistor, and the other terminal of the fourth transistor M4 is the source of the PMOS transistor.
Based on the same inventive concept, an embodiment of the present invention further provides a memory, where the memory includes a current limiting protection circuit, and the current limiting protection circuit is the current limiting protection circuit provided in the embodiment corresponding to fig. 1.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A current limiting protection circuit for a memory, comprising:
the bit line voltage generating circuit is used for generating bit line voltage required by setting operation on a target memory cell according to voltage provided by an external high-voltage power supply and outputting bit line current when the target memory cell is set;
the current sampling circuit is used for sampling the bit line current and outputting a sampling current;
the comparison control circuit is used for comparing the sampling current with a reference current, generating a first control signal when the sampling current is smaller than the reference current, generating a second control signal when the sampling current is not smaller than the reference current, and latching the second control signal;
and the switch circuit is used for transmitting the bit line voltage to the target storage unit when receiving the first control signal and isolating the bit line voltage generation circuit and the target storage unit when receiving the second control signal.
2. The current-limiting protection circuit of claim 1, wherein the bit line voltage generating circuit comprises an operational amplifier, a first resistor, a second resistor, and a first transistor;
the non-inverting input end of the operational amplifier is used for receiving a reference voltage, the inverting input end of the operational amplifier is connected with one end of the first resistor and one end of the second resistor, the output end of the operational amplifier is connected with the control end of the first transistor, and the power supply end of the operational amplifier is connected with the external high-voltage power supply;
the other end of the first resistor is grounded, and the other end of the second resistor is connected with one end of the first transistor and used for generating the bit line voltage;
the other end of the first transistor is used for outputting the bit line current.
3. The current-limiting protection circuit of claim 2, wherein the first transistor is an NMOS transistor, the control terminal of the first transistor is a gate of the NMOS transistor, one terminal of the first transistor is a source of the NMOS transistor, and the other terminal of the first transistor is a drain of the NMOS transistor.
4. The current-limiting protection circuit of claim 1, wherein the current sampling circuit comprises a second transistor and a third transistor;
one end of the second transistor is connected with the control end of the second transistor and the control end of the third transistor and used for receiving the bit line current, one end of the third transistor is used for outputting the sampling current, and the other end of the second transistor and the other end of the third transistor are used for being connected with the external high-voltage power supply.
5. The current-limiting protection circuit of claim 4, wherein the second transistor and the third transistor are PMOS transistors, one end of the second transistor and one end of the third transistor are drains of the PMOS transistors, the other end of the second transistor and the other end of the third transistor are sources of the PMOS transistors, and a control end of the second transistor and a control end of the third transistor are gates of the PMOS transistors.
6. The current-limiting protection circuit of claim 1, wherein the comparison control circuit comprises a comparison node, a latch, and a reference current source for providing the reference current;
the comparison node is used for receiving the sampling current and comparing the sampling current with the reference current to obtain a comparison voltage;
the input end of the latch is used for receiving the comparison voltage, and the output end of the latch is used as the output end of the comparison control circuit.
7. The current-limiting protection circuit of claim 1, wherein the switching circuit comprises a fourth transistor;
one end of the fourth transistor is connected with the target storage unit, the other end of the fourth transistor is used for receiving the bit line voltage, and the control end of the fourth transistor is connected with the output end of the comparison control circuit.
8. The current-limiting protection circuit of claim 7, wherein the fourth transistor is a PMOS transistor, the control terminal of the fourth transistor is a gate of the PMOS transistor, one terminal of the fourth transistor is a drain of the PMOS transistor, and the other terminal of the fourth transistor is a source of the PMOS transistor.
9. The current-limiting protection circuit of any of claims 1 to 8, wherein the target memory cell comprises a gating transistor and a variable resistor;
the control end of the gating transistor is used for receiving word line voltage, one end of the gating transistor is used for receiving source line voltage, the other end of the gating transistor is connected with one end of the variable resistor, and the other end of the variable resistor is used for receiving bit line voltage.
10. A memory comprising the current limiting protection circuit of any one of claims 1 to 9.
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| CN202010345423.2A CN111653304B (en) | 2020-04-27 | 2020-04-27 | Memory and current-limiting protection circuit thereof |
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| CN202010345423.2A CN111653304B (en) | 2020-04-27 | 2020-04-27 | Memory and current-limiting protection circuit thereof |
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| CN111653304B CN111653304B (en) | 2022-07-08 |
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| CN110610730A (en) * | 2019-09-02 | 2019-12-24 | 上海华虹宏力半导体制造有限公司 | Sensitive amplifier |
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| CN102117644A (en) * | 2009-12-30 | 2011-07-06 | 中国科学院微电子研究所 | Readout circuit of storage |
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| US9214931B2 (en) * | 2013-03-15 | 2015-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Sensing circuit with reduced bias clamp |
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| CN111653304B (en) | 2022-07-08 |
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