CN106356090B - Phase transition storage reading circuit and its method for reading data - Google Patents
Phase transition storage reading circuit and its method for reading data Download PDFInfo
- Publication number
- CN106356090B CN106356090B CN201610744117.XA CN201610744117A CN106356090B CN 106356090 B CN106356090 B CN 106356090B CN 201610744117 A CN201610744117 A CN 201610744117A CN 106356090 B CN106356090 B CN 106356090B
- Authority
- CN
- China
- Prior art keywords
- reading
- voltage
- phase
- transition storage
- bit lines
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
- G11C2013/0042—Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB]
Landscapes
- Semiconductor Memories (AREA)
Abstract
The present invention provides a kind of phase transition storage reading circuit and its method for reading data, the phase transition storage reading circuit include at least: pre-charge voltage generation module, for presetting and generating a pre-charge voltage；Control module, for generating precharging signal after receiving external reading enable signal；Pre-charge module, it is connect respectively with this ground bit lines described in m item, the pre-charge voltage generation module and the control module, for being pre-charged according to the precharging signal, this ground bit lines described in m item are charged to the pre-charge voltage simultaneously, and after the precharging signal, stop precharge；Sense amplifier module is connect with the sense bit line, for reading the data stored in the selected phase-change memory cell after stopping precharge.The present invention can achieve relatively small random read access time, while also having taken into account the correctness read and having read nargin.
Description
Technical field
The present invention relates to technical field of integrated circuits, read more particularly to a kind of phase transition storage reading circuit and its data
Take method.
Background technique
Phase transition storage (Phase Change Memory, PCM) is to be mentioned based on Ovshinsky in late 1960s
The memory of Ao Fuxinsiji electronic effect out, its working principle is that using the phase-change material of nano-scale is worked into crystalline state
The resistance states different from when amorphous state realize the storages of data.Phase transition storage is as a kind of novel memory devices, due to it
Read or write speed is fast, erasable durability is high, keeps that information time is long, storage density is big, read-write is low in energy consumption and the spies such as non-volatile
Property, it is considered most there is one of next-generation memory of development potentiality by industry.
Phase transition storage is made using chalcogenide compound material as storage medium using the Joule heat that electric pulse or light pulse generate
Phase-change storage material between amorphous state (material be in high-impedance state) and crystalline state (material is in low resistive state) generation reversible transition and
Realize that the write-in and erasing of data, the reading of data are then realized by measuring the size of resistance.In phase transition storage, because
The overall distribution of the reasons such as the fluctuation of technological parameter and storage unit distance, crystalline resistance and amorphous state resistance is in assume just respectively
State is distributed (Assumed normal distribution).Fig. 1 is the crystalline resistance and amorphous state resistance entirety of phase transition storage
Distribution schematic diagram, wherein typical crystalline resistance value is the most crystalline resistance value of distribution, and typical amorphous state resistance value is to be distributed most
More amorphous state resistance values.Under normal circumstances, highest crystalline resistance value is lower than minimum amorphous state resistance value.
In phase transition storage, phase-change memory cell is made of memory device and gating device (Selector), such as Fig. 2 institute
Show.One end of memory device is connected with one end of gating device.Gating device is NMOS tube or diode etc..In storage unit battle array
In column, there are a plurality of wordline (Word Line, WL) and bit line (Bit Line, BL).Wordline connects one end of gating device, is used for
Control the switch of gating device.Bit line is connected to one end of memory device, for being written and read to phase-change memory cell.For
Realization is written and read phase-change memory cell respectively, and there are two types of transmission gates: reading transmission gate (Read transmission
Gate, RTG) and write transmission gate (Programming transmission gate, PTG).It accordingly will appear three bit lines: this
Ground bit lines (Local Bit Line, LBL), sense bit line (Read Bit Line, RBL) and write bit line (Global Bit Line,
GBL).Wherein this ground bit lines is connected to phase-change memory cell, reads transmission gate and writes transmission gate；Sense bit line be connected to read transmission gate and
Sense amplifier (Sense Amplifier, SA)；Write bit line, which is connected to, to be write transmission gate and writes driving circuit.
There are two types of modes for the reading circuit of phase transition storage: read current mode, by clamp circuit to phase-change memory cell
Apply certain voltage, reads the corresponding electric current for flowing through phase-change memory cell；Read voltage mode is certain to phase-change memory cell input
Electric current measures the voltage at phase-change memory cell both ends.In two kinds of reading modes, bit-line voltage when reading high value device is all higher than reading
Bit-line voltage when low resistance device.
The readout time of phase transition storage is limited by ghost effect.Bitline length refers to that the phase transformation on every bit line is deposited
Storage unit number.In reservoir designs, bitline length is generally 512 or 1024.Bitline length is bigger, and chip is more likely real
Now bigger memory capacity.But meanwhile a large amount of parasitic capacitance and dead resistance will increase the readout time of memory on bit line.
When phase transition storage is read, there are mainly three types of parasitic components: dead resistance and parasitic capacitance on metal connecting line, choosing
Logical device parasitic resistance and parasitic capacitance, transmission gate parasitic capacitance and dead resistance.Sense amplifier needs first to storage unit
Parasitic capacitance charging in array.After line in place is charged to certain voltage, electric current can just be settled out.This period can generate
Puppet reads phenomenon, greatly constrains the speed characteristics of phase transition storage.
In previous phase transition storage precharge reading technology, bit line is selected or bit line on reading transmission gate open
Afterwards, that is, enter precharge mode.After bit line is charged to pre-charge voltage, wordline is selected, and sense amplifier is started to work.
But before reading, reading address is unknown, and this period of precharge should be added read access time, this has also resulted in number
It is too long according to readout time.
Therefore, the data readout time for how improving phase transition storage is too long, has become those skilled in the art in fact urgently
The technical task of solution.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of phase transition storage reading circuits
And its method for reading data, the data readout time for solving the problems, such as phase transition storage in the prior art are too long.
In order to achieve the above objects and other related objects, the present invention provides a kind of phase transition storage reading circuit, the phase
Transition storage includes at least the memory cell array being made of m × n phase-change memory cell, connect with the phase-change memory cell
M this ground bit lines of item and n wordline, the m reading transmission gate to connect one to one with this ground bit lines described in m item, and with m institute
The sense bit line for reading transmission gate while connection is stated, the phase-change memory cell includes at least gating device and connects with the gating device
The memory device connect, wherein m, n are the natural number more than or equal to 1；Wherein, the phase transition storage reading circuit at least wraps
It includes:
Pre-charge voltage generation module, for presetting and generating a pre-charge voltage；
Control module, for generating precharging signal after receiving external reading enable signal；
Pre-charge module, respectively with this ground bit lines described in m item, the pre-charge voltage generation module and the control module
This ground bit lines described in m item are charged to the precharge electricity for being pre-charged according to the precharging signal by connection simultaneously
Pressure, and after the precharging signal, stop precharge；
Sense amplifier module is connect with the sense bit line, for reading selected phase transformation and depositing after stopping precharge
The data stored in storage unit.
Preferably, the pre-charge voltage is preset as the median of the first reference voltage and the second reference voltage.
Preferably, first reference voltage is this ground bit lines electricity when reading the memory device of highest crystalline resistance value
Pressure, second reference voltage is local bit-line voltage when reading the memory device of minimum amorphous state resistance value.
Preferably, first reference voltage is this ground bit lines electricity when reading the memory device of typical crystalline resistance value
Pressure, second reference voltage are local bit-line voltage when reading the memory device of typical amorphous state resistance value；Wherein, described
Typical crystalline resistance value is that most crystalline resistance values is distributed in the phase transition storage, and typical case's amorphous state resistance value is institute
It states and is distributed most amorphous state resistance values in phase transition storage.
Preferably, the pre-charge module includes at least: the m preliminary filling to connect one to one with this ground bit lines described in m item
Electric NMOS tube；The source electrode of the precharge NMOS tube connects described ground bit lines, and drain electrode accesses the pre-charge voltage, and grid connects
Enter the precharging signal.
Preferably, the pre-charge voltage generation module includes at least: connecting simultaneously with the m precharge NMOS tubes
Low pressure difference linear voltage regulator.
Preferably, the phase transition storage reading circuit includes at least:
Discharge module is connect with this ground bit lines described in m item, the control module respectively, in the phase transition storage
After the completion of read operation, this ground bit lines described in m item are discharged simultaneously.
Preferably, the discharge module includes at least: the m electric discharge to connect one to one with this ground bit lines described in m item
NMOS tube；The drain electrode of the electric discharge NMOS tube connects described ground bit lines, source electrode ground connection, and grid accesses discharge signal.
In order to achieve the above objects and other related objects, the present invention also provides a kind of reading data sides of phase transition storage
Method, the phase transition storage include at least the memory cell array being made of m × n phase-change memory cell, deposit with the phase transformation
M this ground bit lines of item and n wordline of storage unit connection, the m reading transmission gate to connect one to one with this ground bit lines described in m item,
And with the described sense bit lines reading transmission gates and connecting simultaneously of m, the phase-change memory cell include at least gating device and with institute
State the memory device of gating device connection, wherein m, n are the natural number more than or equal to 1；Wherein, the phase transition storage
Method for reading data includes at least:
It presets and generates a pre-charge voltage；
After receiving external reading enable signal, precharging signal is generated；
It is pre-charged according to the precharging signal, this ground bit lines described in m item is charged to the precharge electricity simultaneously
Pressure, and after the precharging signal, stop precharge；
After stopping precharge, the data stored in selected phase-change memory cell are read.
Preferably, the pre-charge voltage is preset as the median of the first reference voltage and the second reference voltage.
Preferably, first reference voltage is this ground bit lines electricity when reading the memory device of highest crystalline resistance value
Pressure, second reference voltage is local bit-line voltage when reading the memory device of minimum amorphous state resistance value.
Preferably, first reference voltage is this ground bit lines electricity when reading the memory device of typical crystalline resistance value
Pressure, second reference voltage are local bit-line voltage when reading the memory device of typical amorphous state resistance value；Wherein, described
Typical crystalline resistance value is that most crystalline resistance values is distributed in the phase transition storage, and typical case's amorphous state resistance value is institute
It states and is distributed most amorphous state resistance values in phase transition storage.
Preferably, in precharge, a minimum precharge time is preset, to ensure that this ground bit lines described in m item are filled simultaneously
Electricity arrives the pre-charge voltage.
Preferably, after stopping precharge, the data stored in selected phase-change memory cell, specific method are read
Are as follows:
One reference current is provided；
Choose a phase-change memory cell, by where the selected phase-change memory cell this ground bit lines and wordline lead
It is logical；
When the voltage in this ground bit lines where the selected phase-change memory cell reaches required bit-line voltage,
Read the read current for flowing through memory device in the selected phase-change memory cell；
The read current and the reference current are compared, comparison result is exported, as the selected phase transformation
The data stored in storage unit；
Wherein, when the memory device in the selected phase-change memory cell is crystalline state, the selected phase transformation
Voltage in this ground bit lines where storage unit directly declines from the pre-charge voltage and stablizes in required bit-line voltage；
When memory device in the selected phase-change memory cell is amorphous state, where the selected phase-change memory cell
This ground bit lines on voltage directly rise from the pre-charge voltage and stablize in required bit-line voltage.
Preferably, the method for reading data of the phase transition storage further include:
After the completion of the phase transition storage read operation, this ground bit lines described in m item are discharged simultaneously.
As described above, phase transition storage reading circuit of the invention and its method for reading data, have the advantages that
This ground bit lines is charged to pre-charge voltage by being pre-charged by the present invention, and pre-charge voltage is preset as the centre of two reference voltages
Value, i.e., so that the difference and reading crystalline resistance of bit-line voltage and pre-charge voltage when reading the memory device of amorphous state resistance value
The difference of bit-line voltage and pre-charge voltage when the memory device of value is equal, and will this before receiving reading address signal
Ground bit lines charge to pre-charge voltage in advance, so that the parasitic capacitance in this ground bit lines be made to store certain charge, are reading
When, the time charged to parasitic capacitance is shortened, therefore can achieve relatively small random read access time, while also taking into account
The correctness and reading nargin of reading.In addition, being stood after phase change memory chip is adjusted to reading mode, receives reading enable signal
Start at quarter to be pre-charged this ground bit lines, after reaching pre-charge voltage, chip can be read at random, that is to say, that wordline and
Bit line is not chosen in advance because of precharge, so this period of precharge is not added read access time, to subtract significantly
Small data readout times.
Detailed description of the invention
Fig. 1 is shown as the present invention crystalline resistance of phase transition storage and the signal of amorphous state resistance overall distribution in the prior art
Figure.
Fig. 2 is shown as the structural schematic diagram of phase transition storage in the prior art of the invention.
Fig. 3 is shown as the schematic diagram of the phase transition storage reading circuit of first embodiment of the invention.
Fig. 4 is shown as the signal of sense amplifier module in the phase transition storage reading circuit of first embodiment of the invention
Figure.
Fig. 5 is shown as the flow chart of the method for reading data of the phase transition storage of third embodiment of the invention.
Fig. 6 is shown as the timing diagram of the method for reading data of the phase transition storage of third embodiment of the invention.
The method for reading data that Fig. 7 is shown as the phase transition storage of third embodiment of the invention reads emulation when data
Result schematic diagram.
The method for reading data that Fig. 8 is shown as the phase transition storage of four embodiment of the invention reads emulation when data
Result schematic diagram.
Component label instructions
10 memory cell arrays
11 selected phase-change memory cells
20 pre-charge voltage generation modules
30 control modules
40 pre-charge modules
50 sense amplifier modules
60 discharge modules
S1~S4 step
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Fig. 3 and Fig. 4 are please referred to, first embodiment of the invention is related to a kind of phase transition storage reading circuit.It needs to illustrate
, the basic conception that only the invention is illustrated in a schematic way is illustrated provided in the present embodiment, then in diagram only display with
Related component in the present invention rather than component count when according to actual implementation, shape and size are drawn, and when actual implementation is each
Kenel, quantity and the ratio of component can arbitrarily change for one kind, and its assembly layout kenel may also be increasingly complex.
In the present embodiment, phase transition storage includes at least the storage unit battle array being made of m × n phase-change memory cell
Column 10, m this ground bit lines of the item LBL1~LBLm and n wordline WL1~WLn being connect with phase-change memory cell, with this ground bit lines of m item
M reading transmission gate RTG1~RTGm that LBL1~LBLm connects one to one, and simultaneously with m reading transmission gate RTG1~RTGm
The sense bit line RBL of connection, the memory device that phase-change memory cell includes at least gating device and connect with gating device, wherein
M, n is the natural number more than or equal to 1.The row control signal of memory cell array 10 is word-line signal WL1~WLn, and m reading passes
Control signal Y1~Ym of defeated door RTG1~RTGm controls the gating of this ground bit lines.The same time only has wordline and one at all
Ground bit lines conducting.Transmission gate RTG1~RTGm and sense amplifier module 50 are read in sense bit line RBL connection.As shown in Figure 3 and Figure 4,
In the present embodiment, phase-change memory cell includes memory device RGST1 and the first NMOS tube NM1, with the 2nd row m column phase transformation
Storage unit is as selected phase-change memory cell 11, in the selected phase-change memory cell 11, memory device RGST1 mono-
Transmission gate RTGm is read by this ground bit lines LBLm connection in end, the other end connects the drain terminal of the first NMOS tube NM1, the first NMOS tube
The grid end connection wordline WL2 of NM1, source ground connection.
Please continue to refer to Fig. 3, the phase transition storage reading circuit of present embodiment is included at least:
Pre-charge voltage generation module 20, for presetting and generating a pre-charge voltage VPC.In the present embodiment, preliminary filling
Piezoelectric voltage generation module 20 includes at least a low pressure difference linear voltage regulator, can export one by means of low pressure difference linear voltage regulator
A pre-charge voltage V lower than supply voltage VDDPC.Pre-charge voltage VPCIt is preset as the first reference voltage and the second reference voltage
Median, as shown in Figure 1, the first reference voltage be read highest crystalline resistance value memory device when this ground bit lines electricity
Pressure, the second reference voltage is local bit-line voltage when reading the memory device of minimum amorphous state resistance value.As an example,
For 180nm phase change memory chip, when supply voltage VDD is 2.5V, the first reference voltage is 280mV or so, the second reference
Voltage is 320mV or so, thus by pre-charge voltage VPCIt is set as 300mV or so.Certainly, the first reference voltage, the second reference
Voltage, and corresponding pre-charge voltage VPCIt can be set, be not limited with present embodiment according to physical circuit result.
Control module 30, for generating precharging signal PC after receiving external reading enable signal RE.In this embodiment party
In formula, control module 30 can export precharging signal PC and discharge signal in response to the external reading enable signal RE provided
PDIS。
Pre-charge module 40, respectively with m this ground bit lines of item LBL1~LBLm, pre-charge voltage generation module 20 and control mould
Block 30 connects, for according to precharging signal VPCIt is pre-charged, m this ground bit lines of item LBL1~LBLm is charged to preliminary filling simultaneously
Piezoelectric voltage VPC, and after precharging signal, stop precharge.In the present embodiment, pre-charge module includes at least: with
The m precharge NMOS tube Npc that m this ground bit lines of item LBL1~LBLm connects one to one, the leakage of m precharge NMOS tube Npc
End is connect with the low pressure difference linear voltage regulator in pre-charge voltage generation module 20, and grid end connects precharging signal PC, source
Connect this ground bit lines LBL1~LBLm.When the grid end that m is pre-charged NMOS tube Npc receives precharging signal PC, low voltage difference
M this ground bit lines of item LBL1~LBLm is charged to pre-charge voltage V by linear voltage regulatorPC.And after precharging signal PC,
It is exactly the precharging signal PC failure that control module 30 generates, that is, receives the reading address of selected phase-change memory cell 11
When signal, stop precharge, phase change memory chip can be read at random.Wherein, reading address signal includes selected
Local bit line address and wordline address where phase-change memory cell 11.
Sense amplifier module 50 is connect with sense bit line RBL, for reading selected phase transformation after stopping precharge
The data stored in storage unit 11.Please continue to refer to Fig. 4, in the present embodiment, sense amplifier module 50 is included at least:
The second NMOS tube NM2 that source is connect with selected phase-change memory cell 11, the electricity being connect with the drain terminal of the second NMOS tube NM2
Stream mirror unit, the current conversion unit being connect with reading reference voltage Vref, comparing unit and S/R latch unit.Wherein,
The grid end of two NMOS tube NM2 connects external clamp voltage Vclamp, generates under the control of external clamp voltage Vclamp selected
In phase-change memory cell 11 in read current Iread.As an example, at 2.5V supply voltage VDD, external clamper electricity
Vclamp is pressed to be arranged in 900mV or so.Certainly, external clamp voltage Vclamp can be set according to physical circuit result, not with
Present embodiment is limited.Current lens unit extracts the read current Iread in selected phase-change memory cell 11, including first
PMOS tube PM1 and the second PMOS tube PM2.Current conversion unit will read reference voltage Vref and be reduced to read reference current Iref, packet
Include the 5th PMOS tube PM5.Comparing unit is connect with current lens unit, current conversion unit respectively, by selected phase change memory
Read current Iread in unit 11 indicates selected phase-change memory cell compared with reading reference current Iref, with comparison result
The data stored in 11, including third PMOS tube PM3, the 4th PMOS tube P4, the 4th NMOS tube NM4, the 5th NMOS tube NM5,
Three NMOS tube NM3 and the 6th NMOS tube NM6；The drain terminal of third PMOS tube PM3 connects the 4th NMOS tube NM4, with the first PMOS
Pipe PM1, the second PMOS tube PM2 form current mirror, and the read current Iread of selected phase-change memory cell 11 is mirrored to third
The drain terminal of PMOS tube PM3.The drain terminal of third NMOS tube NM3 connects the drain terminal of the second PMOS tube PM2, with the 5th NMOS tube NM5 group
At current mirror, read current Iread is mirrored to the drain terminal of the 5th NMOS tube NM5.The drain terminal of 6th NMOS tube NM6 is connected to the 5th
The drain terminal of PMOS tube PM5 forms current mirror with the 4th NMOS tube NM4, will read reference current Iref and is mirrored to the 4th NMOS tube NM4
Drain terminal.4th PMOS tube PM4 and the 5th PMOS tube PM5 forms current mirror, will read reference current Iref and is mirrored to the 4th PMOS
The drain terminal of pipe PM4.The drain terminal of 4th NMOS tube NM4 is connected with the drain terminal of third PMOS tube PM3, and first as comparing unit is defeated
Outlet V1.The drain terminal of 5th NMOS tube NM5 is connected with the drain terminal of the 4th PMOS tube PM4, the second output terminal as comparing unit
V2.First output end V of comparing unit1With second output terminal V2For difference output.The end the R connection of S/R latch unit is more single
First output end V of member1, the second output terminal V of the end the S connection comparing unit of S/R latch unit2, according to S/R latch unit
Output signal DO obtain the data stored in selected phase-change memory cell 11.
When the data stored in reading selected phase-change memory cell 11, first by selected phase-change memory cell 11
This ground bit lines and wordline at place are connected, while sense amplifier module 50 is started to work.Then pass through external clamp voltage
Vclamp control sense amplifier module 50 reads the read current for flowing through memory device in selected phase-change memory cell 11, and
Read current and reference current are compared, comparison result is exported.But due to where phase-change memory cell 11 selected at this time
This ground bit lines on voltage and unstable, but from pre-charge voltage VPCStart to change, so that read current is also changing,
Therefore comparison result is inaccurate.In the local after variation after a period of time, where selected phase-change memory cell 11
Voltage on bit line tends towards stability, and read current also tends towards stability, and the comparison result exported at this time is more accurate, in this, as selected
In phase-change memory cell 11 in the data that store.It should be noted that the storage in selected phase-change memory cell 11
When device is crystalline state, the voltage in this ground bit lines where selected phase-change memory cell 11 is directly from pre-charge voltage VPCUnder
It drops and stablizes in required bit-line voltage；When memory device in selected phase-change memory cell 11 is amorphous state, it is chosen
In phase-change memory cell 11 where this ground bit lines on voltage directly from pre-charge voltage VPCRise and stablizes required
Bit-line voltage.
In addition, the phase transition storage reading circuit of present embodiment further include:
Discharge module 60 is connect with m this ground bit lines of item LBL1~LBLm, control module 30 respectively, for selected
After the completion of the reading data stored in phase-change memory cell 11, discharged simultaneously m this ground bit lines of item LBL1~LBLm.In this implementation
In mode, discharge module is included at least: the m electric discharge NMOS tube to connect one to one with m this ground bit lines of item LBL1~LBLm
Ndis；The drain terminal of m electric discharge NMOS tube Ndis connects one to one m item this ground bit lines LBL1~LBLm, and source ground connection, grid end connects
Enter discharge signal PDIS.After the completion of phase transition storage read operation, discharge module 60 is released the charge of whole road, extra
Charge by the device that can protect in memory cell array 10 of releasing.
When being read due to conventional phase change memory, sense amplifier needs first fill the parasitic capacitance on bit line
Electricity, after line in place is charged to certain voltage, read current can just be settled out.And the pre-charge module in present embodiment is by institute
There is this ground bit lines to charge to pre-charge voltage in advance, so the parasitic capacitance in this ground bit lines stores certain charge, in number
When according to reading, the time charged to parasitic capacitance is shortened, to reduce readout time.
Moreover, setting first with reference to electricity for pre-charge voltage in the pre-charge voltage generation module of present embodiment
The median of pressure and the second reference voltage, the first reference voltage are bit line electricity when reading the memory device of highest crystalline resistance value
Pressure, the second reference voltage is bit-line voltage when reading the memory device of minimum amorphous state resistance value, and when reading high value device
Bit-line voltage be higher than read low resistance device when bit-line voltage.So in reading data, if selected phase change memory list
Memory device in member is crystalline state, and bit-line voltage can decline from pre-charge voltage and (bleed off a part of charge), until stablizing；If by
The memory device in phase-change memory cell chosen is amorphous state, and bit-line voltage can rise from pre-charge voltage and (continue to charge),
Until stablizing.By setting pre-charge voltage to the median of the first reference voltage and the second reference voltage, so as to read non-
The difference of bit-line voltage and pre-charge voltage when the memory device of crystalline resistance value and when reading the memory device of crystalline resistance value
Bit-line voltage and pre-charge voltage difference it is equal, relatively small random read access time is reached with this, while also having taken into account reading
The correctness and reading nargin taken.
It is noted that each module involved in present embodiment is logic module, and in practical applications, one
A logic unit can be a physical unit, be also possible to a part of a physical unit, can also be with multiple physics lists
The combination of member is realized.In addition, in order to protrude innovative part of the invention, it will not be with solution institute of the present invention in present embodiment
The technical issues of proposition, the less close unit of relationship introduced, but this does not indicate that there is no other single in present embodiment
Member.
Second embodiment of the invention is related to a kind of phase transition storage reading circuit.Second embodiment and the first embodiment party
Formula is roughly the same, is in place of the main distinction: in the first embodiment, the first reference voltage is to read highest crystalline resistance value
Memory device when local bit-line voltage, the second reference voltage is sheet when reading the memory device of minimum amorphous state resistance value
Status line voltage.And in second embodiment of the invention, the first reference voltage is the memory for reading typical crystalline resistance value
Local bit-line voltage when part, the second reference voltage are this ground bit lines electricity when reading the memory device of typical amorphous state resistance value
Pressure.Wherein, as shown in Figure 1, typical crystalline resistance value is to be distributed most crystalline resistance values, typical amorphous state in phase transition storage
Resistance value is to be distributed most amorphous state resistance values in phase transition storage.As an example, for 180nm phase transition storage core
Piece, when supply voltage VDD is 2.5V, the first reference voltage is 40mV or so, and the second reference voltage is 380mV or so, precharge
Voltage VPCIt is arranged in 210mV or so.
Local bit-line voltage when relative in first embodiment by the memory device for reading highest crystalline resistance value is made
For the first reference voltage, the local bit-line voltage when memory device that will read minimum amorphous state resistance value is as second with reference to electricity
Pressure, due to the first reference voltage and the typical crystalline resistance value that is related to of the second reference voltage and typical amorphous in present embodiment
State resistance value is the most resistance value of distribution, the sheet where the more close most of phase-change memory cells of preset pre-charge voltage
Bit-line voltage needed for ground bit lines, therefore in reading data, pre-charge voltage can quickly be raised or lowered to required
Bit-line voltage；Relative to first embodiment, data readout time may be shorter.
Third embodiment of the invention is related to a kind of method for reading data of phase transition storage, and detailed process please refers to Fig. 5.
Wherein, phase transition storage includes at least the memory cell array being made of m × n phase-change memory cell, with phase-change memory cell
M this ground bit lines of item and n wordline of connection, the m reading transmission gate to connect one to one with m item this ground bit lines, and read with m
The sense bit line that transmission gate connects simultaneously, the memory that phase-change memory cell includes at least gating device and connect with gating device
Part, wherein m, n are the natural number more than or equal to 1.
As shown in figure 5, the method for reading data of the phase transition storage of present embodiment includes at least:
Step S1 presets and generates a pre-charge voltage.
In step sl, pre-charge voltage is preset as the median of the first reference voltage and the second reference voltage, the first ginseng
Examining voltage is local bit-line voltage when reading the memory device of highest crystalline resistance value, and the second reference voltage is that reading is minimum non-
Local bit-line voltage when the memory device of crystalline resistance value.
Step S2 generates precharging signal after receiving external reading enable signal.
Step S3, is pre-charged according to precharging signal, and m this ground bit lines of item are charged to pre-charge voltage simultaneously, and
After precharging signal, stop precharge.
In step s3, in precharge, a minimum precharge time is preset, to ensure that m this ground bit lines of item are filled simultaneously
Electricity arrives pre-charge voltage.Certainly, precharge time can set according to physical circuit result, be not limited with present embodiment.
Step S4 reads the data stored in selected phase-change memory cell after stopping precharge.
In the present embodiment, step S4 method particularly includes:
Step S41 provides a reference current.
Step S42 chooses a phase-change memory cell, by this ground bit lines and wordline where selected phase-change memory cell
Conducting.
Step S43, the voltage in this ground bit lines where selected phase-change memory cell reach required bit line electricity
When pressure, the read current for flowing through memory device in selected phase-change memory cell is read.
Step S44, read current and reference current are compared, and comparison result are exported, as selected phase change memory
The data stored in unit.
Wherein, when the memory device in selected phase-change memory cell is crystalline state, selected phase-change memory cell
Voltage in this ground bit lines at place directly declines from pre-charge voltage and stablizes in required bit-line voltage；In selected phase
When becoming the memory device in storage unit as amorphous state, the voltage in this ground bit lines where selected phase-change memory cell is straight
It connects and rises from pre-charge voltage and stablize in required bit-line voltage.
In addition, the method for reading data of the phase transition storage of present embodiment further include:
Step S5, after the completion of phase transition storage read operation, to m item, this ground bit lines is discharged simultaneously.
In step s 5, after the completion of phase transition storage read operation, and n wordline and m item this ground bit lines are not chosen
When middle, a discharge signal is generated, is released the charge of whole road according to the discharge signal.
Referring to Fig. 6, the working principle of the method for reading data of the phase transition storage of present embodiment is as follows:
In first time period T0, discharge operation is carried out.The enable signal RE that reads external at this time is low level, precharging signal PC
For low level, and the gating signal Ym of word-line signal WL2 and this ground bit lines LBLm is low level, and discharge signal PDIS is high level
VDD.This ground bit lines LBLm starts to discharge, and discharges into 0V.
In second time period T1, precharge operation is carried out.The external enable signal RE that reads is high level VDD at this time, represents phase
Transition storage chip is switched to reading mode；The gating signal Ym of word-line signal WL2 and this ground bit lines LBLm is low level, preliminary filling
Electric signal PC is high level VDD, and discharge signal PDIS is low level.This ground bit lines LBLm is charged to pre-charge voltage VPC, read
The voltage of bit line RBL is still 0V.Pre-charge voltage V is charged in this ground bit lines LBLmPCBefore, precharging signal PC will not lose
Effect.
In third period T2, read operation is carried out.The enable signal RE that reads external at this time is high level VDD, word-line signal
The gating signal Ym of WL2 and this ground bit lines LBLm is high level VDD；Precharging signal PC is low level, and discharge signal PDIS is
Low level.When the T2 stage just starts, because this ground bit lines LBLm is charged to pre-charge voltage V in T1PC, this branch road
Charge can't flow away, and the voltage on sense bit line RBL rises to pre-charge voltage V at oncePC, then pass through external clamp voltage
Vclamp reads the read current Iread of selected phase-change memory cell.At this time:
1) when selected phase-change memory cell is a crystalline state storage unit, voltage on this ground bit lines LBLm can be from
Pre-charge voltage VPCDecline, until stablizing；Iread>Iref.Third PMOS tube PM3 attempts the electric current of mirror image than the 4th NMOS tube
NM4's is big, so the first output end V1Output voltage can rise towards in supply voltage VDD；4th PMOS tube PM4 attempts
The electric current of mirror image is smaller than the 5th NMOS tube NM5's, so second output terminal V2Output voltage can drop to 0V or so.SR is latched
The output end DO of device unit exports high level.
2) the voltage meeting when selected phase-change memory cell is an amorphous state storage unit, on this ground bit lines LBLm
From pre-charge voltage VPCRise, until stablizing；Iread<Iref.Third PMOS tube PM3 attempts the electric current of mirror image than the 4th NMOS
Pipe NM4's is small, so the first output end V1Output voltage can drop to 0V or so；4th PMOS tube PM4 attempts the electricity of mirror image
Stream is bigger than the 5th NMOS tube NM5, so second output terminal V2Output voltage can rise towards in supply voltage VDD.SR
The output end DO of latch unit exports low level.
In the 4th period T3, discharge operation is carried out.The enable signal RE that reads external at this time is low level, precharging signal PC
For low level, and word-line signal WL2 and local bit line signal Ym is low level, and discharge signal PDIS is high level VDD.This status
Line LBLm starts to discharge, and discharges into 0V.
When reading 1Kbit phase change memory chip data using the method for reading data of the phase transition storage of present embodiment
Simulation result it is as shown in Figure 7.The chip uses 180nm technique, and supply voltage VDD is 2.5V, and local bitline length is 1024.
Wherein, EN signal is enable signal, and with the raising of EN signal voltage, word-line signal and local bit line signal rise to height simultaneously
Level starts to read data.When reading low-resistance (crystalline state), read access time 6.27ns；When reading high resistant (amorphous state), read
The time is taken to be less than 0.5ns.Therefore, use the random read access time of the method for reading data of the phase transition storage of present embodiment for
6.27ns.In contrast, using the 1Kbit phase change memory chip readout time of traditional reading method in 70ns or so.Thus
As it can be seen that the method for reading data of the phase transition storage using present embodiment, substantially reduces data read time.
The step of various methods divide above, be intended merely to describe it is clear, when realization can be merged into a step or
Certain steps are split, multiple steps are decomposed into, as long as comprising identical logical relation, all in the protection scope of this patent
It is interior；To adding inessential modification in algorithm or in process or introducing inessential design, but its algorithm is not changed
Core design with process is all in the protection scope of the patent.
It is not difficult to find that present embodiment is embodiment of the method corresponding with first embodiment, present embodiment can be with
First embodiment is worked in coordination implementation.The relevant technical details mentioned in first embodiment still have in the present embodiment
Effect, in order to reduce repetition, which is not described herein again.Correspondingly, the relevant technical details mentioned in present embodiment are also applicable in
In first embodiment.
Four embodiment of the invention is related to a kind of method for reading data of phase transition storage.4th embodiment and third
Embodiment is roughly the same, is in place of the main distinction: in the third embodiment, the first reference voltage is to read highest crystalline state
Local bit-line voltage when the memory device of resistance value, the second reference voltage are the memory device for reading minimum amorphous state resistance value
When local bit-line voltage.And in four embodiment of the invention, the first reference voltage is to read typical crystalline resistance value
Local bit-line voltage when memory device, the second reference voltage are local when reading the memory device of typical amorphous state resistance value
Bit-line voltage；Wherein, typical crystalline resistance value is to be distributed most crystalline resistance values, typical amorphous state resistance in phase transition storage
Value is to be distributed most amorphous state resistance values in phase transition storage.
When reading 1Kbit phase change memory chip data using the method for reading data of the phase transition storage of present embodiment
Simulation result it is as shown in Figure 8.The chip uses 180nm technique, and supply voltage VDD is 2.5V, and local bitline length is 1024.
Wherein, EN signal is enable signal, and with the raising of EN signal voltage, word-line signal and local bit line signal rise to height simultaneously
Level starts to read data.When reading low-resistance (crystalline state), read access time 4.78ns；When reading high resistant (amorphous state), read
The time is taken to be less than 0.5ns.Therefore, use the random read access time of the method for reading data of the phase transition storage of present embodiment for
4.78ns.In contrast, using the 1Kbit phase change memory chip readout time of traditional reading method in 70ns or so.Thus
As it can be seen that the method for reading data of the phase transition storage using present embodiment, substantially reduces data read time.
Since second embodiment is corresponded to each other with present embodiment, present embodiment can be mutual with second embodiment
Match implementation.The relevant technical details mentioned in second embodiment are still effective in the present embodiment, implement second
The attainable technical effect of institute similarly may be implemented in the present embodiment in mode, no longer superfluous here in order to reduce repetition
It states.Correspondingly, the relevant technical details mentioned in present embodiment are also applicable in second embodiment.
In conclusion this ground bit lines is charged to pre-charge voltage by being pre-charged by the present invention, pre-charge voltage is preset as
The median of two reference voltages, i.e., so that read amorphous state resistance value memory device when bit-line voltage and pre-charge voltage
Difference and the difference of bit-line voltage and pre-charge voltage when reading the memory device of crystalline resistance value it is equal, and receiving reading
Before address signal will this ground bit lines charge to pre-charge voltage in advance, so that the parasitic capacitance in this ground bit lines be made to store
Certain charge shortens the time charged to parasitic capacitance, therefore can achieve relatively small random reading at the time of reading
Time, while also having taken into account the correctness read and having read nargin.In addition, when phase change memory chip is adjusted to reading mode, i.e. reception
To after reading enable signal, gets started and this ground bit lines is pre-charged, after reaching pre-charge voltage, chip can random write
It takes, that is to say, that wordline and bit line are not chosen in advance because of precharge, so this period of precharge is not added reading
The time is taken, to substantially reduce data readout time.So the present invention effectively overcome various shortcoming in the prior art and
Has high industrial utilization value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (9)
1. a kind of phase transition storage reading circuit, the phase transition storage is included at least to be made of m × n phase-change memory cell
Memory cell array, m this ground bit lines of item and n wordline being connect with the phase-change memory cell, with this ground bit lines one described in m item
One m reading transmission gate being correspondingly connected with, and the sense bit lines being connect simultaneously with the m reading transmission gates, the phase change memory list
The memory device that member includes at least gating device and connect with the gating device, wherein m, n are the nature more than or equal to 1
Number；It is characterized in that, the phase transition storage reading circuit includes at least:
Pre-charge voltage generation module, for presetting and generating a pre-charge voltage；
Control module, for generating precharging signal after receiving external reading enable signal；
Pre-charge module connects with this ground bit lines described in m item, the pre-charge voltage generation module and the control module respectively
It connects, for being pre-charged according to the precharging signal, this ground bit lines described in m item is charged to the precharge electricity simultaneously
Pressure, and after the precharging signal, stop precharge；
Sense amplifier module is connect with the sense bit line, for reading selected phase change memory list after stopping precharge
The data stored in member；
Wherein the numerical value of the pre-charge voltage is preset as the first reference voltage and the second reference voltage numerical coordinates intermediate point
Numerical value；Local bit-line voltage when first reference voltage is the memory device of reading highest crystalline resistance value, described second
Reference voltage is local bit-line voltage when reading the memory device of minimum amorphous state resistance value；Or first reference voltage
Local bit-line voltage when memory device to read typical crystalline resistance value, second reference voltage is to read typical amorphous
Local bit-line voltage when the memory device of state resistance value, typical case's crystalline resistance value is to be distributed most in the phase transition storage
More crystalline resistance values, typical case's amorphous state resistance value are to be distributed most amorphous state resistance values in the phase transition storage.
2. phase transition storage reading circuit according to claim 1, which is characterized in that the pre-charge module at least wraps
It includes: the m precharge NMOS tube to connect one to one with this ground bit lines described in m item；The source electrode connection of the precharge NMOS tube
Described ground bit lines, drain electrode access the pre-charge voltage, and grid accesses the precharging signal.
3. phase transition storage reading circuit according to claim 2, which is characterized in that the pre-charge voltage generation module
It includes at least: the low pressure difference linear voltage regulator being connect simultaneously with the m precharge NMOS tubes.
4. phase transition storage reading circuit according to claim 1, which is characterized in that the phase transition storage reading circuit
Further include:
Discharge module is connect with this ground bit lines described in m item, the control module respectively, for reading in the phase transition storage
After the completion of operation, this ground bit lines described in m item are discharged simultaneously.
5. phase transition storage reading circuit according to claim 4, which is characterized in that the discharge module includes at least:
The m electric discharge NMOS tube to connect one to one with this ground bit lines described in m item；The drain electrode of the electric discharge NMOS tube connects the local
Bit line, source electrode ground connection, grid access discharge signal.
6. a kind of method for reading data of phase transition storage, the phase transition storage is included at least by m × n phase-change memory cell
The memory cell array of composition, m this ground bit lines of item and n wordline being connect with the phase-change memory cell, with local described in m item
The m reading transmission gate that bit line connects one to one, and the sense bit lines being connect simultaneously with the m reading transmission gates, the phase transformation
The memory device that storage unit includes at least gating device and connect with the gating device, wherein m, n are more than or equal to 1
Natural number；It is characterized in that, the method for reading data of the phase transition storage includes at least:
It presets and generates a pre-charge voltage；
After receiving external reading enable signal, precharging signal is generated；
It is pre-charged according to the precharging signal, this ground bit lines described in m item is charged to the pre-charge voltage simultaneously, and
After the precharging signal, stop precharge；
After stopping precharge, the data stored in selected phase-change memory cell are read；
Wherein the numerical value of the pre-charge voltage is preset as the first reference voltage and the second reference voltage numerical coordinates intermediate point
Numerical value；Local bit-line voltage when first reference voltage is the memory device of reading highest crystalline resistance value, described second
Reference voltage is local bit-line voltage when reading the memory device of minimum amorphous state resistance value；Or first reference voltage
Local bit-line voltage when memory device to read typical crystalline resistance value, second reference voltage is to read typical amorphous
Local bit-line voltage when the memory device of state resistance value, typical case's crystalline resistance value is to be distributed most in the phase transition storage
More crystalline resistance values, typical case's amorphous state resistance value are to be distributed most amorphous state resistance values in the phase transition storage.
7. the method for reading data of phase transition storage according to claim 6, which is characterized in that in precharge, preset
One minimum precharge time, to ensure this ground bit lines described in m item while be charged to the pre-charge voltage.
8. the method for reading data of phase transition storage according to claim 6, which is characterized in that after stopping precharge,
The data stored in selected phase-change memory cell are read, method particularly includes:
One reference current is provided；
A phase-change memory cell is chosen, by this ground bit lines and wordline conducting where the selected phase-change memory cell；
When the voltage in this ground bit lines where the selected phase-change memory cell reaches required bit-line voltage, read
Flow through the read current of memory device in the selected phase-change memory cell；
The read current and the reference current are compared, comparison result is exported, as the selected phase change memory
The data stored in unit；
Wherein, when the memory device in the selected phase-change memory cell is crystalline state, the selected phase change memory
Voltage in this ground bit lines where unit directly declines from the pre-charge voltage and stablizes in required bit-line voltage；Institute
When to state memory device in selected phase-change memory cell be amorphous state, the sheet where the selected phase-change memory cell
Voltage in ground bit lines directly rises from the pre-charge voltage and stablizes in required bit-line voltage.
9. the method for reading data of phase transition storage according to claim 6, which is characterized in that the phase transition storage
Method for reading data further include:
After the completion of the phase transition storage read operation, this ground bit lines described in m item are discharged simultaneously.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610744117.XA CN106356090B (en) | 2016-08-26 | 2016-08-26 | Phase transition storage reading circuit and its method for reading data |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610744117.XA CN106356090B (en) | 2016-08-26 | 2016-08-26 | Phase transition storage reading circuit and its method for reading data |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106356090A CN106356090A (en) | 2017-01-25 |
| CN106356090B true CN106356090B (en) | 2019-02-01 |
Family
ID=57855214
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610744117.XA Active CN106356090B (en) | 2016-08-26 | 2016-08-26 | Phase transition storage reading circuit and its method for reading data |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106356090B (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106898371B (en) * | 2017-02-24 | 2020-08-28 | 中国科学院上海微系统与信息技术研究所 | Three-dimensional memory reading circuit and word line and bit line voltage configuration method thereof |
| CN107507640A (en) * | 2017-09-05 | 2017-12-22 | 珠海泓芯科技有限公司 | Memory reading circuitry |
| CN108665925B (en) * | 2018-04-25 | 2020-08-04 | 华中科技大学 | Read-write method and system based on multi-level storage type phase change memory |
| KR102480012B1 (en) | 2018-06-12 | 2022-12-21 | 삼성전자 주식회사 | Memory device for compensating current of off cells and operating method thereof |
| CN109903801B (en) * | 2019-03-19 | 2021-04-02 | 中国科学院上海微系统与信息技术研究所 | Data reading circuit and method of phase change memory |
| CN110164497B (en) * | 2019-06-26 | 2023-12-29 | 中国科学院上海微系统与信息技术研究所 | Nonvolatile memory sense amplifier and phase change memory |
| CN110289037B (en) * | 2019-06-26 | 2021-04-13 | 中国科学院上海微系统与信息技术研究所 | Nonvolatile memory read circuit and read method |
| CN110335636B (en) * | 2019-07-05 | 2021-04-02 | 中国科学院上海微系统与信息技术研究所 | Multi-level storage read-write method and system of phase change memory |
| CN112216333B (en) * | 2020-09-30 | 2024-02-06 | 深圳市宏旺微电子有限公司 | Chip testing method and device |
| CN112614525B (en) * | 2020-12-16 | 2023-12-29 | 中国科学院上海微系统与信息技术研究所 | Low-power-consumption phase change memory write driving circuit capable of improving resistance consistency |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070103972A1 (en) * | 2005-11-07 | 2007-05-10 | Yu-Hwan Ro | Non-volatile phase-change memory device and method of reading the same |
| CN1975927A (en) * | 2005-11-30 | 2007-06-06 | 三星电子株式会社 | Phase-changeable memory device and read method thereof |
| CN101976578A (en) * | 2010-10-09 | 2011-02-16 | 中国科学院上海微系统与信息技术研究所 | Data readout circuit and readout method of phase-change storage unit |
| CN102820055A (en) * | 2011-06-07 | 2012-12-12 | 中国科学院上海微系统与信息技术研究所 | Data readout circuit for phase change memorizer |
| CN102820056A (en) * | 2011-06-07 | 2012-12-12 | 中国科学院上海微系统与信息技术研究所 | Data readout circuit for phase change memorizer |
| CN103646668A (en) * | 2013-12-26 | 2014-03-19 | 中国科学院上海微系统与信息技术研究所 | Disposable programmable memory as well as programming method and reading method of memory |
| US20140241070A1 (en) * | 2013-02-26 | 2014-08-28 | Macronix International Co., Ltd. | Reference and sensing with bit line stepping method of memory |
| US9036408B1 (en) * | 2012-08-28 | 2015-05-19 | Being Advanced Memory Corporation | Phase change memory with bit line matching |
-
2016
- 2016-08-26 CN CN201610744117.XA patent/CN106356090B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070103972A1 (en) * | 2005-11-07 | 2007-05-10 | Yu-Hwan Ro | Non-volatile phase-change memory device and method of reading the same |
| CN1975927A (en) * | 2005-11-30 | 2007-06-06 | 三星电子株式会社 | Phase-changeable memory device and read method thereof |
| CN101976578A (en) * | 2010-10-09 | 2011-02-16 | 中国科学院上海微系统与信息技术研究所 | Data readout circuit and readout method of phase-change storage unit |
| CN102820055A (en) * | 2011-06-07 | 2012-12-12 | 中国科学院上海微系统与信息技术研究所 | Data readout circuit for phase change memorizer |
| CN102820056A (en) * | 2011-06-07 | 2012-12-12 | 中国科学院上海微系统与信息技术研究所 | Data readout circuit for phase change memorizer |
| US9036408B1 (en) * | 2012-08-28 | 2015-05-19 | Being Advanced Memory Corporation | Phase change memory with bit line matching |
| US20140241070A1 (en) * | 2013-02-26 | 2014-08-28 | Macronix International Co., Ltd. | Reference and sensing with bit line stepping method of memory |
| CN103646668A (en) * | 2013-12-26 | 2014-03-19 | 中国科学院上海微系统与信息技术研究所 | Disposable programmable memory as well as programming method and reading method of memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106356090A (en) | 2017-01-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106356090B (en) | Phase transition storage reading circuit and its method for reading data | |
| CN105304114B (en) | The method of storage device and operation storage system | |
| JP5614150B2 (en) | Resistance change memory device | |
| CN106205684B (en) | A kind of phase transition storage reading circuit and reading method | |
| CN101976578B (en) | Data readout circuit and readout method of phase-change storage unit | |
| KR102159258B1 (en) | Memory Device and Methods of Operating the Memory Device | |
| CN101828234B (en) | Information processing system | |
| US8391047B2 (en) | Method of executing a forming operation to variable resistance element | |
| CN106875963B (en) | A kind of three-dimensional storage reading circuit and reading method | |
| CN103050148B (en) | Resistance-change memory device, layout structure and its sensing circuit | |
| CN103310837B (en) | Semiconductor memory and memory cell voltage application method | |
| KR102514045B1 (en) | Resistive Memory device and Memory system including thereof | |
| CN102057440B (en) | There is the nand flash memory of integrated bit line capacitance | |
| CN107093452A (en) | Method including writing the SRAM of auxiliary circuit and operating the SRAM | |
| KR20050015293A (en) | Memory cell access circuit of semiconductor memory device | |
| CN104756192A (en) | Memory array with power-efficient read architecture | |
| JP2010182353A (en) | Semiconductor memory device and reading method therefor | |
| CN106898371B (en) | Three-dimensional memory reading circuit and word line and bit line voltage configuration method thereof | |
| US8238138B2 (en) | Semiconductor memory device and its operation method | |
| JP2010080041A (en) | Semiconductor storage apparatus | |
| CN111554342B (en) | Nonvolatile memory device and erasing method of nonvolatile memory device | |
| CN105931665A (en) | Readout circuit and method for phase change memory | |
| CN108877854A (en) | Storage device and its operating method | |
| CN105869670B (en) | Resistive random access memory | |
| CN110289037B (en) | Nonvolatile memory read circuit and read method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |