CN110164497B - Nonvolatile memory sense amplifier and phase change memory - Google Patents
Nonvolatile memory sense amplifier and phase change memory Download PDFInfo
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- CN110164497B CN110164497B CN201910561379.6A CN201910561379A CN110164497B CN 110164497 B CN110164497 B CN 110164497B CN 201910561379 A CN201910561379 A CN 201910561379A CN 110164497 B CN110164497 B CN 110164497B
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- 239000000463 material Substances 0.000 description 4
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- 150000004770 chalcogenides Chemical class 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
Abstract
The invention provides a nonvolatile memory sense amplifier and a phase change memory, comprising: the control module generates a first control signal and a second control signal; the low-power consumption module is used for closing the comparison module when the external enabling signal fails; the first reading voltage module reads the reading current of the selected memory cell when the external enabling signal is enabled and converts the reading current into a first reading voltage; the comparison module receives the first reading reference voltage, and compares the first reading voltage with the first reading reference voltage when the external enabling signal is enabled to obtain a reading voltage signal; the low-power consumption matching module is connected with the parasitic matching module and is used for carrying out voltage matching on the low-power consumption module so as to offset the parasitic effect of the transistor grid electrode in the comparison module. The topology structure and the size of the low-power-consumption matching module are the same as those of the low-power-consumption module, and the source and drain voltages of transistors in the parasitic matching module are the same as those in the comparison module, so that the charging time of parasitic capacitance is the same, and the reading speed is improved.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to a sense amplifier and a phase change memory for a nonvolatile memory.
Background
In the field of integrated circuit fabrication, conventional charge class memories are increasingly limited as process nodes continue to shrink. Various novel memories and novel structures were invented to break through the original limits: MLC NAND, MLC NOR, TLC NAND, MRAM, RRAM, feRAM,3D-Xpoint,3D-NAND, etc. The conventional and new memory read latency are different: as the SRAM of the memory, the reading time of the DRAM is within 10ns, the NAND Flash is about 50us, the 3D-NAND is about 500us, and the hard disk is about 10 ms. If the read time of the memory can be further mined, its competitiveness will be greatly improved.
The phase change memory (Phase Change Memory, PCM) is a memory based on the oshansky electronic effect proposed by Ovshinsky at the end of the 60 s of the 20 th century, and the working principle is to realize data storage by utilizing different resistance states of the phase change material processed to nano-size in crystalline and amorphous states. The phase change memory is regarded as a new type memory, and is one of the most potential memories of the next generation because of its characteristics of fast read/write speed, high erasable durability, long information holding time, high storage density, low read/write power consumption, non-volatility, etc.
The phase change memory takes a chalcogenide material as a storage medium, utilizes joule heat generated by electric pulse or optical pulse to enable the phase change memory material to generate reversible phase change between an amorphous state (the material is in a high-resistance state) and a crystalline state (the material is in a low-resistance state) so as to realize writing and erasing of data, and reads the data by measuring the size of a resistor.
The read operation of the nonvolatile memory is performed by measuring the resistance value of the selected memory cell. A preset voltage or current is applied to the selected memory cell while the current or voltage across the memory cell is read; and comparing the read current or voltage with a reference current or voltage to determine the phase state of the memory cell. The sense amplifier serves as an important module of the sense circuit for generating the sense current and comparing the sense current with the read reference current. The reading speed and the power consumption are two important assessment indexes of the reading circuit.
When the memory array is larger than a certain scale, parasitic effects in the array can cause the read current to change drastically after the read operation starts, which tends to slow down the read speed of the chip. The reference signals of a plurality of sense amplifiers in the array of the traditional technical scheme are controlled by the same read reference voltage generating circuit, and when one of the sense amplifiers starts to work, the sense amplifier which does not work is not completely closed because of the comparison module and the current conversion module, so that serious electric leakage is generated. However, completely turning off the comparison module and the current conversion module requires adding additional transistors to the current branch, which in turn has several negative effects: 1. when the read current and the reference current have a large difference, the comparison module needs to generate two voltage comparison signals with opposite voltages (i.e. logic 0 and logic 1) quickly, and the generation time is limited by the parasitic capacitance of the transistor, and the parasitic capacitance is further increased by the additional transistor, so that the reading speed is reduced. 2. The additional transistor breaks through the established parasitic capacitance balance, and the source and drain voltages of the transistor in the parasitic matching module are different from those in the comparison module, so that the parasitic capacitance is charged for different time, and the reading speed is reduced.
Therefore, how to improve the readout time and the readout power consumption of the current phase change memory, and develop corresponding circuit technology has become a technical problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a sense amplifier and a phase change memory for a nonvolatile memory, which are used for solving the problems of overlong readout time and overlarge readout power consumption of the phase change memory in the prior art.
To achieve the above and other related objects, the present invention provides a nonvolatile memory sense amplifier including at least:
the device comprises a control module, a low-power consumption module, a first read voltage module, a comparison module, a low-power consumption matching module and a parasitic matching module;
the control module receives an external enabling signal, generates a first control signal and a second control signal based on the external enabling signal, and respectively controls the working states of the low-power-consumption module and the first reading voltage module;
the low-power consumption module is connected with the control module and the comparison module and is used for closing the comparison module when the external enabling signal fails;
the first reading voltage module is connected with the control module and the storage array and is used for reading the reading current of a selected storage unit in the storage array when the external enabling signal is enabled and converting the reading current into a first reading voltage;
the comparison module is connected with the first reading voltage module and the low power consumption module and receives a first reading reference voltage, and is used for comparing the first reading voltage with the first reading reference voltage when the external enabling signal is enabled to obtain a reading voltage signal;
the low-power-consumption matching module is connected with the parasitic matching module, the low-power-consumption matching module is used for carrying out voltage matching on the low-power-consumption module, and the parasitic matching module is used for counteracting the parasitic effect of the transistor grid electrode in the comparison module.
Optionally, the control module includes a first inverter and a second inverter; the input end of the first inverter receives the external enabling signal and outputs a first control signal; the input end of the second inverter is connected with the output end of the first inverter, and outputs a second control signal.
Optionally, the low-power consumption module includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor; the sources of the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube are connected with power supply voltage, the grid is connected with the first control signal, and the drains are respectively connected with the comparison module; the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube have the same size.
More optionally, the low-power matching module includes a fifth PMOS transistor, a source of the fifth PMOS transistor is connected to a power supply voltage, a gate of the fifth PMOS transistor is connected to the first control signal, a drain of the fifth PMOS transistor is connected to the parasitic matching module, and dimensions of the fifth PMOS transistor are the same as those of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor.
Optionally, the first read voltage module includes a transmission gate, a first NMOS transistor, and a sixth PMOS transistor; the input end of the transmission gate is connected with the clamping voltage, and the control end of the transmission gate is connected with the second control signal; the source electrode of the first NMOS tube is connected with the storage array, the grid electrode of the first NMOS tube is connected with the output end of the transmission gate, and the drain electrode of the first NMOS tube is connected with the drain electrode of the sixth PMOS tube; and the source electrode of the sixth PMOS tube is connected with a power supply voltage, and the grid electrode of the sixth PMOS tube is connected with the drain electrode and outputs the first reading voltage.
Optionally, the comparison module includes a first current conversion module, a second current conversion module, and a comparator; the first current conversion module is connected with the low-power consumption module and the first reading voltage, and converts the first reading voltage into a second reading voltage when the external enabling signal is enabled; the second current conversion module is connected with the low-power consumption module and the first reading reference voltage, and converts the first reading reference voltage into a second reading reference voltage when the external enabling signal is enabled; the comparator is connected with the low-power consumption module, the first current conversion module and the second current conversion module, and compares the first reading voltage with the first reading reference voltage and the second reading voltage with the second reading reference voltage to obtain a reading voltage signal when the external enabling signal is enabled; the first current conversion module and the second current conversion module are converted in equal proportion.
More optionally, the first current conversion module includes a seventh PMOS transistor and a second NMOS transistor; the source electrode of the seventh PMOS tube is connected with the low-power consumption module, the grid electrode of the seventh PMOS tube is connected with the first reading voltage, and the drain electrode of the seventh PMOS tube is connected with the drain electrode of the second NMOS tube; the grid electrode of the second NMOS tube is connected with the drain electrode and outputs the second reading voltage, and the source electrode of the second NMOS tube is grounded; the second current conversion module comprises an eighth PMOS tube and a third NMOS tube; the source electrode of the eighth PMOS tube is connected with the low-power consumption module, the grid electrode of the eighth PMOS tube is connected with the first reading reference voltage, and the drain electrode of the eighth PMOS tube is connected with the drain electrode of the third NMOS tube; the grid electrode of the third NMOS tube is connected with the drain electrode and outputs the second reading reference voltage, and the source electrode of the third NMOS tube is grounded; the comparator comprises a ninth PMOS tube, a tenth PMOS tube, a fourth NMOS tube and a fifth NMOS tube; the source electrode of the ninth PMOS tube is connected with the low-power consumption module, the grid electrode of the ninth PMOS tube is connected with the first reading voltage, and the drain electrode of the ninth PMOS tube is connected with the drain electrode of the fourth NMOS tube; the grid electrode of the fourth NMOS tube is connected with the second reading reference voltage, and the source electrode of the fourth NMOS tube is grounded; the source electrode of the tenth PMOS tube is connected with the low-power consumption module, the grid electrode of the tenth PMOS tube is connected with the first reading reference voltage, and the drain electrode of the tenth PMOS tube is connected with the drain electrode of the fifth NMOS tube; and the grid electrode of the fifth NMOS tube is connected with the second reading voltage, and the source electrode is grounded.
More optionally, the ninth PMOS transistor and the tenth PMOS transistor have the same size.
More optionally, the parasitic matching module includes 2 (b-1) eleventh PMOS transistors and a sixth NMOS transistor connected in parallel, where a source of the eleventh PMOS transistor is connected to the low power consumption matching module, a gate of the eleventh PMOS transistor is connected to the first read voltage, and a drain of the eleventh PMOS transistor is connected to the sixth NMOS transistor; the grid electrode and the source electrode of the sixth NMOS tube are grounded; the eleventh PMOS tube, the ninth PMOS tube and the tenth PMOS tube have the same size, and b is the number of nonvolatile memory sense amplifiers connected to the same read reference voltage production circuit.
To achieve the above and other related objects, the present invention provides a phase change memory comprising at least:
a read reference voltage generation circuit and a phase change memory cell array;
the read reference voltage generation circuit is connected with the phase change memory cell array and provides a first read reference voltage for the phase change memory cell array;
the phase-change memory cell array comprises at least one phase-change memory cell module and the nonvolatile memory sense amplifier which is in one-to-one correspondence with the phase-change memory cell module, and each bit line in the phase-change memory cell module is connected with the nonvolatile memory sense amplifier through a read transmission gate.
As described above, the nonvolatile memory sense amplifier and the phase change memory of the invention have the following beneficial effects:
the nonvolatile memory sense amplifier and the low-power-consumption module of the phase change memory can completely turn off the sense amplifier when the enabling signal is in a low level, and have low reading power consumption.
The topology structure and the size of the low-power-consumption matching module of the nonvolatile memory sense amplifier and the phase-change memory are the same as those of the low-power-consumption module, and the source and drain voltages of transistors in the parasitic matching module are the same as those in the comparison module, so that the charging time of parasitic capacitance is the same, and the reading speed is improved.
Drawings
Fig. 1 is a schematic diagram showing the structure of a sense amplifier of a nonvolatile memory according to the present invention.
Fig. 2 is a schematic diagram showing the structure of a phase change memory according to the present invention.
FIG. 3 is a graph showing the comparison of the simulation results of power consumption of the sense amplifier for a nonvolatile memory according to the present invention and the prior art sense amplifier applied to a phase change memory.
Fig. 4 shows the result of the simulation of the read time of the sense amplifier in the prior art.
FIG. 5 shows the simulation results of the read time of the sense amplifier of the nonvolatile memory according to the present invention.
Description of element reference numerals
1. Nonvolatile memory sense amplifier
11. Control module
12. Low power consumption module
13. First read voltage module
14. Comparison module
141. First current conversion module
142. Second current conversion module
143. Comparator with a comparator circuit
15. Low-power consumption matching module
16. Parasitic matching module
17. Latch device
2. Read reference voltage generation circuit
3. Phase change memory cell array
4. Phase change memory cell module
41. Selected memory cell
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1-5. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
As shown in fig. 1, the present embodiment provides a nonvolatile memory sense amplifier 1, the nonvolatile memory sense amplifier 1 including:
control module 11, low power consumption module 12, first read voltage module 13, comparison module 14, low power consumption matching module 15, and parasitic matching module 16.
As shown in fig. 1, the control module 11 receives an external enable signal EN, and generates a first control signal and a second control signal based on the external enable signal EN to control the operating states of the low power consumption module 12 and the first read voltage module 13, respectively.
Specifically, in the present embodiment, the control module 11 includes a first inverter INV1 and a second inverter INV2. An input end of the first inverter INV1 receives the external enable signal EN and outputs a first control signal; the input end of the second inverter INV2 is connected to the output end of the first inverter INV1, and outputs a second control signal. When the external enable signal EN is active, the first control signal controls the low power consumption module 12 to be inactive (i.e., the nonvolatile memory sense amplifier 1 is not in a low power consumption state); the first read voltage module 13 receives the clamp voltage Vclamp, and the first read voltage module 13 operates. When the external enable signal EN is disabled, the first control signal controls the low power consumption module 12 to operate (i.e., the nonvolatile memory sense amplifier 1 is in a low power consumption state), and the second control signal controls the first read voltage module 13 to not operate. In this embodiment, when the external enable signal EN is at a high level, the first control signal is at a low level. In practical use, the structure of the control module 11 and the level of the first control signal can be set according to the needs, which is not limited to the present embodiment.
As shown in fig. 1, the low power consumption module 12 is connected to the control module 11 and the comparison module 14, and is configured to turn off the comparison module 14 when the external enable signal EN fails.
Specifically, the low power consumption module 12 receives the first control signal, and when the external enable signal EN fails (in this embodiment, the external enable signal EN fails to be at a low level), the first control signal controls the low power consumption module 12 to turn off the comparison module 14, the comparison module 14 has no leakage, the nonvolatile memory sense amplifier 1 is in a low power consumption state, and the shutdown power consumption and the read power consumption are greatly reduced. In this embodiment, the low power consumption module 12 includes a first PMOS pipe PM1, a second PMOS pipe PM2, a third PMOS pipe PM3, and a fourth PMOS pipe PM4; the sources of the first PMOS PM1, the second PMOS PM2, the third PMOS PM3 and the fourth PMOS PM4 are connected to the power supply voltage VDD, the gates are connected to the first control signal, and the drains are respectively connected to the comparison module 14. When the first control signal is at a high level, the first PMOS PM1, the second PMOS PM2, the third PMOS PM3, and the fourth PMOS PM4 are all turned off, no power is supplied to the comparison module 14, and the comparison module 14 does not operate; when the first control signal is at a low level, the first PMOS PM1, the second PMOS PM2, the third PMOS PM3, and the fourth PMOS PM4 are all turned on, the power supply voltage VDD supplies power to the comparison module 14 via the low power consumption module 12, and the comparison module 14 works. In this embodiment, the first PMOS pipe PM1, the second PMOS pipe PM2, the third PMOS pipe PM3, and the fourth PMOS pipe PM4 have the same size.
It should be noted that the structure of the low power consumption module 12 may be adaptively modified according to the specific structure of the comparison module 14, which is not limited to the embodiment.
As shown in fig. 1, the first read voltage module 13 is connected to the control module 11 and the memory array, and is configured to read the read current Iread of the selected memory cell in the memory array and convert the read current Iread into a first read voltage Vread1 when the external enable signal EN is activated.
Specifically, in the present embodiment, the first read voltage module 13 includes a transmission gate TG, a first NMOS transistor NM1, and a sixth PMOS transistor PM6. The input end of the transmission gate TG is connected to the clamp voltage Vclamp, the control end receives the second control signal, and the output end is connected to the first NMOS NM1. The source of the first NMOS transistor NM1 is connected to a read bit line RBL in the memory array (in this embodiment, the selected memory cell in the memory array comprises a switching transistor NM7 and a phase-change resistor R connected in series GST ) The gate of the first NMOS transistor NM1 is connected to the output end of the transmission gate TG, and the drain of the first NMOS transistor NM1 is connected to the drain of the sixth PMOS transistor PM6. The sixth PMOS PM6 is configured as a current mirror structure, with a source connected to the power voltage VDD, and a gate connected to a drain and outputting the first read voltage Vread1. When the external enable signal EN is asserted, the second control signal controls the transmission gate TG to be turned on, the clamp voltage Vclamp acts on the gate of the first NMOS transistor NM1, the read current Iread is smaller than the write current and the erase current, and the clamp voltage Vclamp controls the first NMOS transistor NM1 to make the bit line voltage smaller than the amorphous threshold voltage of the memory device.
As shown in fig. 1, the comparing module 14 is connected to the first read voltage module 13 and the low power consumption module 12, and receives a first read reference voltage Vref1 for comparing the first read voltage Vread1 with the first read reference voltage Vref1 when the external enable signal EN is active, so as to obtain a read voltage signal, wherein the first read reference voltage Vref1 is provided by a read reference voltage generating circuit (not shown in fig. 1).
Specifically, in the present embodiment, the comparing module 14 includes a first current converting module 141, a second current converting module 142, and a comparator 143. The first current conversion module 141 is connected to the low power consumption module 12 and the first read voltage Vread1, and converts the first read voltage Vread1 into a second read voltage Vread2 when the external enable signal EN is activated. The second current conversion module 142 is connected to the low power consumption module 12 and the first read reference voltage Vref1, and converts the first read reference voltage Vref1 into a second read reference voltage Vref2 when the external enable signal EN is activated; the comparator 143 is connected to the low power consumption module 12, the first current conversion module 141, and the second current conversion module 142, and compares the second read voltage Vread2 with the second read reference voltage Vref2 to obtain a read voltage signal when the external enable signal EN is active. In this embodiment, the first current conversion module 141 and the second current conversion module 142 are equal-proportioned.
More specifically, the first current conversion module 141 includes a seventh PMOS PM7 and a second NMOS NM2. The source electrode of the seventh PMOS PM7 is connected to the low power consumption module 12, the gate electrode is connected to the first read voltage Vread1, and the drain electrode is connected to the drain electrode of the second NMOS NM 2; the second NMOS transistor NM2 forms a current mirror structure, a gate is connected to a drain, and outputs the second read voltage Vread2, and a source of the second NMOS transistor NM2 is grounded.
More specifically, the second current conversion module 142 includes an eighth PMOS transistor PM8 and a third NMOS transistor NM3. The source electrode of the eighth PMOS PM8 is connected to the low power consumption module 12, the gate electrode is connected to the first read reference voltage Vref1, and the drain electrode is connected to the drain electrode of the third NMOS NM 3; the third NMOS transistor NM3 forms a current mirror structure, a gate is connected to a drain, and outputs the second read reference voltage Vref2, and a source of the third NMOS transistor NM3 is grounded.
More specifically, the comparator includes a ninth PMOS transistor PM9, a tenth PMOS transistor PM10, a fourth NMOS transistor NM4, and a fifth NMOS transistor NM5; the source electrode of the ninth PMOS PM9 is connected to the low power consumption module 12, the gate electrode is connected to the first read voltage Vread1, and the drain electrode is connected to the drain electrode of the fourth NMOS NM 4; the gate of the fourth NMOS transistor NM4 is connected to the second read reference voltage Vref2, and the source is grounded; a source electrode of the tenth PMOS tube PM10 is connected with the low-power consumption module 12, a grid electrode is connected with the first reading reference voltage Vref1, and a drain electrode is connected with a drain electrode of the fifth NMOS tube NM5; the gate of the fifth NMOS transistor NM5 is connected to the second read voltage Vread5, and the source is grounded.
In this embodiment, the size of the ninth PMOS PM9 and the tenth PMOS PM10 is the same.
It should be noted that the structure of each unit in the comparing module 14 may be any one of the prior art, and the current conversion and comparison functions may be realized, which is not limited to the present embodiment.
As shown in fig. 1, the low power matching module 15 is connected to the parasitic matching module 16, the low power matching module 15 is configured to perform voltage matching on the low power matching module 12, and the parasitic matching module 16 is configured to cancel parasitic effects of transistor gates in the comparing module 14.
Specifically, the low-power matching module 15 includes a fifth PMOS tube PM5, where a source of the fifth PMOS tube PM5 is connected to the power supply voltage VDD, a gate of the fifth PMOS tube PM is connected to the first control signal, a drain of the fifth PMOS tube PM5 is connected to the parasitic matching module 16, and dimensions of the fifth PMOS tube PM5 and the first PMOS tube PM1, the second PMOS tube PM2, the third PMOS tube PM3, and the fourth PMOS tube PM4 are the same.
It should be noted that, the topology and the size of the low-power matching module 15 are the same as those of the low-power matching module 12, so as to perform voltage matching on the low-power matching module 12. In practical use, the low-power matching module 15 may be designed according to the structure of the low-power module 12, which is not limited by the embodiment.
Specifically, the parasitic matching module 16 includes 2 (b-1) eleventh PMOS pipes PM11 and sixth NMOS pipes NM6 connected in parallel, where a source of the eleventh PMOS pipe PM11 is connected to the low-power consumption matching module 15, a gate of the eleventh PMOS pipe PM is connected to the first read voltage Vread1, and a drain of the eleventh PMOS pipe PM is connected to the sixth NMOS pipe NM6; the gate and the source of the sixth NMOS transistor NM6 are grounded, wherein b is the number of sense amplifiers of the nonvolatile memory connected to the same read reference voltage generating circuit.
It should be noted that, in the parasitic matching module 16, the eleventh PMOS transistor PM11 and the ninth PMOS transistor PM9 and the tenth PMOS transistor PM10 have the same size, and the source and drain voltages of the eleventh PMOS transistor PM11 and the ninth PMOS transistor PM9 and the tenth PMOS transistor PM10 are the same, so that the charging time of the parasitic capacitance of the sense amplifier is the same, and the reading speed is improved.
As an implementation manner of the present invention, the nonvolatile memory sense amplifier 1 further includes a latch 17, the latch 17 is connected to an output end of the comparing module 14, in this embodiment, a first output end of the comparing module 14 is a drain electrode of the ninth PMOS tube PM9 and the fourth NMOS tube NM4, a second output end of the comparing module 14 is a drain electrode of the tenth PMOS tube PM10 and the fifth NMOS tube NM5, a first output end of the comparing module 14 is connected to a reset end of the latch 17, a second output end of the comparing module 14 is connected to a set end of the latch 17, and the comparing module 14 outputs the read signal DO. The latch 17 includes, but is not limited to, RS latch, D latch, JK latch, and any circuit structure capable of implementing a latch function is suitable, but not limited to this embodiment.
Example two
As shown in fig. 2, the present embodiment provides a phase change memory including:
read reference voltage generation circuit 2 and phase change memory cell array 3.
As shown in fig. 2, the read reference voltage generating circuit 2 is connected to the phase change memory cell array 3, and provides a first read reference voltage Vref1 to the phase change memory cell array 3.
Specifically, the read reference voltage generation circuit 2 accepts the clamp voltage Vclamp and generates the first read reference voltage Vref1. The variation trend of the read reference current Iref generated according to the first read reference voltage Vref1 is consistent with the read current Iread described in the first embodiment, and the final stable value is between the highest value Iread of the crystalline resistance and the lowest value Iread of the amorphous resistance.
As shown in fig. 2, the phase-change memory cell array 3 includes at least one phase-change memory cell module 4 and nonvolatile memory sense amplifiers 1 corresponding to the phase-change memory cell modules 4 one by one, and each bit line in the phase-change memory cell module 4 is connected to the nonvolatile memory sense amplifier through a read transfer gate RTG.
In this embodiment, each phase change memory cell module 4 in the phase change memory cell array 3 is connected to the read reference voltage generating circuit 11, and the first read reference voltage Vref1 is obtained from the read reference voltage generating circuit 11. The phase change memory cell array 3 includes a plurality of phase change memory cell modules 4, in order to facilitate displaying only 3 in fig. 2, in practical use, the number of the phase change memory cell modules 4 in the phase change memory cell array 3 may be set according to design requirements, and meanwhile, the number of the phase change memory cell modules 4 connected to the same read reference voltage generating circuit 11 may be set according to requirements, which is not limited to the embodiment.
Specifically, the row control signals of the phase change memory cell module 4 are word line signals WL1 to WLn, the column transfer signals are bit line signals LBL1 to LBLm, and only one word line and one bit line are turned on at the same time. As shown in fig. 2, the phase-change memory cell 41 includes a phase-change resistor R GST And a switching tube NM7, in this embodiment, taking the 2 nd row and 3 rd column phase change memory cells as examples, the first phase change resistor R GST One end of the switching tube NM7 is connected with the read transmission gate RTG through a word line LBL3 and then is connected with the nonvolatile memory sensitive amplifier 1, the other end of the switching tube NM7 is connected with the drain electrode of the switching tube NM7, and the grid electrode of the switching tube NM7 is connected with the word line WL2 and the source electrode of the switching tube NM7 is grounded.
Specifically, in this embodiment, the number of the nonvolatile memory sense amplifiers 1 connected to the same read reference voltage generating circuit 2 is set to b, the number of the phase change memory cells connected to the same bit line in the phase change memory cell module 4 is set to n, the number of the bit lines connected to the same nonvolatile memory sense amplifier 1 in the phase change memory cell module 4 is set to m, and specific values may be set according to actual needs, and are not limited herein.
More specifically, the nonvolatile memory sense amplifier 1 is connected to each read transfer gate through a read bit line RBL, is connected to a local bit line LBL through a read transfer gate, and is connected to the read reference voltage generating circuit 2 to receive the first read reference voltage Vref1. The first read reference voltage Vref1 is reduced to a read reference current Iref and the read reference current Iref is compared with the read current Iread in the selected memory cell 41 to generate the read signal DO of the selected memory cell 41. The internal structure and the working principle of the nonvolatile memory sense amplifier 1 are the same as those of the first embodiment, and are not described in detail herein.
As shown in fig. 1 to 2, when the data stored in the selected memory cell 41 is 1, iread > Iref; the drain current of the second NMOS transistor NM2 will rise; the second NMOS transistor NM2 is equivalently connected to a diode, so that the gate voltage of the second NMOS transistor NM2 will rise, and the gate voltage of the fifth NMOS transistor NM5 will also rise; however, the first read reference voltage signal Vref1 is unchanged, the gate voltage of the tenth PMOS transistor PM10 is unchanged, and the current that the tenth PMOS transistor PM10 tries to copy is smaller than that of the fifth NMOS transistor NM5; the current attempted to be copied by the ninth PMOS transistor PM9 is greater than that of the fourth NMOS transistor NM 4; the second output voltage V2 of the comparison module 14 will drop to around 0V, while the first output voltage V1 of the comparison module 14 will rise close to the supply voltage VDD. As shown in fig. 1 to 2, if the data stored in the selected memory cell 41 is 0, iread < Iref; the drain current of the second NMOS transistor NM2 decreases; the gate voltage of the second NMOS transistor NM2 decreases, and the gate voltage of the fifth NMOS transistor NM5 also decreases; however, the first read reference voltage signal Vref1 is unchanged, the gate voltage of the tenth PMOS transistor PM10 is unchanged, and the current that the tenth PMOS transistor PM10 tries to copy is greater than that of the fifth NMOS transistor NM5; the current attempted to be copied by the ninth PMOS transistor PM9 is smaller than that of the fourth NMOS transistor NM 4; the second output voltage V2 of the comparison module 14 will rise close to the supply voltage VDD, while the first output voltage V1 of the comparison module 14 will drop to around 0V. The output voltages V1 and V2 of the comparison module 14 are output to an SR latch, so as to obtain an output signal DO, and when the read current Iread of the selected memory cell is greater than the read reference current Iref, the SR latch outputs a high level; the SR latch outputs a low level when the read current Iread of the selected memory cell is less than the read reference current Iref.
Fig. 3 is a comparison of simulation results of power consumption of the sense amplifier for nonvolatile memory according to the present invention and the sense amplifier in the prior art applied to a phase change memory. The chip adopts a 40nm technology, the bit line length 1024 and 32 bit lines share one nonvolatile memory sense amplifier, and b=4. For the 3 sense amplifiers that are not turned on, the prior art will generate a leakage of iconv=9.91 μa, whereas the invention has only inew=54.15 nA, which is nearly 200 times smaller than the prior art.
Fig. 4 and 5 compare the read time simulation results of the non-volatile memory sense amplifier of the present invention and the sense amplifier of the prior art. EN is the enable signal, DO is the sense signal, and as the EN enable signal voltage increases, the sense amplifier starts reading. The random reading time in the prior art is 3.46ns, and the random reading time is 3.37ns, so that compared with the prior art, the nonvolatile memory sense amplifier can improve the reading speed.
In summary, the present invention provides a nonvolatile memory sense amplifier and a phase change memory, comprising: the device comprises a control module, a low-power consumption module, a first read voltage module, a comparison module, a low-power consumption matching module and a parasitic matching module; the control module receives an external enabling signal, generates a first control signal and a second control signal based on the external enabling signal, and respectively controls the working states of the low-power-consumption module and the first reading voltage module; the low-power consumption module is connected with the control module and the comparison module and is used for closing the comparison module when the external enabling signal fails; the first reading voltage module is connected with the control module and the storage array and is used for reading the reading current of a selected storage unit in the storage array when the external enabling signal is enabled and converting the reading current into a first reading voltage; the comparison module is connected with the first reading voltage module and the low power consumption module and receives a first reading reference voltage, and is used for comparing the first reading voltage with the first reading reference voltage when the external enabling signal is enabled to obtain a reading voltage signal; the low-power-consumption matching module is connected with the parasitic matching module, the low-power-consumption matching module is used for carrying out voltage matching on the low-power-consumption module, and the parasitic matching module is used for counteracting the parasitic effect of the transistor grid electrode in the comparison module. The topology structure and the size of the low-power-consumption matching module of the nonvolatile memory sense amplifier and the phase-change memory are the same as those of the low-power-consumption module, and the source and drain voltages of transistors in the parasitic matching module are the same as those in the comparison module, so that the charging time of parasitic capacitance is the same, and the reading speed is improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (8)
1. A nonvolatile memory sense amplifier, the nonvolatile memory sense amplifier comprising at least:
the device comprises a control module, a low-power consumption module, a first read voltage module, a comparison module, a low-power consumption matching module and a parasitic matching module;
the control module receives an external enabling signal, generates a first control signal and a second control signal based on the external enabling signal, and respectively controls the working states of the low-power-consumption module and the first reading voltage module;
the low-power consumption module is connected with the control module and the comparison module and is used for closing the comparison module when the external enabling signal fails; the low-power consumption module comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube and a fifth PMOS tube; the sources of the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube are connected with power supply voltage, the grid is connected with the first control signal, and the drains are respectively connected with the comparison module; the source electrode of the fifth PMOS tube is connected with a power supply voltage, the grid electrode of the fifth PMOS tube is connected with the first control signal, and the drain electrode of the fifth PMOS tube is connected with the parasitic matching module; the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube and the fifth PMOS tube have the same size;
the first reading voltage module is connected with the control module and the storage array and is used for reading the reading current of a selected storage unit in the storage array when the external enabling signal is enabled and converting the reading current into a first reading voltage;
the comparison module is connected with the first reading voltage module and the low power consumption module and receives a first reading reference voltage, and is used for comparing the first reading voltage with the first reading reference voltage when the external enabling signal is enabled to obtain a reading voltage signal;
the low-power-consumption matching module is connected with the parasitic matching module, the low-power-consumption matching module is used for carrying out voltage matching on the low-power-consumption module, and the parasitic matching module is used for counteracting the parasitic effect of the transistor grid electrode in the comparison module.
2. The non-volatile memory sense amplifier of claim 1, wherein: the control module comprises a first inverter and a second inverter; the input end of the first inverter receives the external enabling signal and outputs a first control signal; the input end of the second inverter is connected with the output end of the first inverter, and outputs a second control signal.
3. The non-volatile memory sense amplifier of claim 1, wherein: the first read voltage module comprises a transmission gate, a first NMOS tube and a sixth PMOS tube; the input end of the transmission gate is connected with the clamping voltage, and the control end of the transmission gate is connected with the second control signal; the source electrode of the first NMOS tube is connected with the storage array, the grid electrode of the first NMOS tube is connected with the output end of the transmission gate, and the drain electrode of the first NMOS tube is connected with the drain electrode of the sixth PMOS tube; and the source electrode of the sixth PMOS tube is connected with a power supply voltage, and the grid electrode of the sixth PMOS tube is connected with the drain electrode and outputs the first reading voltage.
4. The non-volatile memory sense amplifier of claim 1, wherein: the comparison module comprises a first current conversion module, a second current conversion module and a comparator; the first current conversion module is connected with the low-power consumption module and the first reading voltage, and converts the first reading voltage into a second reading voltage when the external enabling signal is enabled; the second current conversion module is connected with the low-power consumption module and the first reading reference voltage, and converts the first reading reference voltage into a second reading reference voltage when the external enabling signal is enabled; the comparator is connected with the low-power consumption module, the first current conversion module and the second current conversion module, and compares the first reading voltage with the first reading reference voltage and the second reading voltage with the second reading reference voltage to obtain a reading voltage signal when the external enabling signal is enabled; the first current conversion module and the second current conversion module are converted in equal proportion.
5. The nonvolatile memory sense amplifier of claim 4, wherein: the first current conversion module comprises a seventh PMOS tube and a second NMOS tube; the source electrode of the seventh PMOS tube is connected with the low-power consumption module, the grid electrode of the seventh PMOS tube is connected with the first reading voltage, and the drain electrode of the seventh PMOS tube is connected with the drain electrode of the second NMOS tube; the grid electrode of the second NMOS tube is connected with the drain electrode and outputs the second reading voltage, and the source electrode of the second NMOS tube is grounded; the second current conversion module comprises an eighth PMOS tube and a third NMOS tube; the source electrode of the eighth PMOS tube is connected with the low-power consumption module, the grid electrode of the eighth PMOS tube is connected with the first reading reference voltage, and the drain electrode of the eighth PMOS tube is connected with the drain electrode of the third NMOS tube; the grid electrode of the third NMOS tube is connected with the drain electrode and outputs the second reading reference voltage, and the source electrode of the third NMOS tube is grounded; the comparator comprises a ninth PMOS tube, a tenth PMOS tube, a fourth NMOS tube and a fifth NMOS tube; the source electrode of the ninth PMOS tube is connected with the low-power consumption module, the grid electrode of the ninth PMOS tube is connected with the first reading voltage, and the drain electrode of the ninth PMOS tube is connected with the drain electrode of the fourth NMOS tube; the grid electrode of the fourth NMOS tube is connected with the second reading reference voltage, and the source electrode of the fourth NMOS tube is grounded; the source electrode of the tenth PMOS tube is connected with the low-power consumption module, the grid electrode of the tenth PMOS tube is connected with the first reading reference voltage, and the drain electrode of the tenth PMOS tube is connected with the drain electrode of the fifth NMOS tube; and the grid electrode of the fifth NMOS tube is connected with the second reading voltage, and the source electrode is grounded.
6. The non-volatile memory sense amplifier of claim 5, wherein: the ninth PMOS tube and the tenth PMOS tube have the same size.
7. The non-volatile memory sense amplifier of claim 6, wherein: the parasitic matching module comprises 2 (b-1) eleventh PMOS tubes and a sixth NMOS tube which are connected in parallel, wherein the source electrode of the eleventh PMOS tube is connected with the low-power-consumption matching module, the grid electrode of the eleventh PMOS tube is connected with the first reading voltage, and the drain electrode of the eleventh PMOS tube is connected with the sixth NMOS tube; the grid electrode and the source electrode of the sixth NMOS tube are grounded; the eleventh PMOS tube, the ninth PMOS tube and the tenth PMOS tube have the same size, and b is the number of nonvolatile memory sense amplifiers connected to the same read reference voltage production circuit.
8. A phase change memory, the phase change memory comprising at least:
a read reference voltage generation circuit and a phase change memory cell array;
the read reference voltage generation circuit is connected with the phase change memory cell array and provides a first read reference voltage for the phase change memory cell array;
the phase-change memory cell array comprises at least one phase-change memory cell module and the nonvolatile memory sense amplifier according to any one of claims 1-7, wherein the phase-change memory cell module corresponds to the phase-change memory cell module one by one, and each bit line in the phase-change memory cell module is connected with the nonvolatile memory sense amplifier through a read transmission gate.
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