CN102592650A - High-speed low-power sense amplifier capable of automatically turning off bit line - Google Patents

Abstract

The invention discloses a high-speed low-power sense amplifier capable of automatically turning off a bit line. The high-speed low-power sense amplifier comprises a precharging module, a balance circuit module, an enable circuit module, a cross-coupling inverter module, an input circuit module and a module for automatically turning off the bit line. According to the high-speed low-power sense amplifier, separate input-output structures are adopted; compared with the conventional sense amplifier with a common input-output structure, the situation that a capacitor at an output end carries out discharge for the bit line in the signal detection period is avoided, so that the time of forming a rated voltage difference between bit lines is largely shortened, therefore the time delay of the sense amplifier is reduced, and the response speed of the sense amplifier is increased; moreover, a precharging operation is carried out through discharging two output ends of the sense amplifier to 0 through a precharging tube; and in comparison with the satiation that the precharging operation of the conventional sense amplifier is carried out through precharging the output ends to VDD (Voltage Drain-Drain), the precharging power consumption is saved, so that the total power consumption of the sense amplifier is reduced.

Description

A kind of high-speed low-power-consumption is from turn-offing the bit line sense amplifier

Technical field

The present invention relates to a kind of high-speed low-power-consumption that is applied to the semiconductor SRAM from turn-offing the bit line sense amplifier.

Background technology

Storer occupies very important position as the memory device of data and instruction in System on Chip/SoC.The speed of storer depends primarily on the time for reading of storer.The time for reading of storer mainly is meant the time of experiencing from the output that is input to data-signal of address signal, and generally the delay by address input buffer device, code translator, storage unit, sense amplifier and output buffer determines jointly.Therefore, reduce the time for reading of storer, two kinds of methods are generally arranged: the one, reduce to be input to the time-delay of word line gating from address signal, because the form relative fixed of circuit such as inner code translator, the time-delay that therefore reduces in this way is more limited; Another kind is to reduce to be strobed into the time-delay that data output is experienced from word line, and this can realize through the design that improves sense amplifier.It is thus clear that the design of high-performance sense amplifier is vital for the improvement of memory performance.

The purpose of sense amplifier work is the data in the reading cells through signal variation small between amplifies bit line.In particular, the effect of sense amplifier in storer is mainly reflected in aspect following three: at first be amplification, it is enlarged into signal difference small between bit line logic level " 0 " and " 1 " of standard; Next is the discharge amplitude that reduces bit line, thereby reduces the power consumption that bit line discharges and recharges.Be through signal difference small between amplifies bit line at last and export complete logic level, avoid waiting for that the complete discharge off of bit line exports again, thereby reduce the time for reading of storer.The work of sense amplifier generally is divided into two stages: the one, and preliminary filling, the 2nd amplifies.

Sense amplifier mainly is divided into two kinds: current mode sense amplifier and voltage-type sense amplifier.Detect and amplifier bit line between the Weak current difference be referred to as the current mode sense amplifier, though the current mode sense amplifier does not receive the influence of bit-line load electric capacity, its structure complicacy, poor reliability, power consumption is big; The voltage-type sense amplifier detects also small voltage difference between amplifies bit line; Though it receives the influence of bit-line load electric capacity; But it is simple in structure; Stability is high, low in energy consumption, and area is generally also little than current mode sense amplifier, so the sense amplifier that adopts in present most of commercial SRAM is the voltage-type sense amplifier.

As shown in Figure 1, in the voltage-type sense amplifier that uses in the prior art, as the given preliminary filling control signal PRE in outside, when outside given enable signal SAEN is low level, sense amplifier is in pre-charge state, and its output terminal is precharged to VDD; When preliminary filling control signal PRE is a high level; When enable signal SAEN was low level, sense amplifier was in the detection signal state, because this sense amplifier is the input and output sharing structure; So when detecting input signal; Preliminary filling to the output terminal of high level can manage P3 through PMOS, P4 discharges to the given bit line in outside, sense amplifier output terminal load capacitance is big more, amplification quantity is big more; This can prolong the time that differential voltage between bit line reaches ratings, thereby increases the time-delay of sense amplifier; Sense amplifier precharge operation shown in Figure 1 in addition be with the output terminal preliminary filling to high level, this can increase the power consumption of sense amplifier.

Summary of the invention

Prior art sense amplifier output terminal meeting pairs of bit line during detecting input signal is discharged and precharge operation is that output terminal is charged to the problem that there is the preliminary filling power consumption in high level in order to solve; The present invention proposes a kind of high-speed low-power-consumption and replaces traditional sense amplifier from turn-offing the bit line sense amplifier; To reduce time-delay and power consumption, improve the performance of sense amplifier.

For realizing above-mentioned purpose; The technical scheme that the present invention takes is: a kind of high-speed low-power-consumption is from turn-offing the bit line sense amplifier; It is characterized in that; Comprise pre-charge module, balancing circuit modules, enable circuits module, cross coupling inverter module, input circuit module and turn-off the bit line module certainly, wherein:

Pre-charge module comprises NMOS pipe N1 and NMOS pipe N2, and NMOS pipe N1 also is connected outside given preliminary filling signal PRE with the gate interconnect of NMOS pipe N2, and the source electrode of NMOS pipe N1 and NMOS pipe N2 and substrate be ground connection GND all;

Balancing circuit modules comprises NMOS pipe N3; The grid of the grid of NMOS pipe N3 and NMOS pipe N1 and the grid of NMOS N2 link together; The drain electrode of NMOS pipe N3 is connected with the drain electrode of NMOS pipe N1, the source electrode of NMOS pipe N3 is connected the substrate ground connection GND of NMOS pipe N3 with the drain electrode of NMOS pipe N2;

The enable circuits module comprises PMOS pipe P1, and the grid of PMOS pipe P1 connects outside given enable signal SANE, and the source electrode of PMOS pipe P1 all links to each other with VDD with substrate;

The cross coupling inverter module comprises that PMOS pipe P2, PMOS pipe P3, NMOS pipe N4, NMOS manage N5; The substrate of PMOS pipe P2 and PMOS pipe P3 all connects VDD; The source electrode of PMOS pipe P2 and PMOS pipe P3 links together and is connected with the drain electrode of PMOS pipe P1; The grid of PMOS pipe P2 and PMOS pipe P3 is connected with the grid of NMOS pipe N4 and NMOS pipe N5 respectively; The drain electrode of PMOS pipe P2 and PMOS pipe P3 is connected with the drain electrode of NMOS pipe N4 and NMOS pipe N5 respectively; The grid of the grid of the drain electrode of the drain electrode of PMOS pipe P2, NMOS pipe N4 and PMOS pipe P3 and NMOS pipe N5 links together, and the drain electrode of the grid of the grid of PMOS pipe P2, NMOS pipe N4 and the drain electrode of PMOS pipe P3 and NMOS pipe N5 links together, substrate and the source grounding GND of NMOS pipe N4 and NMOS pipe N5;

The input circuit module comprises that NMOS pipe N6, NMOS manage N7; Substrate and the source grounding of NMOS pipe N6 and NMOS pipe N7; The drain electrode of the drain electrode of the drain electrode of the drain electrode of the drain electrode of NMOS pipe N6 and NMOS pipe N1, NMOS pipe N3, PMOS pipe P2 and NMOS pipe N4 links together, and the drain electrode of the drain electrode of the drain electrode of NMOS pipe N7 and NMOS pipe N2, the drain electrode of PMOS pipe P3 and NMOS pipe N5 links together;

Comprise PMOS pipe P4, PMOS pipe P5, NMOS pipe N8 and NMOS pipe N9 from turn-offing the bit line module; The gate interconnection of the grid of PMOS pipe P4 and NMOS pipe N8 and link together with the drain electrode of the drain electrode of the drain electrode of the drain electrode of NMOS pipe N1, NMOS pipe N3, NMOS pipe N6, PMOS pipe P2 and drain electrode that NMOS manages N4 is connected; The substrate of PMOS pipe P4 connects VDD; The source electrode of PMOS pipe P4 is connected with the outside position line BL that gives; The grid of the drain electrode of the drain electrode of PMOS pipe P4 and NMOS pipe N8 and NMOS pipe N6 links together; Substrate and the source grounding GND of NMOS pipe N8; The grid of PMOS pipe P5 links together with the gate interconnection of NMOS pipe N9 and with the drain electrode of NMOS pipe N2, the source electrode of NMOS pipe N3, the drain electrode of NMOS pipe N7, the drain electrode of PMOS pipe P3 and the drain electrode of NMOS pipe N5, and the substrate of PMOS pipe P5 connects VDD, and the source electrode of PMOS pipe P5 is connected with given another bit line BLB in outside; The grid of the drain electrode of the drain electrode of PMOS pipe P5 and NMOS pipe N9 and NMOS pipe N7 links together, substrate and the source grounding GND of NMOS pipe N9.

Compare with existing sense amplifier, the present invention has the following advantages and is showing effect:

1) sense amplifier of the present invention adopts the input and output isolating construction; Compare with traditional shared input/output structure sense amplifier; Avoided during detection signal, the output capacitor pairs of bit line is discharged, and greatly reduces the time that forms the rated voltage difference between bit line; Thereby reduced the time-delay of sense amplifier, improved the speed of sense amplifier;

2) precharge operation of sense amplifier of the present invention be with two output terminals of sense amplifier through the preliminary filling tube discharge to " 0 "; With traditional sense amplifier precharge operation is that the output terminal preliminary filling is compared to VDD; Its precharge operation does not consume power consumption; And the amplifieroperation power consumption of its amplifieroperation power consumption and traditional sense amplifier is suitable, thereby makes the power consumption of sense amplifier of the present invention reduce greatly;

Description of drawings

Fig. 1 is a prior art sensitive amplifier circuit schematic diagram;

Fig. 2 is the circuit theory diagrams of sense amplifier of the present invention;

Fig. 3 frame of broken lines partly is the pre-charge module among Fig. 2;

Fig. 4 frame of broken lines partly is the balancing circuit modules among Fig. 2;

Fig. 5 frame of broken lines partly is the enable circuits module among Fig. 2;

Fig. 6 frame of broken lines partly is the cross coupling inverter module among Fig. 2;

Fig. 7 frame of broken lines partly is the input circuit module among Fig. 2;

Fig. 8 frame of broken lines partly is the bit line of the shutoff certainly module among Fig. 2;

Fig. 9 is input signal, control signal and the signal output waveform figure of sense amplifier of the present invention.

Embodiment

Referring to Fig. 2-8, sense amplifier of the present invention comprises pre-charge module, balancing circuit modules, enable circuits module, cross coupling inverter module, input circuit module and turn-offs the bit line module certainly, wherein:

Pre-charge module (Fig. 3 frame of broken lines part); Be used for the enable signal SAEN that the output terminal of sense amplifier is externally given and discharge into " 0 " current potential before effectively; Comprise two NMOS pipe N1, N2 by the given preliminary filling control signal PRE control in outside; NMOS pipe N1 also is connected outside given preliminary filling signal PRE with the gate interconnect of N2, and the source electrode of NMOS pipe N1 and N2 and substrate be ground connection GND all;

Balancing circuit modules (Fig. 4 frame of broken lines part); Be used for current potential at effective forward horizontal stand two output terminals of the enable signal SAEN of sense amplifier; Two output terminal current potentials are equated; It comprises the NMOS pipe N3 of outside given preliminary filling control signal PRE control; The grid of the grid of NMOS pipe N3 and NMOS pipe N1 and the grid of NMOS N2 link together, and the drain electrode of NMOS pipe N3 is connected with the drain electrode of NMOS pipe N1, the source electrode of NMOS pipe N3 is connected the substrate ground connection GND of NMOS pipe N3 with the drain electrode of NMOS pipe N2;

Enable circuits module (Fig. 5 frame of broken lines part); Be used to control opening and shutting off of whole sense amplifier; It comprises the PMOS pipe P1 of enable signal SAEN control, and the grid of PMOS pipe P1 connects outside given enable signal SANE, and the source electrode of PMOS pipe P1 all links to each other with VDD with substrate;

Cross coupling inverter module (Fig. 6 frame of broken lines part); Be used for after sense amplifier is opened; Amplify small bit line differential voltage fast, comprise PMOS pipe P2, P3, NMOS pipe N4, N5, the substrate of PMOS pipe P2 and P3 all connects VDD; The source electrode of PMOS pipe P2 and P3 links together and is connected with the drain electrode of PMOS pipe P1; The grid of PMOS pipe P2 and PMOS pipe P3 is connected with the grid of NMOS pipe N4 and NMOS pipe N5 respectively, and the drain electrode of PMOS pipe P2 and PMOS pipe P3 is connected with the drain electrode of NMOS pipe N4 and NMOS pipe N5 respectively, and the grid of the drain electrode of the drain electrode of PMOS pipe P2, NMOS pipe N4 and the grid of PMOS pipe P3 and NMOS pipe N5 links together; The drain electrode of the drain electrode of the grid of the grid of PMOS pipe P2, NMOS pipe N4 and PMOS pipe P3 and NMOS pipe N5 links together; Substrate and the source grounding GND of NMOS pipe N4 and NMOS pipe N5, PMOS pipe P2, NMOS pipe N4 form phase inverter INV1, and PMOS pipe P3, NMOS pipe N5 form phase inverter INV2.

Input circuit module (Fig. 7 frame of broken lines part); Be used to detect the bit line differential voltage and open the back at sense amplifier the output terminal of sense amplifier is discharged; Comprise from the NMOS pipe N6, the NMOS that turn-off the control of bit line module output voltage and manage N7; Substrate and the source grounding of NMOS pipe N6 and NMOS pipe N7; The drain electrode of the drain electrode of the drain electrode of the drain electrode of the drain electrode of NMOS pipe N6 and NMOS pipe N1, NMOS pipe N3, PMOS pipe P2 and NMOS pipe N4 links together, and the drain electrode of the drain electrode of the drain electrode of NMOS pipe N7 and NMOS pipe N2, the drain electrode of PMOS pipe P3 and NMOS pipe N5 links together.

From turn-offing bit line module (Fig. 8 frame of broken lines part); Be used for transmission and turn-off bit-line voltage; Comprise PMOS pipe P4, PMOS pipe P5, NMOS pipe N8 and NMOS pipe N9; The gate interconnection of the grid of PMOS pipe P4 and NMOS pipe N8 and link together with the drain electrode of the drain electrode of the drain electrode of the drain electrode of NMOS pipe N1, NMOS pipe N3, NMOS pipe N6, PMOS pipe P2 and drain electrode that NMOS manages N4 is connected; The substrate of PMOS pipe P4 connects VDD, and the source electrode of PMOS pipe P4 is connected with the outside position line BL that gives, and the drain electrode of the drain electrode of PMOS pipe P4 and NMOS pipe N8 and the grid of NMOS pipe N6 link together; Substrate and the source grounding GND of NMOS pipe N8; The grid of PMOS pipe P5 links together with the gate interconnection of NMOS pipe N9 and with the drain electrode of NMOS pipe N2, the source electrode of NMOS pipe N3, the drain electrode of NMOS pipe N7, the drain electrode of PMOS pipe P3 and the drain electrode of NMOS pipe N5, and the substrate of PMOS pipe P5 connects VDD, and the source electrode of PMOS pipe P5 is connected with given another bit line BLB in outside; The grid of the drain electrode of the drain electrode of PMOS pipe P5 and NMOS pipe N9 and NMOS pipe N7 links together, substrate and the source grounding GND of NMOS pipe N9.Because the grid of PMOS pipe P4, NMOS pipe N8 and PMOS pipe P5, NMOS pipe N9 is respectively by the output signal controlling of sense amplifier; The source electrode of PMOS pipe P4, PMOS pipe P5 links to each other for position line BL, BLB with the outside respectively again; So when sense amplifier is in pre-charge state; Sense amplifier is output as " 0 ", two PMOS pipe P4, P5 conducting, and bit-line voltage can be delivered to the grid of input circuit NMOS pipe N6, NMOS pipe N7; After sense amplifier is opened and is correctly exported; Output terminal is that the meeting of high level is turn-offed the PMOS pipe that is connected with bit line; Thereby the cut-out bit line is connected with the input circuit module; Accomplish from the process of turn-offing bit-line voltage, this process by internal signal control, does not need extra introducing external control signal fully.

Principle of work of the present invention is following:

With reference to Fig. 9, the preliminary filling control signal PRE that sense amplifier of the present invention is outside given is same signal with outside given enable signal SAEN.As the given preliminary filling control signal PRE in outside, when outside given enable signal SAEN is high level, sense amplifier turn-offs.Preliminary filling pipe NMOS pipe N1, NMOS pipe N2 open; Sense amplifier is in pre-charge state, and this moment, its two output terminal was not to be charged to VDD, but discharged into " 0 " current potential through two NMOS pipe N1, N2; Pre-charge process consumed energy not just like this, the average power consumption of pre-charge process is 0; In the pre-charge process, balance pipe NMOS pipe N3 opens, and is used to make two output terminals before sense amplifier carries out amplifieroperation, to be in identical current potential; When treating output1, output2 two node potentials for " 0 ", from two PMOS of breaking circuit module pipe P4, P5 complete opening, the outside voltage of giving position line BL, BLB is managed the grid that P4, P5 are delivered to input pipe NMOS pipe N6, N7 through PMOS;

As the given preliminary filling control signal PRE in outside, when outside given enable signal SAEN is low level, sense amplifier is started working.Enabling to manage PMOS pipe P1 opens; Supply voltage VDD charges to two output terminals through PMOS pipe P1, P2, the PMOS pipe P3 pipe of opening; Input pipe NMOS pipe N6, N7 open; Sense amplifier two output terminals discharge through NMOS pipe N6, N7 respectively, and charging rate and output terminal over the ground the velocity of discharge of supply voltage VDD to output terminal depended in the rising of output1, output2 two node potentials or decline.Incipient stage, the PMOS pipe is in the saturation region, and the NMOS pipe is in linear zone, so charging current and discharge current are respectively:

$I_P=\frac{1}{2}\·{\mathrm{\μ}}_p\·C_{\mathrm{ox}}\·{\left(\frac{W}{L}\right)}_p\·{(V_{\mathrm{GS}}-V_{\mathrm{thp}})}^2$

$I_N={\mathrm{\μ}}_n\·C_{\mathrm{ox}}\·{\left(\frac{W}{L}\right)}_n\·[(V_{\mathrm{GS}}-V_{\mathrm{thn}})\·V_{\mathrm{DS}}-\frac{1}{2}{V}_{\mathrm{DS}}^2]$

Wherein, I _P, I _NBe respectively charging current and discharge current; m _p, m _nBe respectively the mobility of hole and electronics; C _OxElectric capacity for gate oxide;

Be respectively the breadth length ratio in PMOS pipe and NMOS pipe trench road; V _GS, V _DSBe respectively the voltage difference between metal-oxide-semiconductor grid and source electrode, drain electrode and the source electrode; V _Thp, V _ThnBe respectively the threshold voltage of PMOS pipe and NMOS pipe.

In the incipient stage, charging current is greater than discharge current, so the current potential of 2 of output1, output2 can rise; Because the outside current potential of position line BL, BLB of giving is unequal, so the discharge current size of NMOS pipe N6, N7 is unequal, thereby the current potential ascending velocity of node output1, output2 is different; As shown in Figure 9, when the current potential that the current potential of position line BL is higher than the outside position line BLB of giving was given in the outside, the discharge current of NMOS pipe N6 was greater than the discharge current of NMOS pipe N7, thereby node output1 current potential ascending velocity is less than node output2; As node output1, when the output2 current potential rises to a certain degree, the NMOS of phase inverter INV1, INV2 pipe N4, N6 open, and the positive feedback between the cross coupling inverter forms; The rapid reduction of current potential meeting of node output1, the current potential of node output2 is rising rapidly, and while input pipe and the positive feedback of turn-offing between the bit line module certainly also form: the output2 current potential is high more; PMOS pipe P5 from turn-offing the bit line module turn-offs; Simultaneously, the NMOS pipe N9 discharge current that turn-offs the bit line module certainly is big more, and the grid-control voltage of input pipe NMOS N7 is more little; Thereby the discharge current of NMOS pipe N7 is more little, and the current potential of node output2 is high more; When the output2 current potential rose to a certain degree, PMOS pipe P5 turn-offed, and the grid of input pipe NMOS pipe N7 is cut off with outside being connected of position line BLB, thereby accomplished from turn-offing the bit line operation.Because the existence of two positive-feedback circuit structures is arranged, after sense amplifier was opened, the sense amplifier output terminal is output complete logic level " 0 " and " 1 " rapidly.

When differential voltage between bit line was 350mV, sense amplifier of the present invention and existing sense amplifier time-delay and the power consumption under 5 kinds of process corner contrasted 1-table 5 as follows:

Table 1

Table 2

Table 3

Table 4

Table 5

Data from above table can find out that sense amplifier of the present invention is compared with the prior art sense amplifier, and speed has promoted 4.1%～11.8%, and power consumption has promoted 41.8%～46.2%, therefore have faster speed and lower power consumption.

Claims (1)

1. a high-speed low-power-consumption is characterized in that from turn-offing the bit line sense amplifier, comprise pre-charge module, balancing circuit modules, enable circuits module, cross coupling inverter module, input circuit module and turn-off the bit line module certainly, wherein:

Pre-charge module comprises NMOS pipe N1 and NMOS pipe N2, and NMOS pipe N1 also is connected outside given preliminary filling signal PRE with the gate interconnect of NMOS pipe N2, and the source electrode of NMOS pipe N1 and NMOS pipe N2 and substrate be ground connection GND all;

Balancing circuit modules comprises NMOS pipe N3; The grid of the grid of NMOS pipe N3 and NMOS pipe N1 and the grid of NMOS N2 link together; The drain electrode of NMOS pipe N3 is connected with the drain electrode of NMOS pipe N1, the source electrode of NMOS pipe N3 is connected the substrate ground connection GND of NMOS pipe N3 with the drain electrode of NMOS pipe N2;

The enable circuits module comprises PMOS pipe P1, and the grid of PMOS pipe P1 connects outside given enable signal SANE, and the source electrode of PMOS pipe P1 all links to each other with VDD with substrate;

The cross coupling inverter module comprises that PMOS pipe P2, PMOS pipe P3, NMOS pipe N4, NMOS manage N5; The substrate of PMOS pipe P2 and PMOS pipe P3 all connects VDD; The source electrode of PMOS pipe P2 and PMOS pipe P3 links together and is connected with the drain electrode of PMOS pipe P1; The grid of PMOS pipe P2 and PMOS pipe P3 is connected with the grid of NMOS pipe N4 and NMOS pipe N5 respectively; The drain electrode of PMOS pipe P2 and PMOS pipe P3 is connected with the drain electrode of NMOS pipe N4 and NMOS pipe N5 respectively; The grid of the grid of the drain electrode of the drain electrode of PMOS pipe P2, NMOS pipe N4 and PMOS pipe P3 and NMOS pipe N5 links together, and the drain electrode of the grid of the grid of PMOS pipe P2, NMOS pipe N4 and the drain electrode of PMOS pipe P3 and NMOS pipe N5 links together, substrate and the source grounding GND of NMOS pipe N4 and NMOS pipe N5;

The input circuit module comprises that NMOS pipe N6, NMOS manage N7; Substrate and the source grounding of NMOS pipe N6 and NMOS pipe N7; The drain electrode of the drain electrode of the drain electrode of the drain electrode of the drain electrode of NMOS pipe N6 and NMOS pipe N1, NMOS pipe N3, PMOS pipe P2 and NMOS pipe N4 links together, and the drain electrode of the drain electrode of the drain electrode of NMOS pipe N7 and NMOS pipe N2, the drain electrode of PMOS pipe P3 and NMOS pipe N5 links together;

Comprise PMOS pipe P4, PMOS pipe P5, NMOS pipe N8 and NMOS pipe N9 from turn-offing the bit line module; The gate interconnection of the grid of PMOS pipe P4 and NMOS pipe N8 and link together with the drain electrode of the drain electrode of the drain electrode of the drain electrode of NMOS pipe N1, NMOS pipe N3, NMOS pipe N6, PMOS pipe P2 and drain electrode that NMOS manages N4 is connected; The substrate of PMOS pipe P4 connects VDD; The source electrode of PMOS pipe P4 is connected with the outside position line BL that gives; The grid of the drain electrode of the drain electrode of PMOS pipe P4 and NMOS pipe N8 and NMOS pipe N6 links together; Substrate and the source grounding GND of NMOS pipe N8; The grid of PMOS pipe P5 links together with the gate interconnection of NMOS pipe N9 and with the drain electrode of NMOS pipe N2, the source electrode of NMOS pipe N3, the drain electrode of NMOS pipe N7, the drain electrode of PMOS pipe P3 and the drain electrode of NMOS pipe N5, and the substrate of PMOS pipe P5 connects VDD, and the source electrode of PMOS pipe P5 is connected with given another bit line BLB in outside; The grid of the drain electrode of the drain electrode of PMOS pipe P5 and NMOS pipe N9 and NMOS pipe N7 links together, substrate and the source grounding GND of NMOS pipe N9.

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