WO2023151146A1 - Sense amplification circuit and semiconductor memory - Google Patents

Abstract

Embodiments of the present disclosure provide a sense amplification circuit and a semiconductor memory. The sense amplification circuit comprises a discharge circuit and a signal amplification circuit, and the signal amplification circuit comprises a first cross coupling tube set and a second cross coupling tube set. The discharge circuit is connected between the first cross coupling tube set and the second cross coupling tube set. The discharge circuit is used for receiving a signal to be transmitted and a reference signal and respectively carrying out discharging processing on the basis of the signal to be transmitted and the reference signal to obtain a signal to be processed. The signal amplification circuit is used for amplifying the signal to be processed to obtain a target amplification signal.

Description

A sensitive amplifier circuit and semiconductor memory

Cross References to Related Applications

This disclosure is based on the Chinese patent application with the application number 202210127974.0, the filing date is February 11, 2022, and the invention title is "A Sensitive Amplifying Circuit and Semiconductor Memory", and claims the priority of the Chinese patent application. The Chinese patent The entire content of the application is hereby incorporated by reference into this disclosure.

technical field

The present disclosure relates to the technical field of semiconductor memory, in particular to a sensitive amplifier circuit and semiconductor memory.

Background technique

Dynamic Random Access Memory (Dynamic Random Access Memory, DRAM) is a semiconductor storage device commonly used in computers, consisting of many repeated storage units. In the process of data reading, the data signal of each storage unit is read through the local data line, the global data line and the data bus in sequence.

At present, there is a sensitive amplifier circuit between the global data line and the data bus, and the data signal output by the global data line needs to be transmitted to the data bus through the sensitive amplifier circuit, but the sensitivity of the sensitive amplifier circuit in the related art needs to be improved, affecting performance of DRAM.

Contents of the invention

The disclosure provides a sensitive amplifying circuit and a semiconductor memory, shortening the time required for the sensitive amplifying circuit to amplify signals by changing the circuit connection structure, and improving the sensitivity of the sensitive amplifying circuit.

In the first aspect, an embodiment of the present disclosure provides a sensitive amplifying circuit, the sensitive amplifying circuit includes a discharge circuit and a signal amplifying circuit, and the signal amplifying circuit includes a first cross-coupling tube group and a second cross-coupling tube group, and the discharging circuit is connected to Between the first cross-coupling tube group and the second cross-coupling tube group; wherein,

The discharge circuit is used to receive the signal to be transmitted and the reference signal, and perform discharge processing based on the signal to be transmitted and the reference signal respectively to obtain the signal to be processed;

The signal amplification circuit is used to amplify the signal to be processed to obtain the target amplified signal.

In a second aspect, an embodiment of the present disclosure provides a semiconductor memory, including the sensitive amplifier circuit as described in the first aspect.

An embodiment of the present disclosure provides a sensitive amplifying circuit, the sensitive amplifying circuit includes a discharge circuit and a signal amplifying circuit, and the signal amplifying circuit includes a first cross-coupling tube group and a second cross-coupling tube group, the discharge circuit is connected to the first cross Between the coupling tube group and the second cross-coupling tube group; wherein, the discharge circuit is used to receive the signal to be transmitted and the reference signal, and perform discharge processing based on the signal to be transmitted and the reference signal respectively to obtain the signal to be processed; the signal amplification circuit, It is used to amplify the signal to be processed to obtain the target amplified signal. In this way, the embodiments of the present disclosure provide a new sensitive amplifying circuit, and the discharge circuit is arranged between two pairs of cross-coupled tube groups, which can shorten the time required for the sensitive amplifying process, and further improve the performance of the DRAM.

Description of drawings

FIG. 1 is a schematic diagram of a partial structure of a DRAM provided by an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a partial structure of another DRAM provided by an embodiment of the present disclosure;

FIG. 3 is a schematic structural diagram of a write drive circuit provided in the related art;

FIG. 4 is a schematic structural diagram of a read amplifier circuit provided by the related art;

FIG. 5 is a schematic structural diagram of an output driving circuit provided by the related art;

FIG. 6 is a schematic structural diagram of a sensitive amplifier circuit provided by an embodiment of the present disclosure;

FIG. 7 is a schematic structural diagram of another sensitive amplifier circuit provided by an embodiment of the present disclosure;

FIG. 8 is a detailed structural schematic diagram of a sensitive amplifier circuit provided by an embodiment of the present disclosure;

FIG. 9 is a schematic diagram of a detailed structure of a reference output circuit provided by an embodiment of the present disclosure;

FIG. 10 is a detailed structural schematic diagram of an output driving circuit provided by an embodiment of the present disclosure;

FIG. 11 is a detailed structural schematic diagram of another sensitive amplifier circuit provided by an embodiment of the present disclosure;

FIG. 12 is a schematic structural diagram of a semiconductor memory provided by an embodiment of the present disclosure.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure with reference to the drawings in the embodiments of the present disclosure. It should be understood that the specific embodiments described here are only used to explain the related application, not to limit the application. It should also be noted that, for the convenience of description, only the parts related to the relevant application are shown in the drawings.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure, and are not intended to limit the present disclosure.

In the following description, references to "some embodiments" describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or a different subset of all possible embodiments, and Can be combined with each other without conflict.

It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects, and do not represent a specific ordering of objects. Understandably, "first\second\third 3" where permitted, the specific order or sequence may be interchanged such that the embodiments of the disclosure described herein can be practiced in sequences other than those illustrated or described herein.

DRAM is a semiconductor memory device commonly used in computers and consists of many repeating memory cells. In the process of data reading, the data signal of each storage unit is sequentially read through the local data line, the global data line and the data bus; in the process of data writing, the data signal of each storage unit is sequentially passed through the data bus , the global data line and the local data line are written into the storage unit.

Referring to FIG. 1 , it shows a schematic diagram of a partial structure of a DRAM provided by an embodiment of the present disclosure. As shown in Figure 1, the core of DRAM is memory array, sense amplifier (Sense amplifier, Sa) array, row decoding and control (XDEC) circuit, column decoding and control (YDEC) circuit, sense amplifier (SSA) circuit and Write Driver (Write Driver) circuit, read amplifier circuit and write driver circuit are collectively referred to as SSA&Write Driver circuit.

The memory array is composed of a large number of memory cells (or cells), and the selected memory cells can be read, written, or refreshed through word lines (Word Line, WL) and bit lines (Bit Line, BL). . Specifically, by giving the word line signal through the row decoding and control circuit, all the memories in the target word line can be activated, and then giving the bit line signal (or called CSL signal) through the column decoding and control circuit , to write, read or refresh data to the target storage unit. Generally, the sense amplifier array can be further divided into an odd array of sense amplifiers and an even array of sense amplifiers, which are used to control odd word lines and even word lines respectively.

Zoom in on the part of the shaded box in Figure 1, and its structure is shown in Figure 2. The working process of the DRAM will be described below in conjunction with FIG. 2 .

(1) When data is refreshed, when the target word line is selected via the XDEC circuit, the data is transmitted to the Sa arrays on the upper and lower sides, amplified by the Sa array, and then written back to the memory cells connected to the selected word line.

(2) When the data needs to be changed/written, after the target word line is selected by the XDEC circuit, the designated sense amplifier is selected by the YDEC circuit, and the data to be written is transmitted from the data bus, and enters the global data line through the write drive circuit to form The Gdata&Gdata# signal is then transmitted to the local data line by the read-write conversion (lrwap) circuit to form the Ldata&Ldata# signal (indicated as Ldat&Ldat# in the figure), and then written to the storage unit connected to the sense amplifier through the selected sense amplifier.

(3) When data is read, after the target word line is selected by the XDEC circuit, the designated sense amplifier is selected by the YDEC circuit, and the target memory unit transmits the data to the local data line through the sense amplifier to form Ldata&Ldata# (shown as Ldat&Ldat#) signal is then transmitted to the global data line by the local read-write conversion (lrwap) circuit to form the Gdata&Gdata# signal, and the Gdata&Gdata# signal is amplified by the read amplifier circuit and then transmitted to the data bus.

In the above process, the output signal of the write drive circuit and the input signal of the read amplifier circuit are habitually referred to as Yio&Yio# signals, that is, Yio&Yio# signals are equivalent to Gdata&Gdata# signals. Taking reading data as an example, the Yio&Yio# signal needs to be transmitted from the global data line to the data bus through the read amplifier circuit.

It should be understood that in the above process, the entire circuit uses a pair of YIO signals (or called double-ended YIO signals), that is, Yio&Yio# signals, and Yio&Yio# is a two-phase paired manner, both in the mode of reading data or writing data. in opposite complementary polarity. In addition, the whole circuit can use a single-ended YIO signal, and the working principle is basically the same.

The read amplifier circuit and the write drive circuit are explained in detail below by taking the double-terminal YIO signal as an example.

As shown in Figure 1, the Yio&Yio# signal has many pairs, from Yio<0>&Yio#<0> to Yio<n>&Yio#<n>. Here, n is a positive integer. Exemplarily, n=135, indicating that there are 136 data buses in the entire circuit, half of the data is associated with the odd Sa array, and half of the data is associated with the even Sa array. A pair of Yio&Yio# signals connected to the array, and a pair of Yio&Yio# signals connected to the even Sa array.

Referring to FIG. 3 , it shows a schematic structural diagram of a write driving circuit provided in the related art. As shown in Figure 3, the write drive circuit receives the EQ signal (precharge signal), WrEn signal (write input control signal) and Data signal (data signal) from the data bus, and outputs YIO according to the EQ signal, WrEn signal and Data signal signal, and pass the YIO signal into the global data line.

Referring to FIG. 4 , it shows a schematic structural diagram of a sense amplifier circuit provided in the related art. As shown in Figure 4, the read amplifier circuit receives the YIO signal and reference signal (composed of VSS signal, VCC signal, YIO_REF<1> signal and YIO_REF<0> signal) from the global data line, and performs YIO signal and reference signal Amplify to get the YIOloc signal and YIONloc signal, and transmit the YIOloc signal and YIONloc signal to the data bus. In addition, FIG. 4 also includes a Com signal and a Com control circuit for controlling the Com signal. The Com control circuit receives a control signal (such as YIO_EN(rdEn)/EQN, power signal VCC) and outputs a Com signal. Here, the Com control circuit is mainly used to play a control role in different working sequence stages of the DRAM, but during the signal amplification process of the read amplifier circuit, the Com signal is in a ground state. In other words, in the technical process of the present disclosure, the Com signal is equivalent to the ground signal.

In addition, after the read amplifier circuit obtains the YIOloc signal and the YIONloc signal, it will output the YIOloc signal and the YIONloc signal to the data bus through the output driving circuit. Referring to FIG. 5 , it shows a schematic structural diagram of an output driving circuit provided in the related art. As shown in Figure 5, the output drive circuit includes a first output drive circuit and a second output drive circuit, the first output drive circuit receives the YIONloc signal, outputs data signals such as Data, Data_N, and determines the reset signal Rst; the second output drive circuit Receive YIOloc signal, output data signal such as Data, Data_N. Here, the data signals such as Data and Data_N are signals transmitted to the data bus, and the reset signal Rst is not related to the working principle of the embodiment of the present disclosure, so no further explanation is given.

For the above read amplifier circuit, the time required for signal induction amplification (Sense) is relatively long, which leads to a decrease in the performance of the DRAM.

An embodiment of the present disclosure provides a sensitive amplifying circuit. The sensitive amplifying circuit includes a discharge circuit and a signal amplifying circuit, and the signal amplifying circuit includes a first cross-coupling tube group and a second cross-coupling tube group. The discharge circuit is connected to the first Between the cross-coupling tube group and the second cross-coupling tube group; wherein, the discharge circuit is used to receive the signal to be transmitted and the reference signal, and perform discharge processing based on the signal to be transmitted and the reference signal respectively to obtain the signal to be processed; the signal amplification circuit , which is used to amplify the signal to be processed to obtain the target amplified signal. In this way, the embodiments of the present disclosure provide a new sensitive amplifying circuit, and the discharge circuit is arranged between two pairs of cross-coupled tube groups, which can shorten the time required for the sensitive amplifying process, and further improve the performance of the DRAM.

Various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

In an embodiment of the present disclosure, refer to FIG. 6 , which shows a schematic structural diagram of a sensitive amplifier circuit 10 provided by an embodiment of the present disclosure. As shown in Figure 6, the sensitive amplifying circuit 10 includes a discharge circuit 101 and a signal amplifying circuit, and the signal amplifying circuit includes a first cross-coupling tube group 1021 and a second cross-coupling tube group 1022, and the discharge circuit 101 is connected to the first cross-coupling tube group Between the group 1021 and the second cross-coupling tube group 1022; wherein,

The discharge circuit 101 is configured to receive a signal to be transmitted and a reference signal, and perform discharge processing based on the signal to be transmitted and the reference signal respectively to obtain a signal to be processed;

The signal amplification circuit is used to amplify the signal to be processed to obtain the target amplified signal.

It should be noted that the sensitive amplifying circuit 10 in the embodiment of the present disclosure is applied to various signal amplification scenarios, such as DRAM, Static Random-Access Memory (SRAM), Synchronous Dynamic Random Access Memory (Synchronous Dynamic Random Access Memory) Memory, SDRAM), etc., those skilled in the art can apply it flexibly.

For the convenience of description, the application scenario in which the sense amplifier circuit in the DRAM is the sense amplifier circuit 10 is taken as an example for explanation below, but this does not constitute a limitation to the embodiments of the present disclosure.

According to the foregoing, in the process of reading data in DRAM, the transmission path of the data signal of the storage unit (Cell) is: local data line-read-write conversion (lrwap) circuit-global data line-read amplifier circuit (i.e. sensitive amplifier circuit 10 )-Data Bus.

For the sensitive amplifying circuit 10, the input signal is called the signal to be transmitted (YIO signal), and the output signal is called the target amplified signal. Specifically, the sensitive amplification circuit 10 includes a discharge circuit 101 and a signal amplification circuit. The discharge circuit 101 performs discharge processing based on the signal to be transmitted and the reference signal respectively to obtain a signal to be processed; the signal amplification circuit amplifies the signal to be processed to obtain a target amplified signal.

In the related art, as shown in FIG. 4 , the signal amplifying circuit includes two cross-coupling tube groups, and the discharge circuit is connected below the two cross-coupling tube groups. In the embodiment of the present disclosure, as shown in FIG. 6, the signal amplifying circuit includes a first cross-coupling tube group 1021 and a second cross-coupling tube group 1022, and the discharge circuit 101 is connected to the first cross-coupling tube group 1021 and the second cross-coupling tube group 1021 and the second cross-coupling tube group 1022. Between tube groups 1022. In this way, the embodiments of the present disclosure provide a brand new sense amplifier circuit, which can shorten the time of sense amplifier (Sense), improve the amplification performance of the sense amplifier circuit, and further improve the performance of the DRAM.

It should also be noted that the sensitive amplifying circuit 10 can amplify a single-ended signal (YIO signal), and can also amplify a double-ended signal (Yio&Yio# signal). In the scenario of amplifying a single-ended signal (YIO signal), the signal to be transmitted is a YIO signal, and the reference signal is a signal with a fixed level value; in the scenario of amplifying a double-ended signal (Yio&Yio# signal), the signal to be transmitted The signal may be a Yio signal, and the reference signal may be a Yio# signal; or, the signal to be transmitted may be a Yio# signal, and the reference signal may be a Yio signal.

In the embodiments of the present disclosure, an application scenario of single-ended signal amplification is used for subsequent description, but this does not constitute a limitation to the embodiments of the present disclosure. For the application scenario of double-ended signal amplification, it can be implemented by referring to the explanation and related principles of single-ended signal amplification.

In some embodiments, refer to FIG. 7 , which shows a schematic structural diagram of another sensitive amplifier circuit 10 provided by an embodiment of the present disclosure. As shown in Figure 7, the discharge circuit 101 includes a first discharge sub-circuit 1011 and a second discharge sub-circuit 1012; wherein,

The first discharge sub-circuit 1011 is used to receive the signal to be transmitted (YIO), and perform discharge processing based on the signal to be transmitted to obtain the first signal to be processed;

The second discharge sub-circuit 1012 is configured to receive a reference signal, and perform discharge processing based on the reference signal to obtain a second signal to be processed;

The signal amplification circuit is specifically used to amplify the first signal to be processed to obtain a first target amplified signal; and amplify the second signal to be processed to obtain a second target amplified signal.

It should be noted that the discharge circuit 101 includes two discharge paths, namely a first discharge sub-circuit 1011 and a second discharge sub-circuit 1012 . The first discharge sub-circuit 1011 is used for performing discharge processing according to the signal to be transmitted (YIO) to obtain a first signal to be processed, and the second discharge sub-circuit 1012 is used for performing discharge processing according to a reference signal to obtain a second signal to be processed.

Here, the difference in the level state between the signal to be transmitted (YIO) and the reference signal will cause the discharge speed of the discharge path to be different, resulting in a small difference between the first signal to be processed and the second signal to be processed, the small difference It will be captured and amplified by the signal amplification circuit, so that the signal level with higher level among the first signal to be processed and the second signal to be processed is higher, and the signal level with lower level is lower, and finally the first A target amplified signal (YIONloc) and a second target amplified signal (YIOloc). In this way, by designing two discharge paths in the discharge circuit 101 , the level state difference between the signal to be transmitted and the reference signal can be quickly compared, thereby realizing the signal amplification process.

Here, the reference signal can be composed of multiple signals with the same level state, or multiple signals with different level states, and the level state of the reference signal can be considered as the average value of the multiple signals.

It should be understood that <1> is indicated when the signal to be transmitted (YIO) is in the first level state, <0> is indicated when the signal to be transmitted (YIO) is in the second level state, and the reference signal is fixed at the first level state and the intermediate value of the second level state. In this way, if the level state of the signal to be transmitted is higher than the level state of the reference signal, it will be judged that the signal to be transmitted indicates <1> through the process of discharge and signal amplification; otherwise, if the level state of the signal to be transmitted is lower than the reference signal The level state of the signal, then through the process of discharge and signal amplification, it is judged that the signal to be transmitted indicates <0>.

In some embodiments, please refer to FIG. 8 , which shows a detailed structural schematic diagram of a sense amplifier circuit 10 provided by an embodiment of the present disclosure. As shown in FIG. 8 , the first discharge sub-circuit 1011 is provided with a first connection terminal on the side close to the first cross-coupling tube group 1021 , and the first discharge sub-circuit 1011 is provided on the side close to the second cross-coupling tube group 1022 set with a second connection end;

The first discharge sub-circuit 1011 includes a first crystal 201 (a = 4 is used as an example in FIG. 8 for illustration), and the respective first pins of the a first transistors 201 are connected to the signal to be transmitted (YIO), a The respective third pins of the first transistors 201 are connected to the second connection end;

The respective second pins of a first transistor 201 are connected to the first connection terminal, and the first connection terminal is used for outputting the first signal to be processed, or for outputting the first target amplified signal (YIONloc).

Similarly, in some embodiments, the second discharge sub-circuit 1012 is provided with a third connection terminal on a side close to the first cross-coupling tube group 1021, and the second discharge sub-circuit 1012 is provided on a side close to the second cross-coupling tube group 1022 One side is provided with a fourth connection end;

The second discharge sub-circuit 1012 includes b second transistors 202 (a=4 is used as an example in FIG. 8 for illustration), and the respective first pins of the b second transistors 202 are connected to the reference signal, and the b second transistors The respective third pins of 202 are connected to the fourth connection end;

The second pins of each of the b second transistors 202 are connected to the third connection end, and the third connection end is used for outputting the second signal to be processed, or for outputting the second target amplified signal (YIOloc).

It should be noted that the positions of the first connection end, the second connection end, the third connection end and the fourth connection end are shown in FIG. 8 .

The first discharge sub-circuit 1011 includes a first transistors 201 in a parallel state, the first terminals of the a first transistors 201 are used to receive the signal to be transmitted (YIO), and the second terminals of the a first transistors 201 are common It is used to output the first signal to be processed/the first target amplified signal (YIONloc). The second discharge sub-circuit 1012 includes b second transistors 202 connected in parallel, the first ends of the b second transistors 202 are used to receive the signal to be transmitted, and the second ends of the b second transistors 202 are used to output The second signal to be processed/the second target amplified signal (YIOloc).

In the embodiment of the present disclosure, for the first transistor and the second transistor, the first terminal is the gate of the transistor, which can control the on/off of the transistor; from the second end to the third end. Here, if the voltage at the first terminal is higher, the current speed of the transistor is faster, so the discharge speed is faster.

Taking the level state of the signal to be transmitted (YIO) greater than the reference signal as an example, the specific process of signal amplification is described.

It should be understood that, before the signal amplification starts, the initial level states of the first connection end and the third connection end are the same, and the initial level states of the second connection end and the fourth connection end are also the same. After the signal amplification starts, because the signal to be transmitted (YIO) is greater than the level state of the reference signal, the discharge speed of the first discharge sub-circuit is higher than that of the second discharge sub-circuit, so the voltage drop speed of the first connection terminal is higher than that of the second discharge sub-circuit. The voltage drop speed of the third connection end, the level state of the first connection end is slightly lower than the level state of the third connection end, at this time the first connection end can be considered as outputting the first signal to be processed, and the third connection end can be considered as output Wait for the second signal to be processed; finally, the first signal to be processed and the second signal to be processed are amplified by the amplifying circuit, so that the level state at the first connection end continues to drop, so that the fourth transistor 204 is turned on, thereby realizing the first The level state at the three connection terminals continues to rise until the difference between the level states at the first connection terminal and the third connection terminal meets the requirements. At this time, the first connection terminal can be regarded as outputting the first target amplified signal (YIONloc). The two connection terminals can be regarded as outputting a signal to be amplified by the second target (YIOloc).

It should be noted that when the level state of the signal to be processed (YIO signal) is higher than the level state of the reference signal, the level state of the first target amplified signal (YIONloc) is lower than the second target amplified signal (YIOloc); In case the level state of the signal to be processed (YIO) is lower than that of the reference signal, the level state of the first target amplified signal (YIONloc) is higher than that of the second target amplified signal (YIOloc).

It should be noted that the number of transistors in the first discharge sub-circuit 1011 and the second discharge sub-circuit 1012 needs to be designed according to the actual application scenario, a and b are both positive integers, and a and b can be the same or different, that is, the first The number of transistors in the first discharge sub-circuit 1011 and the number of transistors in the second discharge sub-circuit 1012 may be the same or different, which need to be determined according to actual application scenarios. In particular, when a=b, the first discharge sub-circuit 1011 and the second discharge sub-circuit 1012 have a symmetrical structure, which can balance hardware errors in the two discharge paths, and bring better amplification performance to the sensitive amplifier circuit 10 .

In a specific embodiment, as shown in FIG. 8, a=b=4, that is, the first discharge sub-circuit 1011 includes four first transistors 201, and the first terminals of these four transistors are all connected to the signal to be transmitted ( YIO) connection, which is equivalent to introducing four identical signals to be transmitted (YIO); the second discharge sub-circuit 1012 includes four second transistors 202, and these four transistors are respectively connected to four reference signals.

Here, the four reference signals may all be the same signal, or may be different signals. Exemplarily, the reference signal may include a first reference signal (YIO_REF<1>), a second reference signal (YIO_REF<0>), a third power supply signal (VCC) and a ground signal (VSS), and four second transistors 202 Including the second first transistor, the second second transistor, the second third transistor and the second fourth transistor; wherein, as shown in FIG. 8, the first pin of the second first transistor is connected to the first reference signal (YIO_REF<1>) , the first pins of the second and second transistors are connected to the second reference signal (YIO_REF<0>), the first pins of the second and third transistors are connected to the third power signal (VCC), and the first pins of the second and fourth transistors The pin is connected to the ground signal (VSS).

In this way, the first discharge sub-circuit 1011 and the second discharge sub-circuit 1012 have a symmetrical structure. On the one hand, they can balance the errors produced in the manufacturing process and reduce the amplification margin of the sensitive amplifier circuit 10 caused by matching defects (Mismatch) in the manufacturing process. On the other hand, it can reduce the influence of noise on the amplification margin (Sense Margin), compare the level state difference between the signal to be transmitted and the reference signal more accurately, and improve the sensitivity of the sense amplifier. accuracy.

In particular, specifications of the four first transistors may be the same or different; specifications of the four second transistors may be the same or different.

In a specific embodiment, as shown in FIG. 8 , the first cross-coupled transistor group 1021 includes a third transistor 203 and a fourth transistor 204; wherein, the first pin of the third transistor 203 and the pin of the fourth transistor 204 Both the third pins are connected to the third connection end; the third pins of the third transistor 203 and the first pins of the fourth transistor 204 are connected to the first connection end; the second pins of the third transistor 203 are connected to the first connection end. A power signal is connected, and the second pin of the fourth transistor 204 is connected to the second power signal.

In some embodiments, as shown in FIG. 8 , the second cross-coupled transistor group 1022 includes a fifth transistor 205 and a sixth transistor 206; wherein, the first pin of the fifth transistor 205 is connected to the third connection end, and the sixth transistor 205 The first pin of the transistor 206 is connected to the first connection end; the second pin of the fifth transistor 205 is connected to the second connection end, and the second pin of the sixth transistor 206 is connected to the fourth connection end; the fifth transistor 205 The third pin of the transistor 206 and the third pin of the sixth transistor 206 are both connected to the ground signal.

It should be noted that each of the first cross-coupling transistor group 1021 and the second cross-coupling transistor group 1022 is composed of a pair of transistors, and their connection mode is shown in FIG. 8 .

The first cross-coupling tube group 1021 and the second cross-coupling tube group 1022 can amplify the difference between the first signal to be processed and the second signal to be processed, thereby obtaining the first target amplified signal (YIONloc) and the second target amplified signal ( YIOloc). In addition, both the first cross-coupling tube group 1021 and the second cross-coupling tube group 1022 are classic cross-coupling amplifier devices, and their specific amplification principles will not be described in detail.

In this way, in the embodiment of the present disclosure, the first discharge sub-circuit discharges based on the signal to be transmitted (YIO) to obtain the first signal to be processed; the second discharge sub-circuit discharges based on the reference signal to obtain the second signal to be processed; The amplifying circuit amplifies the first signal to be processed and the second signal to be processed to obtain a first target amplified signal (YIONloc) and a second target amplified signal (YIOloc).

In some embodiments, the sense amplifier circuit 10 further includes a reference output circuit 103 for outputting a reference signal. According to the foregoing, the reference signal includes the first reference signal (YIO_REF<0>), the second reference signal (YIO_REF<1>), the ground signal VSS and the power signal VCC, so the reference output circuit 103 includes the first reference output circuit 1031 and The second reference output circuit 1032 is used to output the first reference signal (YIO_REF<0>) and the second reference signal (YIO_REF<1>) respectively. It should be understood that the power signal and the ground signal can be directly input through the power terminal/ground terminal.

Referring to FIG. 9 , it shows a schematic structural diagram of a reference output circuit 103 provided by an embodiment of the present disclosure. As shown in FIG. 9, the reference output circuit 103 may include:

The first reference output circuit 1031 is configured to receive a first control signal (CM_SESA<0>), and output a first reference signal (YIO_REF<0>) according to the first control signal;

The second reference output circuit 1032 is configured to receive a second control signal (CM_SESA<1>), and output a second reference signal (YIO_REF<1>) according to the second control signal.

It should be noted that various fixed or sporadic defects may occur during the manufacturing process of the sensitive amplifier circuit 10 , thus causing hardware errors in the first discharge sub-circuit and the second discharge sub-circuit. Therefore, in the embodiment of the present disclosure, a first reference output circuit 1031 and a second reference output circuit 1032 are also provided, which respectively output corresponding reference signals according to corresponding control signals. Here, if a parameter error occurs in the first discharge sub-circuit 1011 and the second discharge sub-circuit 1012, the first control signal (CM_SESA<0>)/second control signal (CM_SESA<0>) can be adjusted through the test mode (Test Mode). 1>), and then adjust the level state of the first reference signal (YIO_REF<0>) and the second reference signal (YIO_REF<1>), and then compensate the error caused by the process, and correct the sensitive amplifier circuit Amplify the margin (Sense Margin), thereby ensuring the performance of the sensitive amplifier circuit. Generally speaking, the adjustment of the first control signal and the second control signal only takes place before leaving the factory or during maintenance, and is generally fixed during normal use by the user, otherwise it may easily cause system downtime.

In a specific embodiment, the first reference output circuit 1031 includes a seventh transistor 207, an eighth transistor 208, and a ninth transistor 209; wherein,

The first pin of the seventh transistor 207 is connected to the first pin of the eighth transistor 208 for receiving the first control signal (CM_SESA<0>);

The third pin of the seventh transistor 207 is connected to the second pin of the eighth transistor 208 and the first pin of the ninth transistor 209 for outputting the first reference signal (YIO_REF<0>);

The second pin of the seventh transistor 207 is connected to the fourth power supply signal (VCCZ), the third pin of the eighth transistor 208 is connected to the ground signal (VSSZ), and the second pin and the third pin of the ninth transistor 209 Both are connected to the ground signal.

In addition, the second reference output circuit 1032 includes a tenth transistor 210, an eleventh transistor 211 and a twelfth transistor 212;

The first pin of the tenth transistor 210 is connected to the first pin of the eleventh transistor 211 for receiving the second control signal (CM_SESA<1>);

The third pin of the tenth transistor 210 is connected to the second pin of the eleventh transistor 211 and the first pin of the twelfth transistor 212 for outputting the second reference signal (YIO_REF<1>);

The second pin of the tenth transistor 210 is connected to the fifth power supply signal (VCCZ), the third pin of the eleventh transistor 211 is connected to the ground signal (VSSZ), the second pin of the twelfth transistor 212 is connected to the third The pins are all connected to the ground signal.

Generally, the seventh transistor 207 and the tenth transistor 210 are P-type transistors. In the embodiment of the present disclosure, the first reference output circuit 1031 and the second reference output circuit 1032 are both arranged on the reference signal side, which has the advantage of selecting between the power signal VCCZ/ground signal VSSZ, and the potential is relatively fixed. If they are placed on both sides of the reference signal and the signal to be transmitted, the disadvantages are: on the side of the signal to be transmitted, when the YIO signal is discharged to a very low level, the P-type transistor has poor ability to control and transmit low potential, and the efficiency is not high. Moreover, it is susceptible to interference, and the actual control efficiency will be lower than expected.

In some embodiments, in order to ensure that the first connection terminal and the third connection terminal are in the same level state before the amplification process starts, the sensitive amplifier circuit 10 also needs to be provided with a pre-charging circuit. The pre-charging circuit is used for receiving the pre-charging signal, and pre-charging the discharging circuit 101 and the signal amplifying circuit based on the pre-charging signal, so that both the first connection end and the third connection end are in a preset level state.

It should be noted that the input of the pre-charging circuit is the pre-charging signal (EQ), and when the pre-charging signal (EQ) is valid, the pre-charging circuit will pre-charge the first connection terminal and the second connection terminal to a preset level state. Here, the preset level state can be determined according to actual application scenarios.

In a specific embodiment, referring to FIG. 8 , the precharge circuit includes a thirteenth transistor 213, a fourteenth transistor 214, and a fifteenth transistor 215; wherein,

The respective first pins of the thirteenth transistor 213, the fourteenth transistor 214 and the fifteenth transistor 215 are all connected to the precharge signal (EQ);

The second pin of the thirteenth transistor 213 is connected to the sixth power signal, and the second pin of the fourteenth transistor 214 is connected to the seventh power signal;

The third pin of the thirteenth transistor 213 and the second pin of the fifteenth transistor 215 are all connected to the first connection terminal; the third pin of the fourteenth transistor 214 and the third pin of the fifteenth transistor 215 are connected to the third connection end.

In the related art, as shown in Figure 4, since the discharge circuit is located under two pairs of cross-coupled transistors, the pre-charge circuit needs to include two parts: the first part includes three pre-charge transistors, located above the first pair of cross-coupled transistors, and the second The part consists of 2 pre-charge transistors located outside the second pair of cross-coupled transistors.

It should be understood that, during the working process of the DRAM, the level state of the YIO signal will be reset to a fixed value (VCC) after each read operation. In the embodiment of the present disclosure, the discharge circuit 101 is located between two pairs of cross-coupled transistors. After the read operation is completed, since the level state of the YIO signal is a fixed value (VCC), the two discharge paths in the discharge circuit will be at this time. The conduction state, so the overall circuit can be precharged by the 3 precharge tubes in the first part of the precharge circuit.

That is to say, as shown in FIG. 8, the sensitive amplifying circuit provided by the embodiment of the present disclosure can save the two pre-charging tubes in the second part of the pre-charging circuit (that is, the part framed by the dotted line in FIG. 4), which is sensitive to the whole As far as the amplifier circuit is concerned, due to the reduction in the number of pre-charge tubes, the total capacitance of the discharge path during the sensitive amplification process is small, and the time required for discharge is reduced, thereby shortening the time required for the signal amplification (Sense) process.

In addition, in the embodiments of the present disclosure, due to the reduction in the number of pre-charging tubes, the time required for the pre-charging process will inevitably increase, and this problem can be solved by adjusting the performance parameters of the pre-charging tubes.

In the foregoing, the first transistor 201, the second transistor 202, the fifth transistor 205, the sixth transistor 206, the eighth transistor 208, the ninth transistor 209, the eleventh transistor 211 and the twelfth transistor 212 are N-type channel A field effect transistor; the third transistor 203, the fourth transistor 204, the seventh transistor 207, the tenth transistor 210, the thirteenth transistor 213, the fourteenth transistor 214 and the fifteenth transistor 215 are P-type channel field effect transistors;

Wherein, the first pin of the N-type field effect transistor is the gate pin, the second pin of the N-type field effect transistor is the drain pin, and the third pin of the N-type field effect transistor is the source Pins, the first pin of the P-type field effect transistor is the gate pin, the second pin of the P-type field effect transistor is the source pin, and the third pin of the P-type field effect transistor is the drain pole pins.

In addition, in the foregoing content, the first power signal to the seventh power signal may have the same level state, or may have different level states, which need to be determined according to actual application scenarios.

In addition, the sensitive amplifier circuit 10 further includes an output driving circuit 104 . In some embodiments, refer to FIG. 10 , which shows a schematic structural diagram of an output driving circuit 104 provided by an embodiment of the present disclosure. As shown in Figure 10, the output drive circuit 104 is used to receive the first target amplified signal (YIONloc) and the second target amplified signal (YIOloc), and the first target amplified signal (YIONloc) and the second target amplified signal (YIOloc) ) to perform drive processing and output a target data signal (Data).

It should be noted that the output terminal of the output driving circuit 104 is connected to the data bus, and is used to determine the target data signal (Data) according to the first target amplified signal (YIONloc) and the second target amplified signal (YIOloc), and convert the target data The signal (Data) is output to the data bus.

Exemplarily, when the level state of the first target amplified signal is lower than the level state of the second target amplified signal, the level state of the target data signal is the first level state; When the level state is higher than the level state of the second target amplified signal, the level state of the target data signal is the second level state.

In a specific embodiment, the output driving circuit 104 includes a first output driving sub-circuit 1041 and a second output driving sub-circuit 1042; the first output driving sub-circuit 1041 includes a first inverter and a first crystal group, the second The two-output driving sub-circuit 1042 includes a second inverter and a second transistor group; wherein;

The input end of the first inverter is connected to the first connection end, and the output end of the first inverter is connected to the first transistor group; the input end of the second inverter is connected to the third connection end, and the second inverter The output end of the phaser is connected with the second transistor group.

It should also be noted that, as shown in FIG. 10 , the first output driver circuit 1041 includes a first inverter and a first transistor group for receiving the first target amplified signal (YIONloc) and outputting the target data signal (Data) and the inverted data signal (Data_N); the second output drive circuit 1042 includes a second inverter and a second transistor group for receiving the second target amplified signal (YIOloc), and outputting the target data signal (Data) and the inverted Data signal (Data_N) for subsequent use.

In addition, compared with the related art (see FIG. 5 ), the first output driving circuit 1041 and the second output driving circuit 1042 each additionally include an inverter, and the first target amplified signal (YIONloc) and the second target amplified signal ( YIOloc) respectively pass through the inverter and enter the subsequent transistors, thereby ensuring that the capacitances on the output terminals YIONloc and YIOloc of the signal amplification circuit are consistent, and optimizing the problem of inconsistent loads at the output terminals.

Exemplarily, as shown in FIG. 10 , for the first output driver circuit 1041 , the first transistor group includes a transistor 301 , a transistor 302 , a transistor 303 , a transistor 304 , a transistor 305 and a transistor 306 . The first end of the transistor 301 is connected with the output end of the first inverter, the third end of the transistor 301 is connected with the second end of the transistor 305, and the third end of the transistor 305 is connected with the second end of the transistor 306; The third terminal is connected to the ground signal; the second terminals of the transistor 302 , the transistor 303 and the transistor 304 are respectively connected to the power signal.

The second end of the transistor 301, the third end of the transistor 302, the third end of the transistor 303, and the third end of the transistor 304 form a connection point, and are used to output the target data signal (Data); the first end of the transistor 302 is connected to The first end of the transistor 301 and the first end of the transistor 303 are connected to the first end of the transistor 305 for outputting an inverted data signal (Data_N).

In addition, the first terminal of the transistor 304 is connected to the first terminal of the transistor 306 and is used to determine the reset signal (Rst). Here, the Rst signal is used for a reset process, which is not closely related to the technical solutions of the embodiments of the present disclosure, and will not be explained too much.

Here, the transistor 301 , the transistor 305 and the transistor 306 are N-type field effect transistors, the transistor 302 , the transistor 303 and the transistor 304 are P-type field effect transistors, and the first terminal of the P-type field effect transistor is a gate pin. In the disclosed embodiment, the second end of the P-type field effect transistor is a source pin, the third end of the P-type field effect transistor is a drain pin, and the first end of the N-type field effect transistor is a gate Pins, the second end of the N-type field effect transistor is a drain pin, and the third end of the N-type field effect transistor is a source pin.

Exemplarily, as shown in FIG. 10 , for the second output driver circuit 1042 , the second transistor group includes a transistor 307 , a transistor 308 , a transistor 309 and a transistor 310 . Wherein, the first end of the transistor 307 is connected with the output end of the second inverter and the first end of the transistor 308, and the second end of the transistor 308 and the transistor 309 are respectively connected with the power signal; the third end of the transistor 307 and the transistor 310 The second terminal of the transistor 310 is connected to the ground, and the third terminal of the transistor 310 is grounded.

The second end of the transistor 307, the third end of the transistor 308, and the third end of the transistor 309 form a connection point, and are used to output the target data signal (Data); the first end of the transistor 309 is connected to the first end of the transistor 310 and Used to output the inverted data signal (Data_N).

Here, the transistor 307 and the transistor 310 are N-type field effect transistors, and the transistor 308 and the transistor 309 are P-type field effect transistors.

Please refer to FIG. 11 , which shows a specific structural schematic diagram of another sensitive amplifier circuit 10 provided by an embodiment of the present disclosure. The difference between Figure 11 and Figure 8 is that there is an additional Com control circuit in Figure 11, the Com control circuit can receive some control signals such as YIO_EN, EQN, and power signal VCC, and obtain the Com signal after some logic processing.

Here, the Com control circuit is used to play a control role in different working stages, that is, output the Com signal according to YIO_EN, EQN, VCC, etc., and the Com signal is the ground signal during the signal amplification (Sense) process of the entire sensitive amplifier circuit 10 .

For FIG. 11 , the sensitive amplifying circuit 10 in the embodiment of the present disclosure has at least the following advantages:

(1) After each read, the level state of the YIO signal will be reset to VCC, so in the process of reset (Reset), the left and right discharge sub-circuits (discharge Path) in the sensitive amplifier circuit will be in the In the conduction state, the Com control circuit can also be charged through the top three pre-charging tubes.

(2) Compared with the related technology, the sensitive amplifier circuit 10 moves the discharge Path to the middle of the 4 transistors of cross-coupling (Cross-Coupling), thus saving two pre-charge tubes (the place framed by the dotted line in Fig. 4), like this The total capacitance of the discharge path can be reduced, and the circuit area is reduced, so the sense amplifier circuit 10 can shorten the time required for the Sense process.

(3) The sensitive amplifier circuit is respectively connected with two inverters (Inv) after outputting YIONloc and YIOloc, that is, the first inverter in the first output drive circuit and the second inverter in the second output drive circuit , so that the capacitors on the output terminals YIONloc and YIOloc of the signal amplification circuit are consistent, and the inconsistency of the load at the optimized output terminal leads to the problem of deviation in the Sense Margin.

(4) Compared with the related technology, the sensitive amplifier circuit 10 has reduced two pre-charging tubes, the circuit layout (Layout) area is reduced, and the time consumed by the Sense process is shortened, but the consumption time of the pre-charging stage may be increased. .

In addition, for the circuit, due to the reduction of two EQ tubes, the pre-charging phase time after the end of Sense will be longer than the original structure, but this can be alleviated by appropriately increasing the pre-charging tube above. The problem. Moreover, this circuit can be used when the time of the Sense process is relatively tight, but the time of the pre-charging process is not very critical.

To sum up, the embodiment of the present disclosure provides a new sensitive amplifier circuit, the discharge circuit is arranged between two pairs of cross-coupled transistors in the signal amplifier circuit, and the number of pre-charge tubes is reduced, at least with the following advantage:

(1) Reduce the overall capacitance of the sensitive amplifier circuit by reducing the pre-charge tube, so that the total capacitance that needs to be discharged during the amplification process is reduced, the amplification speed is improved, and the time required for the amplification process is reduced.

(2) The two discharge paths in the sensitive amplifying circuit have a symmetrical structure, thereby reducing the deviation caused by the manufacturing process.

(3) The sensitive amplifier circuit adds a MOS CAP structure (that is, the first reference output circuit and the second reference output circuit) in the area susceptible to noise, thereby reducing the influence of noise.

(4) Since the sensitive amplifier circuit includes the first reference output circuit and the second reference output circuit, the level state of the first reference signal and the second reference signal can be adjusted in the test mode (Test Mode), and then the sensitive amplifier circuit can be adjusted Sensitive amplification performance, that is, the sensitive amplifier circuit introduces a structure with fuse control to adjust the Sense characteristics.

(5) Both the first reference output circuit and the second reference output circuit are set on the side of the reference signal. The advantage is that the potential is relatively fixed when selecting between VCCZ/VSSZ. If placed on both sides, the disadvantage is: on the input side, when the YIO signal is discharged to a very low level, the P-type transistor has poor ability to control and transmit low potential, the efficiency is not high, and it is susceptible to interference, and the actual control efficiency will be low. than expected.

(6) The sensitive amplification circuit adopts single-ended YIO signal for sensitive amplification, which can save YIO lines and power consumption.

An embodiment of the present disclosure provides a sensitive amplifying circuit, the sensitive amplifying circuit includes a discharge circuit and a signal amplifying circuit, and the signal amplifying circuit includes a first cross-coupling tube group and a second cross-coupling tube group, the discharge circuit is connected to the first cross Between the coupling tube group and the second cross-coupling tube group; wherein, the discharge circuit is used to receive the signal to be transmitted and the reference signal, and perform discharge processing based on the signal to be transmitted and the reference signal respectively to obtain the signal to be processed; the signal amplification circuit, It is used to amplify the signal to be processed to obtain the target amplified signal. In this way, the embodiments of the present disclosure provide a new sensitive amplifying circuit, and the discharge circuit is arranged between two pairs of cross-coupled tube groups, which can shorten the time required for the sensitive amplifying process, and further improve the performance of the DRAM.

In yet another embodiment of the present disclosure, refer to FIG. 12 , which shows a schematic structural diagram of a semiconductor memory 40 provided by an embodiment of the present disclosure. As shown in FIG. 12 , the semiconductor memory 40 includes the sensitive amplifier circuit 10 of any one of the foregoing embodiments.

In some embodiments, the semiconductor memory 40 includes at least a dynamic random access memory (DRAM).

In the embodiment of the present disclosure, the embodiment of the present disclosure provides a new sensitive amplifying circuit. The discharge circuit is arranged between two pairs of cross-coupled tube groups, which can shorten the time required for the sensitive amplifying process, thereby improving the performance of the DRAM. .

The above are only preferred embodiments of the present disclosure, and are not intended to limit the protection scope of the present disclosure.

It should be noted that in this disclosure, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article or apparatus comprising a set of elements includes not only those elements , but also includes other elements not expressly listed, or also includes elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus comprising that element.

The serial numbers of the above-mentioned embodiments of the present disclosure are for description only, and do not represent the advantages and disadvantages of the embodiments.

The methods disclosed in several method embodiments provided in the present disclosure can be combined arbitrarily without conflict to obtain new method embodiments.

The features disclosed in several product embodiments provided in the present disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

The features disclosed in several method or device embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

The above is only a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope of the present disclosure, and should cover all within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be determined by the protection scope of the claims.

Industrial Applicability

The embodiment of the present disclosure provides a new sensitive amplifying circuit. The discharge circuit is arranged between two pairs of cross-coupled tube groups, which can shorten the time required for the sensitive amplifying process, thereby improving the performance of the DRAM.

Claims (17)

1. A sensitive amplifying circuit, the sensitive amplifying circuit includes a discharge circuit and a signal amplifying circuit, and the signal amplifying circuit includes a first cross-coupling tube group and a second cross-coupling tube group, the discharging circuit is connected to the first Between the cross-coupling tube group and the second cross-coupling tube group; wherein,

   The discharge circuit is configured to receive a signal to be transmitted and a reference signal, and perform discharge processing based on the signal to be transmitted and the reference signal respectively to obtain a signal to be processed;

   The signal amplification circuit is used to amplify the signal to be processed to obtain a target amplified signal.
2. The sensitive amplifying circuit according to claim 1, wherein the discharge circuit comprises a first discharge sub-circuit and a second discharge sub-circuit; wherein,

   The first discharge sub-circuit is used to receive the signal to be transmitted, and perform discharge processing based on the signal to be transmitted to obtain a first signal to be processed;

   The second discharge sub-circuit is configured to receive the reference signal, and perform discharge processing based on the reference signal to obtain a second signal to be processed;

   The signal amplifying circuit is specifically configured to amplify the first signal to be processed to obtain a first target amplified signal; and amplify the second signal to be processed to obtain a second target amplified signal.
3. The sensitive amplifying circuit according to claim 2, wherein the first discharge sub-circuit is provided with a first connection terminal on a side close to the first cross-coupling tube group, and the first discharge sub-circuit is close to One side of the second cross-coupling tube set is provided with a second connection end;

   The first discharge sub-circuit includes a first transistors, and the respective first pins of the a first transistors are connected to the signal to be transmitted, and the respective third pins of the a first transistors are connected to the second connection end;

   The respective second pins of the a first transistors are connected to the first connection terminal, and the first connection terminal is used to output the first signal to be processed, or to output the first target amplified signal ;

   Among them, a is a positive integer.
4. The sensitive amplifying circuit according to claim 3, wherein, the second discharge sub-circuit is provided with a third connection terminal on a side close to the first cross-coupling tube group, and the second discharge sub-circuit is close to A fourth connection end is provided on one side of the second cross-coupling tube group;

   The second discharge sub-circuit includes b second transistors, and the respective first pins of the b second transistors are connected to the reference signal, and the respective third pins of the b second transistors are connected to The fourth connection end is connected;

   The respective second pins of the b second transistors are connected to the third connection terminal, and the third connection terminal is used to output the second signal to be processed, or to output the second target amplified signal ;

   Among them, b is a positive integer.
5. The sensitive amplifying circuit according to claim 4, wherein the first cross-coupled transistor group includes a third transistor and a fourth transistor; wherein,

   Both the first pin of the third transistor and the third pin of the fourth transistor are connected to the third connection terminal;

   Both the third pin of the third transistor and the first pin of the fourth transistor are connected to the first connection terminal;

   The second pin of the third transistor is connected to the first power signal, and the second pin of the fourth transistor is connected to the second power signal.
6. The sensitive amplifying circuit according to claim 5, wherein the second cross-coupled transistor group includes a fifth transistor and a sixth transistor; wherein,

   The first pin of the fifth transistor is connected to the third connection end, and the first pin of the sixth transistor is connected to the first connection end;

   The second pin of the fifth transistor is connected to the second connection terminal, and the second pin of the sixth transistor is connected to the fourth connection terminal;

   Both the third pin of the fifth transistor and the third pin of the sixth transistor are connected to the ground signal.
7. The sensitive amplifying circuit according to claim 4, wherein, when b is 4, the reference signals include a first reference signal, a second reference signal, a third power supply signal and a ground signal, and the b second The transistors include the second one transistor, the second two transistors, the second three transistors and the second four transistors; wherein,

   The first pin of the second first transistor is connected to the first reference signal, the first pin of the second second transistor is connected to the second reference signal, the first pin of the second third transistor is connected to the third The power supply signal is connected, and the first pins of the second and fourth transistors are connected to the ground signal.
8. The sensitive amplifying circuit according to claim 7, wherein the sensitive amplifying circuit further comprises a first reference output circuit and a second reference output circuit; wherein,

   The first reference output circuit is configured to receive a first control signal, and output the first reference signal according to the first control signal;

   The second reference output circuit is configured to receive a second control signal, and output the second reference signal according to the second control signal.
9. The sensitive amplifying circuit according to claim 8, wherein the first reference output circuit comprises a seventh transistor, an eighth transistor and a ninth transistor; wherein,

   The first pin of the seventh transistor is connected to the first pin of the eighth transistor for receiving the first control signal;

   The third pin of the seventh transistor is connected to the second pin of the eighth transistor and the first pin of the ninth transistor for outputting the first reference signal;

   The second pin of the seventh transistor is connected to the fourth power supply signal, the third pin of the eighth transistor is connected to the ground signal, and the second pin and the third pin of the ninth transistor are both connected to the ground signal connection.
10. The sensitive amplifying circuit according to claim 8, wherein the second reference output circuit comprises a tenth transistor, an eleventh transistor and a twelfth transistor;

    The first pin of the tenth transistor is connected to the first pin of the eleventh transistor for receiving the second control signal;

    The third pin of the tenth transistor is connected to the second pin of the eleventh transistor and the first pin of the twelfth transistor, and is used to output the second reference signal;

    The second pin of the tenth transistor is connected to the fifth power supply signal, the third pin of the eleventh transistor is connected to the ground signal, and the second pin and the third pin of the twelfth transistor are both Connect to ground signal.
11. The sensitive amplifying circuit according to claim 4, wherein the sensitive amplifying circuit further comprises a pre-charging circuit;

    The pre-charging circuit is configured to receive a pre-charging signal, and perform pre-charging processing on the discharging circuit and the signal amplifying circuit based on the pre-charging signal, so that the first connection end and the third connection terminals are at the preset level.
12. The sensitive amplifying circuit according to claim 11, wherein the pre-charging circuit comprises a thirteenth transistor, a fourteenth transistor and a fifteenth transistor; wherein,

    The respective first pins of the thirteenth transistor, the fourteenth transistor and the fifteenth transistor are all connected to the precharge signal;

    The second pin of the thirteenth transistor is connected to the sixth power signal, and the second pin of the fourteenth transistor is connected to the seventh power signal;

    Both the third pin of the thirteenth transistor and the second pin of the fifteenth transistor are connected to the first connection end; the third pin of the fourteenth transistor is connected to the third pin of the fifteenth transistor The pins are all connected to the third connection end.
13. The sensitive amplifying circuit according to claim 4, wherein the sensitive amplifying circuit further comprises an output drive circuit; wherein,

    The output drive circuit is configured to receive the first target amplified signal and the second target amplified signal, perform drive processing on the first target amplified signal and the second target amplified signal, and output a target data signal ;

    Wherein, when the level state of the first target amplified signal is lower than the level state of the second target amplified signal, the level state of the target data signal is the first level state; in the When the level state of the first target amplified signal is higher than the level state of the second target amplified signal, the level state of the target data signal is the second level state.
14. The sensitive amplifying circuit according to claim 13, wherein the output driving circuit comprises a first output driving sub-circuit and a second output driving sub-circuit; the first output driving sub-circuit comprises a first inverter and a first A transistor group, the second output driving subcircuit includes a second inverter and a second transistor group; wherein;

    The input end of the first inverter is connected to the first connection end, and the output end of the first inverter is connected to the first transistor group;

    The input end of the second inverter is connected to the third connection end, and the output end of the second inverter is connected to the second transistor group.
15. The sensitive amplifying circuit according to any one of claims 4-12, wherein,

    The first transistor, the second transistor, the fifth transistor, the sixth transistor, the eighth transistor, the ninth transistor, the eleventh transistor and the twelfth transistor are N-type channel field effect transistors; the third transistor, the fourth transistor, the The seventh transistor, the tenth transistor, the thirteenth transistor, the fourteenth transistor and the fifteenth transistor are P-type channel field effect transistors;

    Wherein, the first pin of the N-type field effect transistor is a gate pin, the second pin of the N-type field effect transistor is a drain pin, and the first pin of the N-type field effect transistor The three pins are source pins, the first pin of the P-type channel field effect transistor is a gate pin, the second pin of the P-type channel field effect transistor is a source pin, and the P The third pin of the trench field effect transistor is the drain pin.
16. A semiconductor memory, comprising the sensitive amplifier circuit according to any one of claims 1 to 15.
17. The semiconductor memory according to claim 16, wherein said semiconductor memory includes at least a dynamic random access memory.

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