CN115411035A

CN115411035A - Read circuit layout, structure and memory layout

Info

Publication number: CN115411035A
Application number: CN202110580308.8A
Authority: CN
Inventors: 杨正杰
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2021-05-26
Filing date: 2021-05-26
Publication date: 2022-11-29

Abstract

The embodiment of the application provides a reading circuit layout, a reading circuit structure and a reading circuit memory layout, wherein the reading circuit layout comprises the following components: the device comprises a reading amplification module, a first processing module and a second processing module which are arranged along a preset direction, wherein the reading amplification module is used for reading the voltage of a bit line, and the first processing module and the second processing module are at least used for carrying out noise elimination on an output signal of the reading amplification module; the first processing module comprises: the first offset elimination region, the first isolation region and the equalization region are arranged along a preset direction; the second processing module comprises: the pre-charging area, the second isolation area and the second offset elimination area are arranged along a preset direction; the active pattern of the first offset canceling area, the active pattern of the first isolation area and the active pattern of the equalizing area are arranged separately from each other, and the active pattern of the precharge area, the active pattern of the second isolation area and the active pattern of the second offset canceling area are arranged separately from each other, so that the influence of timing mismatch of the memory in the reading process is reduced.

Description

Read circuit layout, structure and memory layout

Technical Field

The present application relates to the field of semiconductor memory structure design, and in particular, to a read circuit layout, a read circuit structure, and a memory layout.

Background

A Dynamic Random Access Memory (DRAM) completes a data write operation to the Memory by storing charges in a capacitor of a Memory cell, and completes a data read operation to the Memory by reading charges in a capacitor of a Memory cell.

In the DRAM, memory cells are connected to a bit line BL and a complementary bit line BLB, and a sense amplifier in a sense circuit is used to sense a voltage of the bit line BL and a voltage of the complementary bit line BLB and amplify a voltage difference between the bit line BL and the complementary bit line BLB during a data sensing operation.

However, the applicant found that for the same sense amplifier structure in the readout circuit, the sharing of the active region in the same sense amplifier structure can cause the problem of timing misalignment during readout of the memory.

Disclosure of Invention

The embodiment of the application provides a read circuit layout, a read circuit structure and a memory layout, provides a design of an active pattern of an MOS (metal oxide semiconductor) transistor, avoids the problem of sharing an active region in the same sense amplifier structure, and improves the device performance of the MOS transistor in the read circuit of the memory, thereby reducing the influence of time sequence mismatch of the memory in the read process.

In order to solve the above technical problem, an embodiment of the present application provides a readout circuit layout, including: the device comprises a read-out amplification module, a first processing module and a second processing module which are arranged along a preset direction, wherein the read-out amplification module is used for reading the voltage of a bit line, and the first processing module and the second processing module are at least used for carrying out noise elimination on an output signal of the read-out amplification module; the first processing module includes: a first offset canceling region, a first isolation region and an equalizing region arranged in a preset direction, the first offset canceling region being configured to connect the bit line to the complementary read bit line, the first isolation region being configured to connect the bit line to the read bit line, the equalizing region being configured to connect the read bit line to the complementary read bit line; the second processing module comprises: a precharge region, a second isolation region, and a second offset canceling region arranged in a preset direction, the precharge region configured to precharge the sense bit line and the complementary sense bit line based on a precharge command, the second isolation region configured to connect the complementary bit line to the complementary sense bit line, the second offset canceling region configured to connect the complementary bit line to the sense bit line; the active pattern of the first offset canceling region, the active pattern of the first isolation region, and the active pattern of the equalizing region are separately disposed from each other, and the active pattern of the precharge region, the active pattern of the second isolation region, and the active pattern of the second offset canceling region are separately disposed from each other.

Compared with the prior art, for the MOS structure of the sense amplifier in the sense amplifier circuit layout, the active patterns of the first offset elimination region, the first isolation region and the equalization region in the first processing module are arranged separately, and the active patterns of the precharge region, the second isolation region and the second offset elimination region in the second processing module are arranged separately, so that the problem that the active regions of the first processing module and the second processing module in the same sense amplifier structure are shared is avoided, the device performance of an MOS tube in the sense amplifier circuit of the memory is improved, and the influence of time sequence mismatch of the memory in the sense amplifier process is reduced.

In addition, the sense amplifying module includes: the first NMOS area and the first PMOS area are arranged close to the first processing module, and the second NMOS area and the second PMOS area are arranged close to the second processing module; the first processing module, the first NMOS area, the first PMOS area, the second processing module, the second NMOS area and the second PMOS area are arranged along a preset direction; the active patterns of the first NMOS area and the second NMOS area are arranged independently, and the active patterns of the first PMOS area and the second PMOS area are arranged independently. The active patterns of the first NMOS area, the second NMOS area, the first PMOS area and the second PMOS area in the read-out amplification module are arranged independently, so that the problem that the active areas are shared in the same sense amplifier structure is further solved, and the device performance of an MOS (metal oxide semiconductor) tube in a read-out circuit of a memory is improved.

In addition, the active pattern of the first NMOS region and the active pattern of the second NMOS region are symmetrically arranged; the active pattern of the first PMOS region and the active pattern of the second PMOS region are symmetrically arranged. The MOS tubes in the same sensing amplifier are symmetrically arranged, so that the condition that the MOS tubes needing to be matched in the same sensing amplifier are consistent is ensured, the device characteristics of the MOS tubes in the same sensing amplifier are balanced, and the stability of the memory is improved.

In addition, the position of the active pattern of the first process module and the position of the active pattern of the second process module are symmetrically arranged. The position of the first processing module and the position of the second processing module in the same sense amplifier are symmetrically arranged, so that the consistency of the environments of the MOS tubes needing to be matched in the same sense amplifier is further ensured, and the stability of the memory is improved.

In addition, the symmetrically arranging of the position of the active pattern of the first process module and the position of the active pattern of the second process module includes: the position of the active pattern of the first offset canceling region and the position of the active pattern of the second offset canceling region are symmetrically arranged, the position of the active pattern of the first isolation region and the position of the active pattern of the second isolation region are symmetrically arranged, and the position of the active pattern of the equalizing region and the position of the active pattern of the precharge region are symmetrically arranged.

In addition, the active pattern of the first process module is disposed between the active pattern of the first NMOS region and the active pattern of the first PMOS region, and the active pattern of the second process module is disposed between the active pattern of the second NMOS region and the active pattern of the second PMOS region.

In addition, in the preset direction, the active pattern of the first NMOS area is disposed on a side of the active pattern of the first processing module away from the active pattern of the second processing module, the active pattern of the second NMOS area is disposed on a side of the active pattern of the second processing module away from the active pattern of the first processing module, and the active pattern of the first PMOS area and the active pattern of the second PMOS area are disposed between the active patterns of the first processing module and the second processing module.

In addition, in the preset direction, the active pattern of the first processing module is arranged on one side, away from the active pattern of the second processing module, of the active pattern of the first NMOS area and the active pattern of the first PMOS area, and the active pattern of the second processing module is arranged on one side, away from the active pattern of the first processing module, of the active pattern of the second NMOS area and the active pattern of the second PMOS area.

In addition, in the preset direction, the active pattern of the first PMOS region is disposed on a side of the first NMOS region close to the active pattern of the second processing module, the active pattern of the first processing module is disposed on a side of the first NMOS region far from the active pattern of the second processing module, the active pattern of the second PMOS region is disposed on a side of the second NMOS region close to the active pattern of the first processing module, and the active pattern of the second processing module is disposed on a side of the second NMOS region far from the active pattern of the first processing module.

In addition, the active pattern of the first processing module and the active pattern of the first NMOS region are arranged in the same well region, and the active pattern of the second processing module and the active pattern of the second NMOS region are arranged in the same well region. The active patterns arranged in the same well region can be guaranteed to have the same ion implantation characteristics, so that the ion implantation characteristics of the active patterns of the first processing module and the first NMOS region are the same, the ion implantation characteristics of the active patterns of the second processing module and the second NMOS region are the same, and the device characteristics of all MOS tubes in the same sense amplifier are further balanced.

In addition, in the preset direction, the active pattern of the first processing module is arranged on one side, close to the active pattern of the second processing module, of the active pattern of the first NMOS area and the active pattern of the first PMOS area, and the active pattern of the second processing module is arranged on one side, close to the active pattern of the first processing module, of the active pattern of the second NMOS area and the active pattern of the second PMOS area.

In addition, in the preset direction, the active pattern of the first NMOS area is disposed on a side of the active pattern of the first PMOS area away from the active pattern of the second processing module, the active pattern of the first processing module is disposed on a side of the active pattern of the first PMOS area close to the active pattern of the second processing module, the active pattern of the second NMOS area is disposed on a side of the active pattern of the second PMOS area away from the active pattern of the first processing module, and the active pattern of the second processing module is disposed on a side of the active pattern of the second PMOS area close to the active pattern of the first processing module.

In addition, in the preset direction, the active pattern of the first PMOS region is disposed on a side of the active pattern of the first NMOS region away from the active pattern of the second processing module, the active pattern of the first processing module is disposed on a side of the active pattern of the first NMOS region close to the active pattern of the second processing module, the active pattern of the second PMOS region is disposed on a side of the active pattern of the second NMOS region away from the active pattern of the first processing module, and the active pattern of the second processing module is disposed on a side of the active pattern of the second NMOS region close to the active pattern of the first processing module.

In addition, the active pattern of the first processing module, the active pattern of the second processing module, the active pattern of the first NMOS region and the active pattern of the second NMOS region are arranged in the same well region. The active patterns arranged in the same well region can be guaranteed to have the same ion implantation characteristics, so that the ion implantation characteristics of the active pattern of the first processing module, the active pattern of the first NMOS region, the active pattern of the second processing module and the active pattern of the second NMOS region are the same, and the device characteristics of each MOS tube in the same sense amplifier are further balanced.

In addition, in the preset direction, the length of the active pattern of the first NMOS area is greater than that of the active pattern of the first PMOS area; the active pattern length of the second NMOS area is greater than the active pattern length of the second PMOS area. The NMOS active pattern has a wider size than the PMOS active pattern, and provides a greater driving capability.

In addition, the gate pattern of the first NMOS region, the gate pattern of the second NMOS region, the gate pattern of the first PMOS region, and the gate pattern of the second PMOS region are arranged along a preset direction, and the gate pattern of the first processing module and the gate pattern of the second processing module are arranged along a vertical direction of the preset direction.

The embodiment of the application also provides a memory layout, which comprises the reading circuit layout, wherein a plurality of reading circuit layouts are sequentially arranged in the vertical direction of the preset direction, two adjacent reading circuit layouts form a reading circuit layout group, the reading circuit layout group shares the same active pattern, and the distance between the adjacent reading circuit layout groups is equal.

In addition, the read amplifier module for reading the circuit layout comprises: the first NMOS area and the first PMOS area are arranged close to the first processing module, and the second NMOS area and the second PMOS area are arranged close to the second processing module; the first processing module, the first NMOS area, the first PMOS area, the second processing module, the second NMOS area and the second PMOS area are arranged along a preset direction; the active patterns of the first NMOS area and the second NMOS area are arranged independently, and the active patterns of the first PMOS area and the second PMOS area are arranged independently.

In addition, the active patterns of the first NMOS region and the second NMOS region are symmetrically arranged, and the active patterns of the first PMOS region and the second PMOS region are symmetrically arranged.

In addition, the position of the active pattern of the first process module and the position of the active pattern of the second process module are symmetrically disposed.

In addition, the memory layout further comprises: and a connection pattern disposed at an edge of the precharge region and contacting the active patterns of the precharge region, the connection pattern being for contacting the active patterns of all the precharge regions in a direction perpendicular to the preset direction.

An embodiment of the present application further provides a readout circuit structure, including: the device comprises a sense amplifier, a first processing circuit and a second processing circuit which are arranged along a preset direction, wherein the sense amplifier is used for sensing the voltage of a bit line, and the first processing circuit and the second processing circuit are at least used for carrying out noise elimination on an output signal of the sense amplifier; the first processing circuit includes: a first offset canceling structure, a first isolation structure and an equalizing structure arranged along a preset direction, the first offset canceling structure being configured to connect the bit line to a complementary sense bit line, the first isolation structure being configured to connect the bit line to the sense bit line, the equalizing structure being configured to connect the sense bit line to the complementary sense bit line; the second processing circuit includes: a precharge structure, a second isolation structure, and a second offset canceling structure arranged in a preset direction, the precharge structure being configured to precharge the sense bit line and the complementary sense bit line based on a precharge command, the second isolation structure being configured to connect the complementary bit line to the complementary sense bit line, the second offset canceling structure being configured to connect the complementary bit line to the sense bit line; the active layer of the first offset canceling structure, the active layer of the first isolation structure and the active layer of the equalizing structure are arranged separately from each other, and the active layer of the pre-charging structure, the active layer of the second isolation structure and the active layer of the second offset canceling structure are arranged separately from each other.

Compared with the prior art, for the sensing amplifier structure in the sensing circuit structure, the active layers of the first offset elimination structure, the first isolation structure and the equalization structure in the first processing circuit are arranged separately from one another, and the active layers of the pre-charging structure, the second isolation structure and the second offset elimination structure in the second processing circuit are arranged separately from one another, so that the problem that the active layers of the first processing circuit and the second processing circuit in the same sensing amplifier structure are shared is solved, the device performance of an MOS (metal oxide semiconductor) transistor in the memory sensing circuit is improved, and the influence of timing mismatch of a memory in the sensing process is reduced.

Drawings

FIG. 1 is a schematic diagram of a memory structure;

FIG. 2 is a circuit schematic of a sensing circuit;

FIG. 3 is a timing diagram of a sensing circuit;

FIG. 4 is a schematic diagram of signals in a bit line BL/complementary bit line BLB when sense amplifier MOS transistors in a sensing circuit are not matched;

fig. 5 to fig. 10 are schematic structural diagrams of a readout circuit layout according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of a memory layout according to another embodiment of the present application.

Detailed Description

Referring to fig. 1, in the structure of the memory, each memory array 100 includes a plurality of memory cells 1000, each memory cell 1000 is a 1T1C (1 transistor 1 capacitance) structure composed of a cell transistor and a cell capacitor, and the read-write conversion circuit 200, the readout circuit 300, the equalization circuit 400, and the input/output circuit 500 are disposed between adjacent memory arrays.

One of the source and the drain of the cell transistor is connected with the cell capacitor, the other is connected with the bit line BL/complementary bit line BLB, the word line WL is connected with the gate of the cell transistor and is used for selectively turning on the gate of the corresponding cell transistor to connect the cell capacitor with the bit line BL/complementary bit line BLB, so that the electric signal in the bit line BL/complementary bit line BLB is written into the cell capacitor, or the electric signal in the cell capacitor is read out into the bit line BL/complementary bit line BLB.

Equalization circuit 400 is coupled to bit line BL and complementary bit line BLB for equalizing the voltage between bit line BL and complementary bit line BLB during the precharge phase.

The input/output circuit 500 includes: and the source or the drain of the input/output transistor is connected with the bit line BL/complementary bit line BLB, the other is connected with the Local data line Local I/O, the grid is used for receiving a selection signal, and the bit line BL/complementary bit line BLB corresponding to the selection signal is selected to be turned on according to the selection signal so as to connect the bit line BL/complementary bit line BLB with the Local data line Local I/O, thereby realizing the data transmission of the bit line BL/complementary bit line BLB and the Local data line Local I/O.

The Local data line Local I/O is connected with the Global data line Global I/O through the read-write conversion circuit 200, so that external data or data in a Local sense amplifier (arranged in the read-write conversion circuit 200) is transmitted into the Local data line Local I/O, or the data in the Local data line Local I/O is output into the Global data line Global I/O.

The sensing circuit 300 is connected between the bit line BL and the complementary bit line BLB, and when the electric signal in the cell capacitor is sensed to the bit line BL/complementary bit line BLB, the voltage of the bit line BL/complementary bit line BLB is increased or decreased by a voltage variation Δ V due to charge sharing of the cell capacitor and the bit line BL/complementary bit line BLB, the sensing circuit 300 serves to sense and amplify the voltage variation Δ V between the bit line BL and the complementary bit line BLB in response to the first control signal PCS and the second control signal NCS.

Specifically, referring to fig. 2, the readout circuit 300 (refer to fig. 1) includes: a first PMOS transistor < P1>, a second PMOS transistor < P2>, a first NMOS transistor < N1> and a second NMOS transistor < N2>; wherein, one of the source or drain of the first PMOS transistor < P1> is connected to the complementary sense bitline SABLB, the other one is for receiving the first control signal PCS, and the gate is connected to the sense bitline SABL; a second PMOS transistor < P2> having one of a source or a drain connected to the sense bit line SABL, the other for receiving the first control signal PCS, and a gate connected to the complementary sense bit line SABLB; one of the source or drain of the first NMOS transistor < N1> is connected to the complementary sense bit line SABLB, the other one is for receiving the second control signal NCS, and the gate is connected to the bit line BL; one of the source or drain of the second NMOS transistor < N2> is connected to the sense bit line BLB, the other one is for receiving the second control signal NCS, and the gate is connected to the complementary sense bit line SABLB.

The readout circuit 300 in fig. 2 is also used for noise cancellation, i.e. the readout circuit 300, further comprises: the first isolation MOS tube < N5>, the second isolation MOS tube < N6>, the first offset elimination MOS tube < N7> and the second offset elimination MOS tube < N8>; wherein, one of the source or the drain of the first Isolation MOS transistor < N5> is connected to the bit line BL, the other is connected to the sense bit line SABL, the gate is used for receiving an Isolation Signal (ISO) for connecting the bit line BL and the sense bit line SABL in response to the Isolation Signal ISO or for isolating the bit line BL and the sense bit line SABL in response to the Isolation Signal ISO; a second isolation MOS transistor < N6> having one of a source or a drain connected to complementary bitline BLB, the other connected to complementary sense bitline SABLB, a gate for receiving an isolation signal ISO for connecting complementary bitline BLB and complementary sense bitline SABLB in response to the isolation signal ISO or isolating complementary bitline BLB and complementary sense bitline SABLB in response to the isolation signal ISO; the first Offset cancellation MOS transistor < N7> has one of a source and a drain connected to the bit line BL, the other connected to the complementary read bit line SABLB, and a gate for receiving an Offset cancellation Signal (OC), for connecting the bit line BL and the complementary read bit line SABLB in response to the Offset cancellation Signal OC, or disconnecting the bit line BL and the complementary read bit line SABLB in response to the Offset cancellation Signal OC; the second offset cancel MOS transistor < N8> has one of a source or a drain connected to the complementary bit line BLB and the other connected to the sense bit line SABL, and a gate for receiving the offset cancel signal OC, for connecting the complementary bit line BLB and the sense bit line SABL in response to the offset cancel signal OC, or for disconnecting the complementary bit line BLB and the sense bit line SABL in response to the offset cancel signal OC.

Precharge is implemented by precharge transistor < N3>, equalization circuit 400 is implemented by equalization transistor < N4>, precharge transistor < N3> having one of a source or a drain for receiving precharge voltage VDD/2, the other for connecting one of a source or a drain of equalization transistor < N4>, a gate for receiving precharge signal PRE for precharging sense bitline SABL and complementary sense bitline SABLB in response to precharge signal PRE; equalization transistor < N4> has one of its source or drain connected to sense bit line SABL and the other connected to complementary sense bit line SABLB, and has a gate for receiving equalization signal EQ for equalizing the voltages of sense bit line SABL and complementary sense bit line SABLB in response to equalization signal EQ.

Referring to fig. 3, a precharge operation is performed in a process of data reading including 5 stages, i.e., a stage 1 to a stage t 0; stage 2, namely stage t 0-stage t1, executing offset elimination operation; stage 3, namely, stages t1 to t2, executing charge sharing operation; stage 4, namely stage t 2-stage t3, executing pre-reading operation; and in the stage 5, namely the stages from t3 to t, the recovery operation is executed.

Specifically, during execution of phase 1, precharge transistor < N3> is responsive to precharge signal PRE of logic high (H), equalization transistor < N4> is responsive to equalization signal EQ of logic high (H), first isolation MOS transistor < N5> and second isolation MOS transistor < N6> are responsive to isolation signal ISO of logic high (H), and first offset cancellation MOS transistor < N7> and second offset cancellation MOS transistor < N8> are responsive to offset cancellation signal OC of logic high (H); bit line BL, complementary bit line BLB, sense bit line SABL, and complementary sense bit line SABLB are all connected to a precharge voltage VDD/2, and first control signal PCS and second control signal NCS are also charged to precharge voltage VDD/2; during the execution of phase 2, the PRE-charge signal PRE and the equalization signal EQ are low, the first isolation MOS transistor < N5> and the second isolation MOS transistor < N6> are responsive to the isolation signal ISO of logic low (L), and the first offset cancellation MOS transistor < N7> and the second offset cancellation MOS transistor < N8> are responsive to the offset cancellation signal OC of logic high (H); the first control signal PCS is converted from the precharge voltage VDD/2 to the internal power voltage VDD, and the second control signal NCS is converted from the precharge voltage VDD/2 to the ground voltage VSS; in performing phase 3, the first isolation MOS transistor < N5> and the second isolation MOS transistor < N6> are responsive to the isolation signal ISO of logic high (H), the first offset canceling MOS transistor < N7> and the second offset canceling MOS transistor < N8> are responsive to the offset canceling signal OC of logic low (L), the word line WL is activated, at which time charge sharing is performed between the selected bit line BL/complementary bit line BLB and the cell capacitor, and the first control signal PCS and the second control signal NCS are transited to the precharge voltage VDD/2; during execution of phase 4, when data having a value of "1" is stored in the memory cell, the voltage on sense bit line SABL may be raised to internal power supply voltage VDD and the voltage on complementary sense bit line SABLB may be lowered to ground voltage VSS during the pre-sense operation phase. When the output having the value "0" is stored in the memory cell, the voltage on the sense bit line SABL may be lowered to the ground voltage VSS and the voltage on the complementary sense bit line SABLB may be raised to the internal power supply voltage VDD in the pre-sense operation stage; in performing phase 5, first isolation MOS transistor < N5> and second isolation MOS transistor < N6> are responsive to isolation signal ISO of logic high (H), and first offset cancellation MOS transistor < N7> and second offset cancellation MOS transistor < N8> are responsive to offset cancellation signal OC of logic high (H); bit line BL, complementary bit line BLB, sense bit line SABL, and complementary sense bit line SABLB are all connected to precharge voltage VDD/2, and first control signal PCS and second control signal NCS are also charged to precharge voltage VDD/2.

In the process of executing the stage 4, the MOS transistors in the same sense amplifier have different device characteristics due to different device environments around the MOS transistors in the sense amplifier, and the device characteristics of the MOS transistors in the same sense amplifier need to be matched with each other, so that the MOS transistors with different device characteristics affect the amplification capability of the sense amplifier, thereby reducing the performance of the DRAM; referring to fig. 4, due to the non-uniform device characteristics of the transistors, a certain offset is generated in the voltage of the bit line BL/complementary bit line BLB that should originally rise according to the dotted line, which causes a timing mismatch problem during the reading process of the memory.

In order to solve the above problem, an embodiment of the present application provides a readout circuit layout, including: the device comprises a read-out amplification module, a first processing module and a second processing module which are arranged along a preset direction, wherein the read-out amplification module is used for reading the voltage of a bit line, and the first processing module and the second processing module are at least used for carrying out noise elimination on an output signal of the read-out amplification module; the first processing module includes: a first offset canceling region, a first isolation region and an equalizing region arranged in a preset direction, the first offset canceling region being configured to connect the bit line to the complementary sense bit line, the first isolation region being configured to connect the bit line to the sense bit line, the equalizing region being configured to connect the sense bit line to the complementary sense bit line; the second processing module comprises: a precharge region, a second isolation region, and a second offset canceling region arranged in a preset direction, the precharge region configured to precharge the sense bit line and the complementary sense bit line based on a precharge command, the second isolation region configured to connect the complementary bit line to the complementary sense bit line, the second offset canceling region configured to connect the complementary bit line to the sense bit line; the active pattern of the first offset canceling region, the active pattern of the first isolation region, and the active pattern of the equalizing region are separately disposed from each other, and the active pattern of the precharge region, the active pattern of the second isolation region, and the active pattern of the second offset canceling region are separately disposed from each other.

To make the objects, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the various embodiments of the present application, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solutions claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments. The following embodiments are divided for convenience of description, and should not constitute any limitation to the specific implementation manner of the present application, and the embodiments may be combined with each other and referred to each other without contradiction.

Fig. 5 to fig. 10 are schematic structural diagrams of the readout circuit layout provided in this embodiment, and the readout circuit layout provided in this embodiment is further described in detail below with reference to the accompanying drawings, specifically as follows:

referring to fig. 5 to 10, the readout circuit layout includes:

the read-out amplification module 103, the first processing module 101 and the second processing module 102 are arranged in a preset direction.

Wherein, in the preset direction, i.e. the X direction (corresponding to the arrangement direction of the plurality of memory arrays 100 in fig. 1), the sense amplifying module 103 is used for sensing the voltage of the bit line BL, and then forming the sense amplifier, the first processing module 101 and the second processing module 102 are at least used for performing noise cancellation on the output signal of the sense amplifying module 103, and then forming the sense circuit 300 shown in fig. 2 with the sense amplifier.

For the first processing module 101, the first processing module 101 includes a first offset canceling region 111, a first isolation region 121, and an equalizing region 131; wherein the first offset canceling region 111 is configured to connect the bit line BL to the complementary sensing bit line SABLB, the first isolation region 121 is configured to connect the bit line BL to the sensing bit line SABL, and the equalizing region 131 is configured to connect the sensing bit line SABL to the complementary sensing bit line SABLB.

With reference to fig. 2, the first offset canceling region 111 is used for forming the first offset canceling MOS transistor < N7> subsequently, the first isolation region 121 is used for forming the first isolation MOS transistor < N5> subsequently, and the equalizing region 131 is used for forming the equalizing MOS transistor < N4> subsequently, wherein the first offset canceling region 111 and the first isolation region 121 share a source, and the shared source is used for connecting the bit line BL; the first isolation region 121 and the equalizing region 131 share a drain, the shared drain is used for connecting the sensing bit line SABL, and the drain of the first offset canceling region 111 and the source of the equalizing region 131 are used for connecting the complementary sensing bit line SABLB.

For the second processing module 102, the second processing module 102 includes a precharge region 112, a second isolation region 122, and a second offset cancellation region 132; the precharge region 112 is configured to precharge the bit line BL and the complementary bit line BLB based on a precharge command, the second isolation region 122 is configured to connect the complementary bit line BLB to the complementary sense bit line SABLB, and the second offset canceling region 132 is configured to connect the complementary bit line BLB to the sense bit line SABL.

With reference to fig. 2, pre-charge region 112 is used to form pre-charge MOS transistor subsequently<N3>The second isolation region 122 is used for subsequently forming a second isolation MOS transistor<N6>The second offset cancellation region 132 is used for forming the second offset cancellation MOS transistor subsequently<N8>Wherein the precharge region 112 and the second isolation region 122 share a source, the shared source is used for connecting the complementary sensing bit line SABLB, the second isolation region 122 and the second offset canceling region 132 share a drain, the shared drain is used for connecting the complementary bit line BLB, and the drain of the precharge region 112 is used for receiving the precharge voltage vbv _DD The source of the second isolation region 132 is used to connect to the sense bit line SABL.

It should be noted that, in this embodiment, the determined "source" and "drain" are examples of the present application, so that a person skilled in the art may clearly understand the arrangement manner of the present embodiment and do not constitute a limitation to the present embodiment, and in other embodiments, the "source" and the "drain" determined in the present application may be arranged alternatively.

The active pattern of the first offset canceling region 111, the active pattern of the first isolation region 121, and the active pattern of the equalizing region 131 are separately disposed, that is, the active pattern of the first offset canceling region 111, the active pattern of the first isolation region 121, and the active pattern of the equalizing region 131 are independent of each other and do not affect each other; the active pattern of the precharge region 112, the active pattern of the second isolation region 122, and the active pattern of the second offset canceling region 132 are separately disposed, that is, the active pattern of the precharge region 112, the active pattern of the second isolation region 122, and the active pattern of the second offset canceling region 132 are independent from each other and do not affect each other; the problem that the first processing module 101 and the second processing module 102 in the same sense amplifier structure share active patterns is solved, so that the device performance of an MOS (metal oxide semiconductor) tube in a read circuit of a memory is improved, and the influence of time sequence mismatch of the memory in the read process is reduced.

Specifically, the readout amplification block 103 includes: a first NMOS region 114 and a first PMOS region 115 disposed adjacent to the first process module 101, and a second NMOS region 124 and a second PMOS region 125 disposed adjacent to the second process module 102.

The first NMOS region 114, the first PMOS region 115, the second NMOS region 124, and the second PMOS region 125 are arranged along a predetermined direction, that is, the first NMOS region 114, the first PMOS region 115, the second NMOS region 124, and the second PMOS region 125 are arranged in the X direction.

Further, the active pattern of the first NMOS region 114 and the active pattern of the second NMOS region 124 are disposed independently of each other, and the active pattern of the first PMOS region 115 and the active pattern of the second PMOS region 125 are disposed independently of each other; the active patterns of the two NMOS regions are arranged independently, and the active patterns of the two PMOS regions are arranged independently, so that the active regions of the MOS tube structures in the subsequently formed sensing amplifier are independent, and the problem of signal interference caused by the sharing of the active regions in the MOS tubes can be reduced.

In addition, in the present embodiment, the active pattern of the first NMOS region 114 and the active pattern of the second NMOS region 124 are symmetrically disposed, and the active pattern of the first PMOS region 115 and the active pattern of the second PMOS region 125 are symmetrically disposed. The MOS tubes in the same sensing amplifier are symmetrically arranged, so that the condition that the MOS tubes needing to be matched in the same sensing amplifier are consistent is ensured, the device characteristics of the MOS tubes in the same sensing amplifier are balanced, and the stability of the memory is improved.

Specifically, referring to fig. 5 to 10, the active pattern of the first NMOS area 114 and the active pattern of the second NMOS area 124 are symmetrically disposed according to the symmetry axis AA1, and the active pattern of the second PMOS area 115 and the active pattern of the second PMOS area 125 are also symmetrically disposed according to the symmetry axis AA 1.

In addition, for the first NMOS region 114, the second NMOS region 124, the first PMOS region 115, and the second PMOS region 125, the gate pattern of the first PMOS region 114, the gate pattern of the second NMOS region 124, the gate pattern of the first PMOS region 115, and the gate pattern of the second PMOS region 124 are disposed in a predetermined direction, i.e., the gate pattern of the first PMOS region 114, the gate pattern of the second NMOS region 124, the gate pattern of the first PMOS region 115, and the gate pattern of the second PMOS region 124 are disposed in the X direction.

It should be noted that, in the present embodiment, the length of the active pattern of the first NMOS region 114 and the length of the active pattern of the second NMOS region 124 are greater than the length of the active pattern of the first PMOS region 115 and the length of the active pattern of the second PMOS region 125, and the active pattern of the NMOS has a wider size compared to the active pattern of the PMOS, thereby providing a greater driving capability. In other embodiments, the size of the PMOS active pattern may be set to be larger than that of the NMOS active pattern, or the size of the PMOS active pattern may be the same as that of the NMOS active pattern.

Accordingly, in the present embodiment, the position of the first process module 101 active pattern and the position of the second process module active pattern 102 are symmetrically disposed. The position of the first processing module 104 and the position of the second processing module 102 in the same sense amplifier are symmetrically arranged, so that the consistency of the environments of the MOS transistors to be matched in the same sense amplifier is further ensured, and the stability of the memory is improved.

Specifically, referring to fig. 5 to 10, the positions of the active patterns of the first process module 101 and the positions of the active patterns of the second process module 102 are symmetrically disposed according to the symmetry axis AA1, i.e., each position of the active patterns in the first process module 101 and the corresponding position of the active patterns in the second process module 102 are equidistant from the symmetry axis AA 1.

Due to the foregoing, in the present embodiment, the positions of the active patterns of the first and

second process modules

101 and 102 are symmetrically disposed according to the symmetry axis AA 1. Specifically, the active pattern of the first offset canceling region 111 and the active pattern of the second offset canceling region 132 are symmetrically disposed based on the symmetry axis AA1, the active pattern of the first isolation region 121 and the active pattern of the second isolation region 122 are symmetrically disposed based on the symmetry axis AA1, and the position of the active pattern of the equalizing region 131 and the position of the active pattern of the precharge region 112 are symmetrically disposed based on the symmetry axis AA 1.

In addition, with the first and

second process modules

101 and 102 in the present embodiment, the gate patterns of the first and

second process modules

101 and 102 are arranged in a direction perpendicular to the preset direction, that is, the gate patterns of the first and

second process modules

101 and 102 are arranged perpendicular to the X direction.

The present embodiment provides six layout modes of the first processing module 101, the second processing module 102, and the readout amplification module 103, which are specifically as follows:

referring to fig. 5 and 6, the active pattern of the first process module 101 is disposed at a side of the active pattern of the first NMOS region 114 and the active pattern of the first PMOS region 115 away from the active pattern of the second process module 102; the active pattern of the second processing module 102 is disposed at a side of the active pattern of the second NMOS region 124 and the active pattern of the second PMOS region 125 far from the active pattern of the first processing module 101, i.e., the first processing module 101 and the second processing module 102 are disposed at both sides of the sense amplifying module 103.

In a specific example, referring to fig. 5, in the preset direction, the active pattern of the first PMOS region 115 is disposed on a side of the first NMOS region 114 close to the active pattern of the second process module 102, the active pattern of the first process module 101 is disposed on a side of the first NMOS region 114 away from the active pattern of the second process module 102, the active pattern of the second PMOS region 125 is disposed on a side of the second NMOS region 124 close to the active pattern of the first process module 101, and the active pattern of the second process module 102 is disposed on a side of the second NMOS region 124 away from the active pattern of the first process module 101.

Wherein the active pattern of the first processing module 101 and the active pattern of the first NMOS region 114 are disposed in the same well region, and the active pattern of the second processing module 102 and the active pattern of the second NMOS region 124 are disposed in the same well region; as shown in fig. 5, the active pattern of the first processing module 101 and the active pattern of the first NMOS region 114 are disposed in the first well region 1001, and the active pattern of the second processing module 102 and the active pattern of the second NMOS region 124 are disposed in the second well region 1002; the active patterns disposed in the same well region may be guaranteed to have the same ion implantation characteristics, such that the ion implantation characteristics of the active pattern of the first processing module 101 and the active pattern of the first NMOS region 114 are the same, and the ion implantation characteristics of the active pattern of the second processing module 102 and the active pattern of the second NMOS region 124 are the same, so as to further balance the device characteristics of each MOS transistor in the same sense amplifier.

In another specific example, referring to fig. 6, in the preset direction, the active pattern of the first NMOS region 114 is disposed on a side of the first PMOS region 115 close to the active pattern of the second process module 102, the active pattern of the first process module 101 is disposed on a side of the first PMOS region 115 away from the active pattern of the second process module 102, the active pattern of the second NMOS region 124 is disposed on a side of the second PMOS region 125 close to the active pattern of the first process module 101, and the active pattern of the second process module 102 is disposed on a side of the second PMOS region 125 away from the active pattern of the first process module 101.

Wherein the active pattern of the first NMOS region 114 and the active pattern of the second NMOS region 115 are disposed in the same well region, as shown in fig. 6, the active pattern of the first NMOS region 114 and the active pattern of the second NMOS region 115 are disposed in the third well region 1003.

Referring to fig. 7 and 8, the active pattern of the first processing module 101 is disposed between the active pattern of the first NMOS region 114 and the active pattern of the first PMOS region 115, and the active pattern of the second processing module 102 is disposed between the active pattern of the second NMOS region 124 and the active pattern of the second PMOS region 125, i.e., the first processing module 101 and the second processing module 102 are disposed within the sense amplifying module 103.

In a specific example, referring to fig. 7, in the preset direction, the active pattern of the first NMOS region 114 is disposed at a side of the active pattern of the first process module 101 away from the active pattern of the second process module 102, the active pattern of the second NMOS region 124 is disposed at a side of the active pattern of the second process module 102 away from the active pattern of the first process module 101, and the active patterns of the first PMOS region 115 and the second PMOS region 125 are disposed between the active pattern of the first process module 101 and the active pattern of the second process module 102.

Wherein the active pattern of the first processing module 101 and the active pattern of the first NMOS area 114 are disposed in the same well region, and the active pattern of the second processing module 102 and the active pattern of the second NMOS area 124 are disposed in the same well region; as shown in fig. 7, the active pattern of the first processing module 101 and the active pattern of the first NMOS area 114 are disposed in the fourth well region 1004, and the active pattern of the second processing module 102 and the active pattern of the second NMOS area 124 are disposed in the fifth well region 1005.

In another specific example, referring to fig. 8, in the preset direction, the active pattern of the first PMOS region 115 is disposed at a side of the active pattern of the first process module 101 away from the active pattern of the second process module 102, the active pattern of the second PMOS region 125 is disposed at a side of the active pattern of the second process module 102 away from the active pattern of the first process module 101, and the active patterns of the first NMOS region 114 and the second NMOS region 124 are disposed between the active pattern of the first process module 101 and the active pattern of the second process module 102.

Wherein the active pattern of the first processing module 101, the active pattern of the first NMOS region 114, the active pattern of the second processing module 102, and the active pattern of the second NMOS region 124 are disposed in the same well region; as shown in fig. 8, the active pattern of the first processing module 101, the active pattern of the first NMOS region 114, the active pattern of the second processing module 102, and the active pattern of the second NMOS region 124 are disposed in the sixth well region 1006; the active patterns disposed in the same well region may be guaranteed to have the same ion implantation characteristics, so that the ion implantation characteristics of the active patterns of the first processing module 101, the first NMOS region 114, the second processing module 102, and the second NMOS region 124 are the same, and the device characteristics of the MOS transistors in the same sense amplifier are further balanced.

Referring to fig. 9 and 10, in the preset direction, the active pattern of the first process module 101 is disposed at a side of the first NMOS region 114 and the first PMOS region 115 close to the second process module 102, and the active pattern of the second process module 102 is disposed at a side of the second NMOS region 124 and the second PMOS region 125 close to the first process module 101. Namely, the first processing block 101 and the second processing block 102 are disposed between the sense amplifying blocks 103.

In a specific example, referring to fig. 9, in the predetermined direction, the active pattern of the first PMOS region 115 is disposed on a side of the first NMOS region 114 away from the active pattern of the second process module 102, the active pattern of the first process module 101 is disposed on a side of the first NMOS region 114 close to the active pattern of the second process module 102, the active pattern of the second PMOS region 125 is disposed on a side of the second NMOS region 124 away from the active pattern of the first process module 101, and the active pattern of the second process module 102 is disposed on a side of the second NMOS region 124 away from the active pattern of the first process module 101.

Wherein the active pattern of the first processing module 101, the active pattern of the first NMOS region 114, the active pattern of the second processing module 102, and the active pattern of the second NMOS region 124 are disposed in the same well region; as shown in fig. 9, the active pattern of the first process module 101, the active pattern of the first NMOS region 114, the active pattern of the second process module 102, and the active pattern of the second NMOS region 124 are disposed in the seventh well region 1007.

In another specific example, referring to fig. 10, in the preset direction, the active pattern of the first NMOS region 114 is disposed on a side of the first PMOS region 115 away from the active pattern of the second process module 102, the active pattern of the first process module 101 is disposed on a side of the first PMOS region 115 close to the active pattern of the second process module 102, the active pattern of the second NMOS region 124 is disposed on a side of the second PMOS region 125 away from the active pattern of the first process module 101, and the active pattern of the second process module 102 is disposed on a side of the second PMOS region 125 away from the active pattern of the first process module 101.

Wherein, the active pattern of the first processing module 101 and the active pattern of the second processing module 102 are disposed in the same well region; as shown in fig. 10, the active pattern of the first process module 101 and the active pattern of the second process module 102 are disposed in the eighth well region 1008.

Another embodiment of the present application further provides a memory layout, including the readout circuit layouts provided in the above embodiments, where a plurality of readout circuit layouts are sequentially arranged in a vertical direction of a preset direction, two adjacent readout circuit layouts form a readout circuit layout group, the readout circuit layout groups share a same active pattern, and distances between adjacent readout circuit layout groups are equal.

Fig. 11 is a schematic structural diagram of the memory layout provided in this embodiment, and the memory layout provided in this embodiment is further described in detail below with reference to the accompanying drawings, specifically as follows:

referring to fig. 11, the memory layout includes a plurality of read circuit layouts according to the above embodiments, and the plurality of read circuit layouts are sequentially arranged in a direction perpendicular to the preset direction, that is, the plurality of read circuit layouts are arranged in a direction perpendicular to the X direction.

Specifically referring to fig. 11, in a direction perpendicular to the preset direction, the embodiment takes 4 readout circuit layouts as an example for detailed description, which is only used for understanding the present application by those skilled in the art, and does not constitute a limitation to the present application, and the details are as follows:

the first column of sense circuit layout and the second column of sense circuit layout form a first set of sense circuit layouts, the third column of sense circuit layout and the fourth column of sense circuit layout form a second set of sense circuit layouts, and in the same set of sense circuit layouts, the first NMOS region 114 shares the same active pattern, the second NMOS region 124 shares the same active pattern, the first PMOS region 115 shares the same active pattern, and the second PMOS region 125 shares the same active pattern.

In the same memory layout, all the first processing modules 101 arranged in the vertical direction in the preset direction share the gate structure, and all the second processing modules 102 arranged in the vertical direction in the preset direction share the gate structure.

The distances between adjacent groups of readout circuit patterns are equal, including: the distances between every two of the plurality of reading circuit layout groups are equal; the distance between the active patterns of the adjacent first processing modules 101, the distance between the active patterns of the adjacent second processing modules 102, the distance between the active patterns of the adjacent first NMOS regions 114, the distance between the active patterns of the adjacent second NMOS regions 124, the distance between the active patterns of the adjacent first PMOS regions 115, and the distance between the active patterns of the adjacent second PMOS regions 125 are equal for the first readout circuit layout group and the second readout circuit layout group.

With continued reference to fig. 11, each sense circuit layout includes:

the read-out amplification module 103, the first processing module 101 and the second processing module 102 are arranged along a preset direction.

Specifically, the readout amplification block 103 includes: a first NMOS region 114 and a first PMOS region 115 disposed adjacent to the first processing module 101, and a second NMOS region 124 and a second PMOS region 125 disposed adjacent to the second processing module 102. The active pattern of the first NMOS region 114 and the active pattern of the second NMOS region 124 are symmetrically disposed, and the active pattern of the first PMOS region 115 and the active pattern of the second PMOS region 125 are symmetrically disposed.

The active pattern of the first NMOS region 114 and the active pattern of the second NMOS region 124 are disposed independently of each other, and the active pattern of the first PMOS region 115 and the active pattern of the second PMOS region 125 are disposed independently of each other.

Accordingly, the position of the first process module 101 active pattern and the position of the second process module active pattern 102 are symmetrically disposed.

For the first processing module 101, the first processing module 101 includes a first offset canceling region 111, a first isolation region 121, and an equalizing region 131; wherein the first offset canceling region 111 is configured to connect the bit line BL to the complementary read bit line SABLB, the first isolation region 121 is configured to connect the bit line BL to the read bit line SABL, and the equalizing region 131 is configured to connect the read bit line SABL to the complementary read bit line SABLB.

Wherein the active pattern of the first offset canceling region 111, the active pattern of the first isolation region 121, and the active pattern of the equalizing region 131 are separately disposed from each other.

Wherein the active pattern of the precharge region 112, the active pattern of the second isolation region 122, and the active pattern of the second offset canceling region 132 are separately disposed from each other.

Due to the foregoing, in the present embodiment, the positions of the active patterns of the first process module 101 and the second process module 102 are symmetrically disposed. Specifically, the active pattern of the first offset canceling region 111 and the active pattern of the second offset canceling region 132 are symmetrically disposed, the active pattern of the first isolation region 121 and the active pattern of the second isolation region 122 are symmetrically disposed, and the position of the active pattern of the equalizing region 131 and the position of the active pattern of the precharge region 112 are symmetrically disposed.

In this embodiment, the memory layout further includes: and a connection pattern 201 disposed at an edge of the precharge region 112 and contacting the active patterns of the precharge region 112, the connection pattern 201 for contacting all the active patterns of the precharge region 112 in a direction perpendicular to the preset direction. Since the active pattern of precharge region 112 is typically smaller in size than the other regions, the device characteristics of the individual MOS transistors in the same sense amplifier are further balanced by connecting pattern 201 to balance the active region "environment" around first NMOS region 114 and second NOS region 125; in this embodiment, the "environment" refers to the same characteristics of the semiconductor structure composed of the same surrounding materials, such as the size, distance, and arrangement.

Compared with the prior art, for the MOS structure of the sense amplifier in the sense amplifier circuit layout, the active patterns of the first offset elimination region, the first isolation region and the equalization region in the first processing module are arranged separately, and the active patterns of the precharge region, the second isolation region and the second offset elimination region in the second processing module are arranged separately, so that the problem that the active regions are shared by the first processing module and the second processing module in the same sense amplifier structure is avoided, the device performance of an MOS tube in the memory sense circuit is improved, and the influence of time sequence mismatch of the memory in the sense amplifier is reduced.

Since the above embodiments correspond to the present embodiment, the present embodiment can be implemented in cooperation with the above embodiments. The related technical details mentioned in the above embodiments are still valid in this embodiment, and the technical effects that can be achieved in the above embodiments can also be achieved in this embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related-art details mentioned in the present embodiment can also be applied to the above-described embodiments.

Another embodiment of the present application provides a readout circuit structure, including: the device comprises a sense amplifier, a first processing circuit and a second processing circuit which are arranged along a preset direction, wherein the sense amplifier is used for sensing the voltage of a bit line, and the first processing circuit and the second processing circuit are at least used for carrying out noise elimination on an output signal of the sense amplifier; the first processing circuit includes: a first offset canceling structure, a first isolation structure and an equalizing structure arranged along a preset direction, the first offset canceling structure being configured to connect the bit line to a complementary sense bit line, the first isolation structure being configured to connect the bit line to the sense bit line, the equalizing structure being configured to connect the sense bit line to the complementary sense bit line; the second processing circuit includes: a precharge structure, a second isolation structure, and a second offset canceling structure arranged in a preset direction, the precharge structure being configured to precharge the sense bit line and the complementary sense bit line based on a precharge command, the second isolation structure being configured to connect the complementary bit line to the complementary sense bit line, the second offset canceling structure being configured to connect the complementary bit line to the sense bit line; the active layer of the first offset canceling structure, the active layer of the first isolation structure and the active layer of the equalizing structure are arranged separately from each other, and the active layer of the pre-charging structure, the active layer of the second isolation structure and the active layer of the second offset canceling structure are arranged separately from each other.

As described in further detail below, the readout circuit structure provided in this embodiment includes:

the circuit comprises a sense amplifier, a first processing circuit and a second processing circuit which are arranged along a preset direction, wherein the sense amplifier is used for sensing the voltage of a bit line, and the first processing circuit and the second processing circuit are at least used for carrying out noise elimination on an output signal of the sense amplifier.

In conjunction with the above embodiments, the sense amplifying module 103 is configured to form the above sense amplifier, the first processing module 101 is configured to form the above first processing circuit, and the second processing module 102 is configured to form the above second processing circuit.

The sense amplifier includes: the first NMOS tube and the first PMOS tube are arranged close to the first processing circuit, the second NMOS tube and the second PMOS tube are arranged close to the second processing circuit, and the first processing circuit, the first NMOS tube, the first PMOS tube, the second processing circuit, the second NMOS tube and the second PMOS tube are arranged along the preset direction.

In combination with the above embodiment, the first NMOS region 114 is used to form the first NMOS transistor, the second NMOS region 124 is used to form the second NMOS transistor, the first PMOS region 115 is used to form the first PMOS transistor, and the second PMOS region 125 is used to form the second PMOS transistor.

The active layer of the first NMOS tube and the active layer of the second NMOS tube are arranged independently, and the active layer of the first PMOS tube and the active layer of the second PMOS tube are arranged independently.

The first processing circuit includes: a first offset canceling structure configured to connect the bit line to a complementary sense bit line, a first isolation structure configured to connect the bit line to the sense bit line, and an equalizing structure configured to connect the sense bit line to the complementary sense bit line, arranged in a predetermined direction.

In conjunction with the above embodiment, the first offset canceling region 111 is used to form the above first offset canceling structure, the first isolation region 121 is used to form the above first isolation structure, and the equalizing region 131 is used to form the above equalizing structure.

The second processing circuit includes: a precharge structure configured to precharge the sense bit line and the complementary sense bit line based on a precharge command, a second isolation structure configured to connect the complementary bit line to the complementary sense bit line, and a second offset canceling structure configured to connect the complementary bit line to the sense bit line, arranged in a preset direction.

In conjunction with the above embodiments, the precharge region 112 is used to form the precharge structure, the second isolation region 122 is used to form the second isolation structure, and the second offset canceling region 132 is used to form the second offset canceling structure.

The active layer of the first offset canceling structure, the active layer of the first isolation structure and the active layer of the equalizing structure are arranged separately from each other, and the active layer of the pre-charging structure, the active layer of the second isolation structure and the active layer of the second offset canceling structure are arranged separately from each other.

Compared with the prior art, for the sensing amplifier structure in the sensing amplifier structure, the active layers of the first offset cancellation structure, the first isolation structure and the equalization structure in the first processing circuit are arranged separately from one another, and the active layers of the pre-charging structure, the second isolation structure and the second offset cancellation structure in the second processing circuit are arranged separately from one another, so that the problem that the active layers of the first processing circuit and the second processing circuit in the same sensing amplifier structure are shared is avoided, the device performance of an MOS (metal oxide semiconductor) transistor in the memory sensing circuit is improved, and the influence of timing sequence mismatch of a memory in the sensing process is reduced.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementations of the present application and that various changes in form and details may be made therein without departing from the spirit and scope of the present application.

Claims

1. A sense circuit layout, comprising:

the device comprises a read-out amplification module, a first processing module and a second processing module which are arranged along a preset direction, wherein the read-out amplification module is used for reading out the voltage of a bit line, and the first processing module and the second processing module are at least used for carrying out noise elimination on an output signal of the read-out amplification module;

the first processing module comprises: a first offset canceling region, a first isolation region and an equalizing region arranged along the preset direction, the first offset canceling region being configured to connect the bit line to a complementary sense bit line, the first isolation region being configured to connect the bit line to a sense bit line, the equalizing region being configured to connect the sense bit line to the complementary sense bit line;

the second processing module comprises: a precharge region, a second isolation region, and a second offset canceling region arranged in the preset direction, the precharge region configured to precharge the sense bit line and the complementary sense bit line based on a precharge command, the second isolation region configured to connect the complementary bit line to the complementary sense bit line, the second offset canceling region configured to connect the complementary bit line to the sense bit line;

wherein the active pattern of the first offset canceling region, the active pattern of the first isolation region, and the active pattern of the equalizing region are separately disposed from each other, and the active pattern of the precharge region, the active pattern of the second isolation region, and the active pattern of the second offset canceling region are separately disposed from each other.

2. A sense circuit layout according to claim 1, wherein the sense amplifying module comprises:

a first NMOS region and a first PMOS region which are arranged close to the first processing module, and a second NMOS region and a second PMOS region which are arranged close to the second processing module;

the first processing module, the first NMOS region, the first PMOS region, the second processing module, the second NMOS region and the second PMOS region are arranged along the preset direction;

the active patterns of the first NMOS region and the second NMOS region are arranged independently, and the active patterns of the first PMOS region and the second PMOS region are arranged independently.

3. A sense circuit layout of claim 2, wherein the active pattern of the first NMOS region and the active pattern of the second NMOS region are symmetrically arranged, and the active pattern of the first PMOS region and the active pattern of the second PMOS region are symmetrically arranged.

4. A readout circuit layout as claimed in claim 1 or 2, wherein the position of the active pattern of the first processing block and the position of the active pattern of the second processing block are symmetrically arranged.

5. The readout circuit layout of claim 1, wherein the symmetrical arrangement of the positions of the active patterns of the first processing block and the positions of the active patterns of the second processing block comprises: the position of the active pattern of the first offset canceling region and the position of the active pattern of the second offset canceling region are symmetrically arranged, the position of the active pattern of the first isolation region and the position of the active pattern of the second isolation region are symmetrically arranged, and the position of the active pattern of the equalizing region and the position of the active pattern of the precharge region are symmetrically arranged.

6. The readout circuit layout of claim 2, wherein the active pattern of the first processing module is disposed between the active pattern of the first NMOS region and the active pattern of the first PMOS region, and the active pattern of the second processing module is disposed between the active pattern of the second NMOS region and the active pattern of the second PMOS region.

7. The readout circuit layout of claim 6, wherein, in the preset direction, the active pattern of the first NMOS region is disposed on a side of the active pattern of the first processing module away from the active pattern of the second processing module, the active pattern of the second NMOS region is disposed on a side of the active pattern of the second processing module away from the active pattern of the first processing module, and the active pattern of the first PMOS region and the active pattern of the second PMOS region are disposed between the active patterns of the first processing module and the second processing module.

8. The readout circuit layout of claim 2, wherein in the preset direction, the active pattern of the first processing module is disposed on a side of the active pattern of the first NMOS region and the active pattern of the first PMOS region away from the active pattern of the second processing module, and the active pattern of the second processing module is disposed on a side of the active pattern of the second NMOS region and the active pattern of the second PMOS region away from the active pattern of the first processing module.

9. The readout circuit layout of claim 8, wherein in the preset direction, the active pattern of the first PMOS region is disposed on a side of the first NMOS region close to the active pattern of the second processing module, the active pattern of the first processing module is disposed on a side of the first NMOS region far from the active pattern of the second processing module, the active pattern of the second PMOS region is disposed on a side of the second NMOS region close to the active pattern of the first processing module, and the active pattern of the second processing module is disposed on a side of the second NMOS region far from the active pattern of the first processing module.

10. The readout circuit layout of claim 9, wherein the active pattern of the first processing module and the active pattern of the first NMOS region are disposed in a same well region, and the active pattern of the second processing module and the active pattern of the second NMOS region are disposed in a same well region.

11. The readout circuit layout of claim 2, wherein in the preset direction, the active pattern of the first processing module is disposed on a side of the active pattern of the first NMOS region and the active pattern of the first PMOS region close to the active pattern of the second processing module, and the active pattern of the second processing module is disposed on a side of the active pattern of the second NMOS region and the active pattern of the second PMOS region close to the active pattern of the first processing module.

12. The readout circuit layout of claim 11, wherein in the preset direction, the active pattern of the first NMOS region is disposed on a side of the first PMOS region away from the active pattern of the second processing module, the active pattern of the first processing module is disposed on a side of the first PMOS region close to the active pattern of the second processing module, the active pattern of the second NMOS region is disposed on a side of the second PMOS region away from the active pattern of the first processing module, and the active pattern of the second processing module is disposed on a side of the second PMOS region close to the active pattern of the first processing module.

13. The readout circuit layout of claim 11, wherein in the preset direction, the active pattern of the first PMOS region is disposed on a side of the first NMOS region away from the active pattern of the second processing module, the active pattern of the first processing module is disposed on a side of the first NMOS region close to the active pattern of the second processing module, the active pattern of the second PMOS region is disposed on a side of the second NMOS region away from the active pattern of the first processing module, and the active pattern of the second processing module is disposed on a side of the second NMOS region close to the active pattern of the first processing module.

14. A sense circuit layout of claim 13, wherein the active pattern of the first process block, the active pattern of the second process block, the active pattern of the first NMOS region and the active pattern of the second NMOS region are arranged in the same well region.

15. A readout circuit layout as claimed in claim 2, wherein in said preset direction the active pattern length of said first NMOS region is greater than the active pattern length of said first PMOS region; the active pattern length of the second NMOS region is greater than the active pattern length of the second PMOS region.

16. A readout circuit layout as claimed in claim 2, wherein the gate pattern of the first NMOS region, the gate pattern of the second NMOS region, the gate pattern of the first PMOS region, and the gate pattern of the second PMOS region are arranged along the preset direction, and the gate pattern of the first processing block and the gate pattern of the second processing block are arranged along a direction perpendicular to the preset direction.

17. A memory layout comprising a plurality of read out circuit layouts according to any of claims 1 to 16; the reading circuit layouts are sequentially arranged in the vertical direction of the preset direction, the adjacent reading circuit layouts form a reading circuit layout group, the reading circuit layout group shares the same active pattern, and the distance between the reading circuit layout groups is equal.

18. The memory layout of claim 17, wherein the sense amplifier module of the sense circuit layout comprises: the first NMOS area and the first PMOS area are arranged close to the first processing module, and the second NMOS area and the second PMOS area are arranged close to the second processing module; the first processing module, the first NMOS region, the first PMOS region, the second processing module, the second NMOS region and the second PMOS region are arranged along the preset direction; the active patterns of the first NMOS region and the second NMOS region are arranged independently, and the active patterns of the first PMOS region and the second PMOS region are arranged independently.

19. The memory layout of claim 18, wherein the active pattern of the first NMOS region and the active pattern of the second NMOS region are symmetrically disposed, and the active pattern of the first PMOS region and the active pattern of the second PMOS region are symmetrically disposed.

20. The memory layout of claim 19, wherein the locations of the active patterns of the first processing module and the second processing module are symmetrically arranged.

21. The memory layout of claim 20, further comprising: and a connection pattern disposed at an edge of the pre-charged region and contacting the active patterns of the pre-charged region, the connection pattern being for contacting all the active patterns of the pre-charged region in a direction perpendicular to the preset direction.

22. A sensing circuit structure, comprising:

the circuit comprises sense amplifiers, a first processing circuit and a second processing circuit which are arranged along a preset direction, wherein the sense amplifiers are used for sensing the voltage of a bit line, and the first processing circuit and the second processing circuit are at least used for carrying out noise elimination on output signals of the sense amplifiers;

the first processing circuit comprises: a first offset canceling structure, a first isolation structure and an equalizing structure arranged along the preset direction, the first offset canceling structure being configured to connect the bit line to a complementary sense bit line, the first isolation structure being configured to connect the bit line to a sense bit line, the equalizing structure being configured to connect the sense bit line to the complementary sense bit line;

the second processing circuit comprises: a precharge structure, a second isolation structure, and a second offset canceling structure arranged along the preset direction, the precharge structure configured to precharge the sense bit line and the complementary sense bit line based on a precharge command, the second isolation structure configured to connect the complementary bit line to the complementary sense bit line, the second offset canceling structure configured to connect the complementary bit line to the sense bit line;

wherein the active layer of the first offset canceling structure, the active layer of the first isolation structure, and the active layer of the equalizing structure are separately disposed from each other, and the active layer of the pre-charge structure, the active layer of the second isolation structure, and the active layer of the second offset canceling structure are separately disposed from each other.