CN115565567A

CN115565567A - Read-out circuit structure

Info

Publication number: CN115565567A
Application number: CN202110751227.XA
Authority: CN
Inventors: 池性洙; 张凤琴; 金书延
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2021-07-02
Filing date: 2021-07-02
Publication date: 2023-01-03

Abstract

The embodiment of the present application provides a readout circuit structure, which is disposed in a gap of a memory array, and includes: a first sense amplifying circuit coupled to one of the adjacent memory arrays through a first bit line and coupled to the other of the adjacent memory arrays through a first complementary bit line, for sensing a voltage of a memory cell of the memory arrays and outputting a logic 1 or 0 corresponding to the voltage; one of the source electrode or the drain electrode of the first equalizing tube is connected with a first bit line; one of the source electrode or the drain electrode of the second equalizing pipe is connected with the first complementary bit line; the first equalizing tube and the second equalizing tube are respectively arranged on two opposite sides of the first sensing amplifying circuit and used for precharging the voltage of the first bit line and the voltage of the first complementary bit line to a preset voltage according to the equalizing signal so as to solve the problem of low precharging speed of the memory.

Description

Read-out circuit structure

Technical Field

The present application relates to the field of memory layout design, and in particular, to a read circuit structure.

Background

Dynamic Random Access Memory (DRAM) is a semiconductor Memory device commonly used in computers, and is composed of many repetitive Memory cells. Each memory cell generally includes a capacitor and a transistor, a gate of the transistor is connected to a word line, a drain of the transistor is connected to a bit line, and a source of the transistor is connected to the capacitor, and a voltage signal on the word line can control the transistor to be turned on or off, so that data information stored in the capacitor can be read through the bit line or written into the capacitor through the bit line for storage.

The DRAM may be classified into a Double Data Rate (DDR) DRAM, a GDDR DRAM, and a Low Power Double Data Rate (LPDDR) DRAM. With the increasing field of DRAM application, such as the increasing application of DRAM to the mobile field, the user's requirement for DRAM power consumption index is higher and higher.

However, the performance of current DRAMs is still to be improved.

Disclosure of Invention

The embodiment of the application provides a sensing circuit structure to solve the problem of low memory pre-charging speed.

To solve the above technical problem, an embodiment of the present invention provides a sensing circuit structure disposed in a gap of a memory array, including: a first sense amplifying circuit coupled to one of the adjacent memory arrays through a first bit line and coupled to the other of the adjacent memory arrays through a first complementary bit line, for sensing a voltage of a memory cell of the memory array and outputting a logic 1 or 0 corresponding to the voltage; one of the source electrode or the drain electrode of the first equalizing tube is connected with a first bit line; one of the source electrode or the drain electrode of the second equalizing pipe is connected with the first complementary bit line; the first equalizing tube and the second equalizing tube are respectively arranged on two opposite sides of the first sensing amplifying circuit and used for precharging the voltage of the first bit line and the voltage of the first complementary bit line to a preset voltage according to the equalizing signal.

Compared with the prior art, one end of the source electrode or the drain electrode of the first equalizing pipe is directly connected with the first bit line and used for directly precharging the first bit line, one end of the source electrode or the drain electrode of the second equalizing pipe is directly connected with the first complementary bit line and used for directly precharging the first complementary bit line, namely, the equalizing pipe is directly connected with the bit line/complementary bit line and directly charges the bit line and the complementary bit line, the condition that the bit line/complementary bit line can be precharged only by switching on the switching transistor in the precharging process is avoided, and therefore the charging speed of the first bit line and the first complementary bit line connected with the first sensing amplifying circuit is increased.

In addition, the readout circuit structure further includes: a second sense amplifier circuit disposed adjacent to the first sense amplifier circuit in a bit line extending direction, coupling one of the adjacent memory arrays through a second bit line, coupling the other of the adjacent memory arrays through a second complementary bit line, sensing a voltage of the memory cell and outputting a logic 1 or 0 corresponding to the voltage; one of the source electrode or the drain electrode of the third equalizing pipe is connected with the second bit line; one of the source electrode or the drain electrode of the fourth equalizing pipe is connected with the second complementary bit line; the third equalizing tube and the fourth equalizing tube are respectively arranged on two opposite sides of the second sensing amplifying circuit and are used for precharging the voltage of the second bit line and the voltage of the second complementary bit line to a preset voltage according to the equalizing signals. One end of the source electrode or the drain electrode of the third equalizing tube is directly connected with the second bit line and used for directly pre-charging the second bit line, one end of the source electrode or the drain electrode of the fourth equalizing tube is directly connected with the second complementary bit line and used for directly pre-charging the second complementary bit line, namely, the equalizing tube is directly connected with the bit line/complementary bit line and directly charges the bit line and the complementary bit line, so that the condition that the bit line/complementary bit line can be pre-charged only by conducting a switching transistor in the pre-charging process is avoided, and the charging speed of the second bit line and the second complementary bit line connected with the second sensing amplifying circuit is increased.

In addition, the readout circuit structure further includes: the read-write conversion circuit is used for writing data into the storage units of the storage array or reading the data in the storage units; the first equalizing tube and the fourth equalizing tube are symmetrically arranged based on the read-write conversion circuit; the second equalizing tube and the third equalizing tube are symmetrically arranged based on the read-write conversion circuit.

In addition, the first equalizing pipe is arranged on one side of the first sensing amplifying circuit, which is far away from the second sensing amplifying circuit; the second equalizing pipe is arranged between the first sensing amplifying circuit and the second sensing amplifying circuit; the third equalizing pipe is arranged between the second sensing amplifying circuit and the first sensing amplifying circuit; the fourth equalizing pipe is arranged on one side, far away from the first sensing amplifying circuit, of the second sensing amplifying circuit.

In addition, the first complementary bit line passes through the area where the second sensing amplifying circuit is located and is coupled with the first sensing amplifying circuit, and is not electrically connected with the second sensing amplifying circuit; the second bit line passes through the area where the first sensing amplifying circuit is located and is coupled with the second sensing amplifying circuit, and is not electrically connected with the first sensing amplifying circuit. The first complementary bit line penetrates through the area where the second sensing amplifying circuit is located and is coupled with the first sensing amplifying circuit, namely the first complementary bit line does not need to occupy extra layout area to complete wiring, and therefore the layout area of the reading circuit structure is reduced.

In addition, the equalization signal includes a first equalization signal and a second equalization signal, and the preset voltage includes a first precharge voltage and a second precharge voltage; a first equalizing pipe, wherein the grid electrode is used for receiving a first equalizing signal, one of the source electrode or the drain electrode is used for receiving a first pre-charging voltage, and the other one is connected with a first bit line; and the grid of the second equalizing pipe is used for receiving a second equalizing signal, one of the source electrode or the drain electrode is used for receiving a second pre-charging voltage, and the other one is connected with the first complementary bit line.

In addition, the equalization signals further comprise a third equalization signal and a fourth equalization signal, and the preset voltage comprises a third pre-charge voltage and a fourth pre-charge voltage; a third equalizing pipe, wherein the grid electrode is used for receiving a third equalizing signal, one of the source electrode or the drain electrode is used for receiving a third pre-charging voltage, and the other one is connected with a second bit line; and the grid of the fourth equalizing pipe is used for receiving a fourth equalizing signal, one of the source or the drain is used for receiving a fourth pre-charging voltage, and the other one is connected with a second complementary bit line.

The first equalized signal and the third equalized signal are the same equalized signal, and the second equalized signal and the fourth equalized signal are the same equalized signal.

The first precharge voltage and the third precharge voltage are the same precharge voltage, and the second precharge voltage and the fourth precharge voltage are the same precharge voltage.

In addition, the first sense amplifying circuit includes: a sense amplifying module connected to the first bit line through a sense bit line and the first complementary bit line through a complementary sense bit line, for sensing a voltage of the memory cell and outputting a logic 1 or 0 corresponding to the voltage; the isolation module is connected between the complementary read bit line and the first complementary bit line, is connected between the read bit line and the first bit line, and is used for isolating signal interaction among the first bit line, the first complementary bit line, the read bit line and the complementary read bit line according to an isolation signal; and the offset elimination module is connected between the read bit line and the first complementary bit line, is connected between the complementary read bit line and the first bit line, and is used for adjusting the source-drain conduction difference between NMOS tubes or PMOS tubes in the sensing amplification module according to the offset elimination signal.

In addition, the sense amplifying module includes: the gate of the first sense amplification N tube is connected with the first bit line, the drain of the first sense amplification N tube is connected with the complementary read bit line, the source of the first sense amplification N tube is connected with the second signal end, and when the sense amplification module is in an amplification stage, the second signal end is electrically connected with the voltage corresponding to the logic 0; a grid electrode of the second sensing amplification N tube is connected with the first complementary bit line, a drain electrode of the second sensing amplification N tube is connected with the read bit line, and a source electrode of the second sensing amplification N tube is connected with a second signal end; the gate of the first sense amplification P tube is connected with the read bit line, the drain of the first sense amplification P tube is connected with the complementary read bit line, the source of the first sense amplification P tube is connected with the first signal end, and when the sense amplification module is in an amplification stage, the first signal end is electrically connected with the voltage corresponding to the logic 1; and the grid electrode of the second sensing amplifying P tube is connected with the complementary read bit line, the drain electrode of the second sensing amplifying P tube is connected with the read bit line, and the source electrode of the second sensing amplifying P tube is connected with the first signal end.

In addition, the extension directions of the grid structure of the first sensing amplification N tube, the grid structure of the second sensing amplification N tube, the grid structure of the first sensing amplification P tube and the grid structure of the second sensing amplification P tube are the same, the extension directions of the grid structure of the MOS tube in the isolation module and the grid structure of the MOS tube in the offset elimination module are the same, and the extension directions of the grid structure of the first sensing amplification N tube and the grid structure of the MOS tube in the isolation module are perpendicular to each other.

In addition, the first sensing amplification P pipe, the second sensing amplification P pipe, the isolation module and the offset elimination module are arranged between the first sensing amplification N pipe and the second sensing amplification N pipe.

In addition, the isolation module includes: the grid electrode of the first isolation tube is used for receiving an isolation signal, the source electrode of the first isolation tube is connected with a first bit line, and the drain electrode of the first isolation tube is connected with a read bit line; and the grid of the second isolation tube is used for receiving an isolation signal, the source of the second isolation tube is connected with the first complementary bit line, and the drain of the second isolation tube is connected with the complementary reading bit line.

In addition, the offset canceling module includes: the grid electrode of the first offset eliminating tube is used for receiving an offset eliminating signal, the source electrode of the first offset eliminating tube is connected with a first bit line, and the drain electrode of the first offset eliminating tube is connected with a complementary reading bit line; and the grid of the second offset eliminating tube is used for receiving the offset eliminating signal, the source of the second offset eliminating tube is connected with the first complementary bit line, and the drain of the second offset eliminating tube is connected with the read bit line.

In addition, the source electrode of the first isolation tube is communicated with the source electrode of the first offset elimination tube and is connected with a first bit line; the source electrode of the second isolation tube is connected with the source electrode of the second offset elimination tube and is connected with the first complementary bit line.

In addition, the readout circuit structure further includes: a third sense amplifying circuit disposed adjacent to the first sense amplifying circuit, wherein the third sense amplifying circuit couples one of the adjacent memory arrays through a third bitline and couples the other of the adjacent memory arrays through a third complementary bitline; one of the source electrode or the drain electrode of the fifth equalizing pipe is connected with a third bit line; one of the source electrode or the drain electrode of the sixth equalizing pipe is connected with the third complementary bit line; the fifth equalizing tube and the sixth equalizing tube are respectively arranged on two opposite sides of the third sensing amplifying circuit and are used for precharging the voltage of the third bit line and the voltage of the third complementary bit line to a preset voltage according to the equalizing signal; the first equalizing pipe is communicated with part of active areas of the fifth equalizing pipe and used for receiving preset voltage, and the second equalizing pipe is communicated with part of active areas of the sixth equalizing pipe and used for receiving the preset voltage.

In addition, the first equalizing tube and the fifth equalizing tube share the same grid and are used for receiving equalizing signals; the second equalizing tube and the sixth equalizing tube share the same grid and are used for receiving the equalizing signals.

Drawings

Fig. 1 is a schematic structural diagram of a 1 × 2 readout circuit structure provided in an embodiment of the present application;

fig. 2 is a schematic structural diagram of a 2 × 2 readout circuit structure according to an embodiment of the present disclosure;

fig. 3 is a schematic circuit structure diagram of a first sense amplifier circuit and a third sense amplifier circuit provided in an embodiment of the present application;

fig. 4 is a schematic circuit structure diagram of a second sense amplifying circuit and a fourth sense amplifying circuit provided in the embodiment of the present application;

fig. 5 is a layout of a first sense amplifier circuit, a second sense amplifier circuit, a third sense amplifier circuit, and a fourth sense amplifier circuit according to an embodiment of the present disclosure.

Detailed Description

It is known in the art that the performance of the prior art DRAM is still to be improved.

The applicant finds that, in the pre-charging process of the bit line and the complementary bit line, the existing sense amplifier with the offset compensation function includes the conducting process of the switching transistor, so that the charging speed of the bit line and the complementary bit line is not fast enough, and as the size of the transistor is further reduced, the saturation current of the switching transistor is reduced, which is more serious and is not beneficial to improving the read-write performance of the memory.

To solve the above problem, an embodiment of the present application provides a sensing circuit structure disposed in a gap of a memory array, including: a first sense amplifying circuit coupled to one of the adjacent memory arrays through a first bit line and coupled to the other of the adjacent memory arrays through a first complementary bit line, for sensing a voltage of a memory cell of the memory arrays and outputting a logic 1 or 0 corresponding to the voltage; one of the source electrode or the drain electrode of the first equalizing pipe is connected with a first bit line; one of the source electrode or the drain electrode of the second equalizing pipe is connected with the first complementary bit line; the first equalizing tube and the second equalizing tube are respectively arranged on two opposite sides of the first sensing amplifying circuit and used for precharging the voltage of the first bit line and the voltage of the first complementary bit line to a preset voltage according to the equalizing signal.

To make the objects, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the various embodiments of the present application, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments. The following embodiments are divided for convenience of description, and should not constitute any limitation to the specific implementation manner of the present application, and the embodiments may be combined with each other and referred to each other without contradiction.

Fig. 1 is a schematic structural diagram of a 1 × 2 readout circuit structure provided in this embodiment, fig. 2 is a schematic structural diagram of a 2 × 2 readout circuit structure provided in this embodiment, fig. 3 is a schematic circuit structural diagram of a first sense amplifier circuit and a third sense amplifier circuit provided in this embodiment, fig. 4 is a schematic circuit structural diagram of a second sense amplifier circuit and a fourth sense amplifier circuit provided in this embodiment, fig. 5 is a layout of the first sense amplifier circuit, the second sense amplifier circuit, the third sense amplifier circuit, and the fourth sense amplifier circuit provided in this embodiment, and the following describes in detail the readout circuit structure provided in this embodiment with reference to the drawings:

referring to fig. 1, a sensing circuit structure, disposed in a gap of a memory array 101, includes:

the first sense amplifier circuit 113 is coupled to one memory array 101 of the adjacent memory arrays 101 through a first bit line BL1, and coupled to the other memory array 101 of the adjacent memory arrays 101 through a first complementary bit line BLB1, for sensing a voltage of a memory cell of the memory array 101 and outputting a logic 1 or 0 corresponding to the voltage.

In the present embodiment, in order to clearly distinguish the above-mentioned one memory array 101 from the other memory array 101, in the following description, the memory array 101 to which the first sense amplifying circuit 113 is connected through the first bit line BL1 is referred to as a "first memory array"; the memory array 101 in which the first sense amplifying circuit 113 is connected through the first complementary bit line BLB1 is referred to as a "second memory array".

The first equalizing pipe < N1>, one of the source or the drain is connected to the first bit line BL1 and the second equalizing pipe < N2>, and one of the source or the drain is connected to the first complementary bit line BLB1, for precharging the voltage of the first bit line BL1 and the voltage of the first complementary bit line BLB1 to a predetermined voltage according to an equalizing signal.

One end of the source electrode or the drain electrode of the first equalizing pipe < N1> is directly connected with the first bit line BL1 and is used for directly precharging the first bit line BL1, one end of the source electrode or the drain electrode of the second equalizing pipe < N2> is directly connected with the first complementary bit line BLB1 and is used for directly precharging the first complementary bit line BLB1, namely, the equalizing pipe is directly connected with the bit line/complementary bit line and directly charges the bit line and the complementary bit line, so that the condition that the bit line/complementary bit line can be precharged only by switching on a switching transistor in the precharging process is avoided, and the charging speed of the first bit line BL1 and the first complementary bit line BLB1 connected with the first sensing amplifying circuit 113 is increased.

Wherein, the first equalizing pipe < N1> and the second equalizing pipe < N2> are arranged at two opposite sides of the first sensing amplifying circuit 113; specifically, the first equalizing pipe < N1> is disposed on a side of the first sense amplifying circuit 113 away from the second sense amplifying circuit 123, that is, the first equalizing pipe < N1> is disposed between the first sense amplifying circuit 113 and the "first memory array", and the second equalizing pipe < N2> is disposed between the first sense amplifying circuit 113 and the second sense amplifying circuit 123.

It should be noted that, the above-mentioned "preset voltage" is the voltage required for precharging in the memory precharging stage, and the specific voltage magnitude is set according to the precharge voltage required for normal operation of the memory, and this embodiment does not constitute a limitation on the value of the "preset voltage".

With continuing reference to fig. 1, in this embodiment, the readout circuit structure further includes: a read-write conversion circuit 102 for writing external data into the memory cells of the memory array 101 or reading data from the memory cells.

In the present embodiment, the read-write conversion circuit 102 is provided between the first sense amplification circuit 113 and the second sense amplification circuit 123; in other embodiments, the read-write conversion circuit may also be disposed between the first sense amplifying circuit and the memory array or between the second sense amplifying circuit and the memory array.

The memory array 101 has n rows and m columns of memory cells, each memory cell is used for storing 1bit (bit) data, that is, a memory array 101 can store n × mbit data, and in the data reading process, the memory cells are read out or written with data by gating the specific memory cells.

The second sense amplifier circuit 123, disposed adjacent to the first sense amplifier circuit 113 in the bit line extending direction, is coupled to one memory array 101 of the adjacent memory arrays 101 through a second bit line BL2, and is coupled to the other memory array 101 of the adjacent memory arrays 101 through a second complementary bit line BLB2, for sensing a voltage of a memory cell and outputting a logic 1 or 0 corresponding to the voltage.

And one of the source electrode or the drain electrode of the third equalizing pipe < N3> is connected with the second bit line BL2 and the fourth equalizing pipe < N4>, and one of the source electrode or the drain electrode of the third equalizing pipe < N4> is connected with the second complementary bit line BLB2, and is used for precharging the voltage of the second bit line BL2 and the voltage of the second complementary bit line BLB2 to a preset voltage according to an equalizing signal.

One end of the source or the drain of the third equalizing pipe < N3> is directly connected with the second bit line BL2 and is used for directly precharging the second bit line BL2, and one end of the source or the drain of the fourth equalizing pipe < N4> is directly connected with the second complementary bit line BLB2 and is used for directly precharging the second complementary bit line BLB2, that is, the equalizing pipe is directly connected with the bit line/complementary bit line and directly charges the bit line and the complementary bit line, so that the situation that the bit line/complementary bit line can be precharged only by switching on the switching transistor during the precharging process is avoided, and the charging speed of the second bit line BL2 and the second complementary bit line BLB2 connected with the second sensing amplifying circuit 123 is increased.

Wherein, the third equalizing tube < N3> and the fourth equalizing tube < N4> are disposed at two opposite sides of the second sensing amplifying circuit 123; specifically, the third equalizing pipe < N3> is disposed between the second sense amplifying circuit 123 and the first sense amplifying circuit 113; the fourth equalizing pipe < N4> is disposed at a side of the second sense amplifying circuit 123 far from the first sense amplifying circuit 113, i.e., the fourth equalizing pipe < N4> is disposed between the second sense amplifying circuit 123 and the "second memory array".

Specifically, the first complementary bit line BLB1 is coupled to the first sense amplifying circuit 113 through the region where the second sense amplifying circuit 123 is located, and is not electrically connected to the second sense amplifying circuit 123; the second bit line BL2 is coupled to the second sense amplifying circuit 123 through a region where the first sense amplifying circuit 113 is located, and is not electrically connected to the first sense amplifying circuit 113. The first complementary bit line BLB1 passes through the region where the second sense amplifying circuit 123 is located to be coupled with the first sense amplifying circuit 113, that is, the first complementary bit line BLB1 does not need to occupy an extra layout area to complete the wiring, thereby further reducing the layout area of the sensing circuit structure, and the second bit line BL2 passes through the region where the first sense amplifying circuit 113 is located to be coupled with the second sense amplifying circuit 123, that is, the second bit line BL2 does not need to occupy an extra layout area to complete the wiring, thereby reducing the layout area of the sensing circuit structure.

For the first equalization tube < N1> and the second equalization tube < N2>: in one example, the equalizing signal includes a first equalizing signal and a second equalizing signal, the preset voltage includes a first pre-charge voltage and a second pre-charge voltage, the gate of the first equalizing pipe < N1> is used for receiving the first equalizing signal, one of the source or the drain is used for receiving the first pre-charge voltage, and the other is connected with the first bit line BL1; the gate of the second equalizing pipe < N2> is used for receiving the second equalizing signal, one of the source or the drain is used for receiving the second pre-charge voltage, and the other is connected with the first complementary bit line BLB1.

The first equalizing pipe < N1> and the second equalizing pipe < N2> respectively receive the first equalizing signal and the second equalizing signal, thereby independently controlling the first bit line BL1 and the first complementary bit line BLB1 connected to the first sense amplifier circuit 113, and further, independently precharging the first bit line BL1 and the first complementary bit line BLB1 connected to the first sense amplifier circuit 113 by precharging the first bit line BL1 to a first precharge voltage based on the first equalizing signal and precharging the first complementary bit line BLB1 to a second precharge voltage based on the second equalizing signal.

For the third equalization tube < N3> and the fourth equalization tube < N4>: in one example, the equalizing signals include a third equalizing signal and a fourth equalizing signal, the preset voltages include a third pre-charge voltage and a fourth pre-charge voltage, a gate of the third equalizing pipe < N3> is used for receiving the third equalizing signal, one of a source or a drain is used for receiving the third pre-charge voltage, and the other is connected with the second bit line BL2; the gate of the fourth equalizing pipe < N4> is used for receiving the fourth equalizing signal, one of the source or the drain is used for receiving the fourth precharge voltage, and the other is connected with the second complementary bit line BLB2.

The third equalizing pipe < N3> and the fourth equalizing pipe < N4> respectively receive the third equalizing signal and the fourth equalizing signal, so that the second bit line BL2 and the second complementary bit line BLB2 connected to the second sensing amplifier circuit 123 are independently controlled, and in addition, the second bit line BL2 is precharged to a third precharge voltage based on the third equalizing signal, the second complementary bit line BLB2 is precharged to a fourth precharge voltage based on the fourth equalizing signal, so that the second bit line BL2 and the second complementary bit line BLB2 connected to the second sensing amplifier circuit 123 are independently precharged.

In another example, the first equalizing signal and the third equalizing signal are the same equalizing signal, that is, the equalizing pipes for precharging the first bit line BL1 and the second bit line BL2 are controlled by the same signal; the second equalization signal and the fourth equalization signal are the same equalization signal, i.e., the equalization pipes for precharging the first complementary bit line BLB1 and the second complementary bit line BLB2 are controlled by the same signal.

Further, the first precharge voltage and the third precharge voltage are the same precharge voltage, i.e., for controlling the first bit line BL1 and the second bit line BL2 to be precharged to the same precharge voltage; the second precharge voltage and the fourth precharge voltage are the same precharge voltage, i.e., for controlling the first complementary bit line BLB1 and the second complementary bit line BLB2 to be precharged to the same precharge voltage.

As will be appreciated by those skilled in the art, there are a plurality of sense amplifier circuits for between adjacent memory arrays 101. Specifically, a plurality of sense amplifier circuits are arranged in a word line extending direction (where the word line extending direction is perpendicular to a bit line extending direction), and referring to fig. 2, the present embodiment further describes the layout of the sense amplifier circuit and the equalizing pipe provided by the present embodiment with a 2 × 2 sense amplifier circuit layout, and in the word line extending direction, other sense amplifier circuit structures are consistent with the 2 × 2 sense amplifier circuit layout shown in the figure.

Similar to the connection structure of the first sense amplifier circuit 113, the third sense amplifier circuit 133 is coupled to the "first memory array" through the third bit line BL3 and the "second memory array" through the third complementary bit line BLB3, wherein the fifth equalizing pipe < N5> is used for precharging the third bit line BL3 and the sixth equalizing pipe < N6> is used for precharging the third complementary bit line BLB3.

Specifically, the third sense amplifier circuit 133 is disposed adjacent to the first sense amplifier circuit 113, and is coupled to one memory array 101 of the adjacent memory arrays 101 through the third bit line BL3, and is coupled to the other memory array 101 of the adjacent memory arrays 101 through the third complementary bit line BLB3.

The fifth equalizing pipe < N5>, one of the source or the drain is connected to the third bit line BL3, the sixth equalizing pipe < N6>, and one of the source or the drain is connected to the third complementary bit line BLB3, for precharging the voltage of the third bit line BL3 and the voltage of the third complementary bit line BLB3 to a predetermined voltage according to the equalizing signal.

Wherein, the fifth equalizing pipe < N5> and the sixth equalizing pipe < N6> are disposed at two opposite sides of the third sensing amplifying circuit 133; specifically, the fifth equalizing pipe < N5> is disposed on a side of the third sense amplifying circuit 133 away from the fourth sense amplifying circuit 143, that is, the fifth equalizing pipe < N5> is disposed between the third sense amplifying circuit 133 and the "first storage array", and the sixth equalizing pipe < N6> is disposed between the third sense amplifying circuit 133 and the fourth sense amplifying circuit 143.

Similar to the connection structure of the second sense amplifying circuit 123, the fourth sense amplifying circuit 143 is coupled to the "second memory array" through the fourth bit line BL4, and is coupled to the "second memory array" through the fourth complementary bit line BLB4, wherein the seventh equalizing pipe < N7> is used for precharging the fourth bit line BL4, and the eighth equalizing pipe < N8> is used for precharging the fourth complementary bit line BLB4.

Specifically, the fourth sense amplifier circuit 143 is disposed adjacent to the second sense amplifier circuit 123, and is coupled to one memory array 101 of the adjacent memory arrays 101 through the fourth bit line BL4, and is coupled to the other memory array 101 of the adjacent memory arrays 101 through the fourth complementary bit line BLB4.

And one of the source or the drain of the seventh equalizing pipe < N7> is connected with the fourth bit line BL4 and the eighth equalizing pipe < N8>, and one of the source or the drain of the seventh equalizing pipe < N8> is connected with the fourth complementary bit line BLB4, and is used for precharging the voltage of the fourth bit line BL4 and the voltage of the fourth complementary bit line BLB4 to preset voltages according to the equalizing signal.

Wherein, the seventh equalizing pipe < N7> and the eighth equalizing pipe < N8> are disposed at opposite sides of the fourth sensing amplifying circuit 143; specifically, the seventh equalizing pipe < N7> is disposed between the fourth sense amplifying circuit 143 and the third sense amplifying circuit 133; the eighth equalizing pipe < N8> is disposed at a side of the fourth sense amplifying circuit 143 away from the third sense amplifying circuit 133, i.e., the eighth equalizing pipe < N8> is disposed between the fourth sense amplifying circuit 143 and the "second memory array".

During the pre-charging process, for the first equalizing pipe < N1>, the second equalizing pipe < N2>, the third equalizing pipe < N3> and the fourth equalizing pipe < N4>:

in one example, the preset voltages include a first precharge voltage, a second precharge voltage, a third precharge voltage, and a fourth precharge voltage. Wherein, the grid of the first equalizing pipe < N1> is used for receiving a first equalizing signal EQ1, one of the source electrode or the drain electrode is used for receiving a first pre-charging voltage, and the other one is connected with a first bit line BL1; the grid electrode of the second equalizing pipe < N2> is used for receiving a second equalizing signal EQ2, one of the source electrode or the drain electrode is used for receiving a second pre-charging voltage, and the other one is connected with the first complementary bit line BLB1; the grid electrode of the third equalizing pipe < N3> is used for receiving the first equalizing signal EQ1, one of the source electrode or the drain electrode is used for receiving a third pre-charging voltage, and the other one is connected with a second bit line BL2; the gate of the fourth equalizing pipe < N4> is used for receiving the second equalizing signal EQ2, one of the source or the drain is used for receiving the fourth precharge voltage, and the other is connected to the second complementary bit line BLB2.

In another example, the first precharge voltage and the third precharge voltage are the same precharge voltage, the second precharge voltage and the fourth precharge voltage are the same precharge voltage, i.e., the voltage used to precharge the bit lines is the same precharge voltage, and the voltage used to precharge the complementary bit lines is the same precharge voltage. Further, referring to fig. 3 and 4, the first precharge voltage, the second precharge voltage, the third precharge voltage and the fourth precharge voltage are the same precharge voltage, that is, the precharge voltage for precharging the sense amplifying circuit is the same precharge voltage V _BLP (ii) a In the present embodiment, the precharge voltage V _BLP ＝1/2V _DD Wherein V is _DD Is the chip internal supply voltage; in other embodiments, the precharge voltage V _BLP The setting may be made according to a specific application scenario.

Referring to fig. 3 and 4, as for the first sense amplifier circuit 113 and the third sense amplifier circuit 133, the first sense amplifier circuit 113 is taken as an example to be described in detail below, and the first sense amplifier circuit 113 (refer to fig. 2) includes:

and a sense amplifying block connected to the first bit line BL1 through the sense bit line SABL and connected to the first complementary bit line BLB1 through the complementary sense bit line SABLB for sensing a voltage of the memory cell and outputting a logic 1 or 0 corresponding to the voltage.

Specifically, a sense amplifier module includes: the first sense amplifying N transistor < N1400>, the grid electrode is connected with a first bit line BL1, the drain electrode is connected with a complementary reading bit line SABLB, the source electrode is connected with a second signal end NCS, and when the sense amplifying module is in an amplifying stage, the second signal end NCS is electrically connected with a voltage corresponding to logic 0; a second sense amplifier N transistor < N1405>, a gate connected to the first complementary bit line BLB1, a drain connected to the sense bit line SABL, and a source connected to the second signal terminal NCS; when the sensing amplification module is in an amplification stage, the first signal end PCS is electrically connected with voltage corresponding to logic 1; the second sense amplifying P-transistor < P1400>, the gate connected to the complementary sensing bit line SABLB, the drain connected to the sensing bit line SABL, and the source connected to the first signal terminal PCS.

And an isolation module connected between the complementary sensing bit line SABLB and the first complementary bit line BLB1, and connected between the sensing bit line SABL and the first bit line BL1, for isolating the first bit line BL1, the first complementary bit line BLB1 and signal interaction between the sensing bit line SABL and the complementary sensing bit line SABLB according to an isolation signal ISO.

Specifically, an isolation module comprising: a first isolation transistor < N1402>, a gate for receiving an isolation signal ISO, a source connected to the first bit line BL1, a drain connected to the sense bit line SABL, and a second isolation transistor < N1403>, a gate for receiving the isolation signal ISO, a source connected to the first complementary bit line BLB1, and a drain connected to the complementary sense bit line SABLB.

And the offset elimination module is connected between the sensing bit line SABL and the first complementary bit line BLB1, and connected between the complementary sensing bit line SABLB and the first bit line BL1, and is used for adjusting the source-drain conduction difference between the NMOS tubes or the PMOS tubes in the sensing amplification module according to the offset elimination signal OC.

It should be noted that the above-mentioned "source-drain conduction difference" refers to: the first and second sense-amplifying N-transistors < N1400> and N1405> and the first and second sense-amplifying P-transistors < P1401> and P1400> may have different threshold voltages from each other due to variations in manufacturing processes, temperatures, and the like. In this case, the sense amplification module may cause offset noise due to a difference between threshold voltages of the first and second sense amplification P-tubes < P1401> and < P1400> and the first and second sense amplification N-tubes < N1400> and < N1405 >.

Specifically, the offset canceling module includes: a first offset cancellation transistor < N1401>, having a gate for receiving an offset cancellation signal OC, a source connected to the first bit line BL1, and a drain connected to the complementary sensing bit line SABLB; a second offset cancellation transistor < N1404>, having a gate for receiving an offset cancellation signal OC, a source connected to the first complementary bit line BLB1, and a drain connected to the sensing bit line SABL.

Those skilled in the art will appreciate that the structure of the third sense amplifier circuit 133 is the same as that of the first sense amplifier circuit 113, and the above description applies equally when replacing features of the corresponding structure. Specifically, the corresponding structure includes: the first bit line BL1 corresponds to BL3, the first complementary bit line BLB1 corresponds to BLB3, the first equalizing pipe < N1> corresponds to < N5>, the third equalizing pipe < N3> corresponds to < N7>, the first sense amplifier N pipe < N1400> corresponds to < N1410>, the second sense amplifier N pipe < N1405> corresponds to < N1415>, the first sense amplifier P pipe < P > corresponds to < P1411>, the second sense amplifier P pipe < P1400> corresponds to < P1410>, the first isolation pipe < N1402> corresponds to < N1412>, the second isolation pipe < N1403> corresponds to < N1413>, the first offset canceller pipe < N1401> corresponds to < N1411> and the second offset canceller pipe < N > 1404 corresponds to < N1414>.

Referring to fig. 3 and 4, regarding the second sense amplifying circuit 123 and the fourth sense amplifying circuit 143, the second sense amplifying circuit 123 is taken as an example to be described in detail below, and the second sense amplifying circuit 123 (refer to fig. 2) includes:

and a sense amplifying block connected to the second bit line BL2 through the sense bit line SABL and connected to the second complementary bit line BLB2 through the complementary sense bit line SABLB for sensing a voltage of the memory cell and outputting a logic 1 or 0 corresponding to the voltage.

Specifically, a sense amplifier module includes: a third sense amplifying N-tube < N1425>, a gate connected to the second bit line BL2, a drain connected to the complementary read bit line SABLB, and a source connected to the second signal terminal NCS, wherein when the sense amplifying module is in an amplifying stage, the second signal terminal NCS is electrically connected to a voltage corresponding to a logic 0; a fourth sense amplifying N transistor < N1420>, the gate of which is connected to the second complementary bit line BLB2, the drain of which is connected to the readout bit line SABL, and the source of which is connected to the second signal terminal NCS; a third sense amplifying P tube < P1421>, a gate connected to the sense bit line SABL, a drain connected to the complementary sense bit line SABLB, a source connected to the first signal terminal PCS, and when the sense amplifying module is in an amplifying stage, the first signal terminal PCS is electrically connected to a voltage corresponding to logic 1; the fourth sense amplifier P-transistor < P1420>, has a gate connected to the complementary sense bitline SABLB, a drain connected to the sense bitline SABL, and a source connected to the first signal terminal PCS.

And an isolation module connected between the complementary sensing bit line SABLB and the second complementary bit line BLB2, and connected between the sensing bit line SABL and the second bit line BL2, for isolating the second bit line BL2, the second complementary bit line BLB2 from signal interaction between the sensing bit line SABL and the complementary sensing bit line SABLB according to an isolation signal ISO.

Specifically, an isolation module includes: a first isolation transistor < N1423>, a gate for receiving an isolation signal ISO, a source connected to the second bit line BL2, a drain connected to the sense bit line SABL, and a second isolation transistor < N1422>, a gate for receiving an isolation signal ISO, a source connected to the second complementary bit line BLB2, and a drain connected to the complementary sense bit line SABLB.

And the offset elimination module is connected between the sensing bit line SABL and the second complementary bit line BLB2, and connected between the complementary sensing bit line SABLB and the second bit line BL2, and is used for adjusting the source-drain conduction difference between the NMOS tubes or the PMOS tubes in the sensing amplification module according to the offset elimination signal OC.

It should be noted that the above-mentioned "source-drain conduction difference" refers to: the third and fourth sense amp Npipe < N1425> and N1420> and the third and fourth sense amp pT < P1421> and P1420> may have different threshold voltages from each other due to variations in manufacturing processes, temperatures, etc. In this case, the sense amplification module may cause offset noise due to a difference between threshold voltages of the third and fourth sense amplification P-tubes < P1421> and P1420> and the third and fourth sense amplification N-tubes < N1445> and N1420 >.

Specifically, the offset canceling module includes: a third offset cancellation transistor < N1424>, having a gate for receiving an offset cancellation signal OC, a source connected to the second bit line BL2, and a drain connected to the complementary sensing bit line SABLB; a fourth offset cancellation transistor < N1421>, having a gate for receiving the offset cancellation signal OC, a source connected to the second complementary bit line BLB2, and a drain connected to the sensing bit line SABL.

Those skilled in the art will appreciate that the structure of the fourth sense amplifier circuit 143 is the same as that of the second sense amplifier circuit 123, and the above description applies equally after replacing the features of the corresponding structure. Specifically, the corresponding structure includes: the second bitline BL2 corresponds to BL4, the second complementary bitline BLB2 corresponds to BLB4, the second equalizing pipe < N2> corresponds to < N6>, the fourth equalizing pipe < N4> corresponds to < N8>, the third sense-amp N pipe < N1425> corresponds to < N1435>, the fourth sense-amp N pipe < N1420> corresponds to < N1430>, the third sense-amp P pipe < P1421> corresponds to < P1431>, the fourth sense-amp P pipe < P1420> corresponds to < P >, the third isolation pipe < N1423> corresponds to < N1433>, the fourth isolation pipe < N1422> corresponds to < N1432>, the third offset-cancel pipe < N1424> corresponds to < N1434>, the fourth offset-cancel pipe < N1421> corresponds to < N1431.

Referring to fig. 5, the left side is a layout of the first sense amplifier circuit 113 (refer to fig. 2) and the third sense amplifier circuit 133 (refer to fig. 2), and the right side is a layout of the second sense amplifier circuit 123 (refer to fig. 2) and the fourth sense amplifier circuit 143 (refer to fig. 2).

For fig. 5, the oblique frame region is the layout of the active layer, the white frame region is the layout of the gate layer, and the shadow region is the layout of the contact layer. In the figure, a solid arrow passes through the layout of the contact layer, which shows that the structure represented by the solid arrow is in contact with the contact layer; any areas through which the dashed arrows pass do not touch each other.

For the left-side layout, the following steps are performed from top to bottom in sequence: the device comprises a first equalizing tube layout, a first sensing amplification N tube layout, a first offset isolation layout, a first sensing amplification P tube layout, a second offset isolation layout, a second sensing amplification N tube layout and a second equalizing tube layout.

As can be seen from the figure, in the present embodiment, the gate structures of the first sensing amplification N transistor < N1400>, the second sensing amplification N transistor < N1405>, the first sensing amplification P transistor < P1401> and the second sensing amplification P transistor < P1400 extend in the same direction, the gate structures of the MOS transistors in the isolation module and the offset cancellation module extend in the same direction, and the gate structures of the first sensing amplification N transistor < N1400> and the MOS transistors in the isolation module extend in the direction perpendicular to each other.

As can be seen, in the present embodiment, the first sense amplifier P pipe < P1401>, the second sense amplifier P pipe < P1400>, the isolation module and the offset cancellation module are disposed between the first sense amplifier N pipe < N1400> and the second sense amplifier N pipe < N1405 >.

For the first equalizing pipe layout, partial active areas of the first equalizing pipe < N1> and the fifth equalizing pipe < N5> are communicated and used for receiving preset voltage.

Specifically, referring to FIG. 5, in this embodiment, a first equalization tube<N1>Source electrode and fifth equalizing tube<N5>For receiving a pre-charge voltage V _BLP First equalizing tube<N1>To connect the first bit line BL1, a fifth equalizing pipe<N5>To connect to the third bit line BL3.

In addition, the first equalizing pipe < N1> and the fifth equalizing pipe < N5> share the same grid electrode for receiving the equalizing signals.

For the second equalizing pipe layout, the partial active areas of the second equalizing pipe < N2> and the sixth equalizing pipe < N6> are communicated and used for receiving preset voltage.

Specifically, referring to FIG. 5, in the present embodiment, a second equalizing tube<N2>Source electrode and sixth equalizing tube<N6>For receiving a pre-charge voltage V _BLP Second equalizing tube<N2>To connect the first complementary bit line BLB1, the sixth equalizing pipe<N6>To connect to a third complementary bitline BLB3.

In addition, the second equalizer tube < N2> and the sixth equalizer tube < N6> share the same gate for receiving the equalizing signal.

For the first offset isolation layout and the second offset isolation layout, the source of the first isolation pipe < N1402> is communicated with the source of the first offset cancellation pipe < N1401>, and is connected with the first bit line BL1; the source of the second isolation transistor < N1403> is connected to the source of the second offset cancellation transistor < N1404> and to the first complementary bit line BLB1.

For the right layout, the following steps are performed from top to bottom: the device comprises a first balanced tube layout, a first sensing amplification N tube layout, a first offset isolation layout, a first sensing amplification P tube layout, a first offset isolation layout, a first sensing amplification N tube layout and a first balanced tube layout.

As can be seen from the figure, in the present embodiment, the gate structures of the third sense amplifying N-transistor < N1425>, the fourth sense amplifying N-transistor < N1420>, the third sense amplifying P-transistor < P1421> and the fourth sense amplifying P-transistor < P1420> have the same extending direction, the gate structures of the MOS transistors in the isolation module and the offset canceling module have the same extending direction, and the gate structures of the third sense amplifying N-transistor < N1425> and the MOS transistors in the isolation module have the perpendicular extending direction.

As can be seen, in the present embodiment, the third sense amplifier P pipe < P1421>, the fourth sense amplifier P pipe < P1420>, the isolation module and the offset cancellation module are disposed between the third sense amplifier N pipe < N1425> and the fourth sense amplifier N pipe < N1420 >.

For the third equalizing pipe layout, partial active areas of the third equalizing pipe < N3> and the seventh equalizing pipe < N7> are communicated and used for receiving preset voltage.

Specifically, referring to FIG. 5, in this embodiment, a third equalization tube<N3>Source electrode and seventh equalizing tube<N7>For receiving a pre-charge voltage V _BLP Third equalizing tube<N3>To connect the second bit line BL2, a seventh equalizing pipe<N7>To connect to the fourth bit line BL4.

In addition, the third equalizer tube < N3> and the seventh equalizer tube < N7> share the same gate for receiving the equalized signal.

For the fourth equalizing pipe layout, the partial active regions of the fourth equalizing pipe < N4> and the eighth equalizing pipe < N8> are communicated and used for receiving preset voltage.

Specifically, referring to FIG. 5, in the present embodiment, a fourth equalizing tube<N4>Source electrode and eighth equalizing tube<N8>For receiving a pre-charge voltage V _BLP Fourth equalizing tube<N4>To connect the second complementary bit line BLB2, an eighth equalizing pipe<N8>To connect to a fourth complementary bit line BLB4.

In addition, the fourth equalizing tube < N4> and the eighth equalizing tube < N8> share the same gate for receiving the equalizing signal.

For the third offset isolation layout and the fourth offset isolation layout, the source of the third isolation pipe < N1423> is communicated with the source of the third offset cancellation pipe < N1424>, and is connected with the second bit line BL2; the source of the fourth isolation pipe < N1422> is connected to the source of the fourth offset cancellation pipe < N1421>, and the second complementary bit line BLB2 is connected.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementations of the present application and that various changes in form and details may be made therein without departing from the spirit and scope of the present application.

Claims

1. A sensing circuit structure disposed in a gap between adjacent memory arrays, comprising:

a first sense amplifying circuit coupled to one of the adjacent memory arrays through a first bit line and coupled to the other of the adjacent memory arrays through a first complementary bit line, for sensing a voltage of a memory cell of the memory array and outputting a logic 1 or 0 corresponding to the voltage;

one of the source electrode or the drain electrode of the first equalizing pipe is connected with the first bit line;

one of the source electrode or the drain electrode of the second equalizing pipe is connected with the first complementary bit line;

the first equalizing tube and the second equalizing tube are respectively arranged on two opposite sides of the first sensing amplifying circuit and used for precharging the voltage of the first bit line and the voltage of the first complementary bit line to a preset voltage according to an equalizing signal.

2. The sensing circuit structure of claim 1, further comprising:

a second sense amplifying circuit disposed adjacent to the first sense amplifying circuit in a bit line extending direction, coupled to one of the adjacent memory arrays through a second bit line, coupled to the other of the adjacent memory arrays through a second complementary bit line, for sensing a voltage of the memory cell and outputting a logic 1 or 0 corresponding to the voltage;

one of the source electrode or the drain electrode of the third equalizing pipe is connected with the second bit line;

one of the source electrode or the drain electrode of the fourth equalizing pipe is connected with the second complementary bit line;

the third equalizing tube and the fourth equalizing tube are respectively arranged on two opposite sides of the second sensing amplifying circuit and are used for precharging the voltage of the second bit line and the voltage of the second complementary bit line to the preset voltage according to the equalizing signal.

3. A sensing circuit structure of claim 2, further comprising:

the read-write conversion circuit is used for writing data into the storage units of the storage array or reading the data in the storage units;

the first equalizing tube and the fourth equalizing tube are symmetrically arranged based on the read-write conversion circuit;

the second equalizing tube and the third equalizing tube are symmetrically arranged based on the read-write conversion circuit.

4. A sensing circuit structure of claim 2, comprising:

the first equalizing pipe is arranged on one side, away from the second sensing amplifying circuit, of the first sensing amplifying circuit; the second equalizing pipe is arranged between the first sensing amplifying circuit and the second sensing amplifying circuit;

the third equalizing pipe is arranged between the second sensing amplifying circuit and the first sensing amplifying circuit; the fourth equalizing pipe is arranged on one side, far away from the first sensing amplifying circuit, of the second sensing amplifying circuit.

5. The sensing circuit structure of claim 2, wherein the first complementary bit line is coupled to the first sense amplifier circuit through a region where the second sense amplifier circuit is located, and is not electrically connected to the second sense amplifier circuit; the second bit line passes through the area where the first sensing amplification circuit is located and is coupled with the second sensing amplification circuit, and is not electrically connected with the first sensing amplification circuit.

6. The sensing circuit structure of claim 2, wherein the equalization signal comprises a first equalization signal and a second equalization signal, and the preset voltage comprises a first precharge voltage and a second precharge voltage;

the gate of the first equalizing pipe is used for receiving the first equalizing signal, one of the source electrode or the drain electrode is used for receiving a first pre-charging voltage, and the other one is connected with the first bit line;

the second equalizing pipe has a gate for receiving the second equalizing signal, a source or a drain for receiving a second pre-charge voltage, and the other connected to the first complementary bit line.

7. The sensing circuit structure of claim 6, wherein the equalized signals further include a third equalized signal and a fourth equalized signal, and the preset voltage includes a third pre-charge voltage and a fourth pre-charge voltage;

the gate of the third equalizing pipe is used for receiving the third equalizing signal, one of the source electrode or the drain electrode is used for receiving a third pre-charging voltage, and the other one is connected with the second bit line;

the fourth equalizing pipe has a gate for receiving the fourth equalizing signal, one of a source or a drain for receiving a fourth pre-charge voltage, and the other connected to the second complementary bit line.

8. A sensing circuit arrangement according to claim 7, wherein the first equalized signal and the third equalized signal are the same equalized signal, and the second equalized signal and the fourth equalized signal are the same equalized signal.

9. A sensing circuit arrangement according to claim 7 or 8, wherein the first and third pre-charge voltages are the same pre-charge voltage and the second and fourth pre-charge voltages are the same pre-charge voltage.

10. A readout circuit structure according to claim 1, wherein the first sense amplifying circuit includes:

a sense amplifying module connected to the first bit line through a sense bit line and the first complementary bit line through a complementary sense bit line, for sensing a voltage of the memory cell and outputting a logic 1 or 0 corresponding to the voltage;

the isolation module is connected between the complementary sensing bit line and the first complementary bit line, is connected between the sensing bit line and the first bit line, and is used for isolating signal interaction between the first bit line and the first complementary bit line and between the sensing bit line and the complementary sensing bit line according to an isolation signal;

and the offset elimination module is connected between the read bit line and the first complementary bit line, is connected between the complementary read bit line and the first bit line, and is used for adjusting the source-drain conduction difference between NMOS tubes or PMOS tubes in the sensing amplification module according to an offset elimination signal.

11. The readout circuit structure of claim 10, wherein the sense amplifying module comprises:

a gate of the first sense amplifying N transistor is connected with the first bit line, a drain of the first sense amplifying N transistor is connected with the complementary read bit line, and a source of the first sense amplifying N transistor is connected with a second signal end;

a grid electrode of the second sensing amplification N tube is connected with the first complementary bit line, a drain electrode of the second sensing amplification N tube is connected with the read bit line, and a source electrode of the second sensing amplification N tube is connected with the second signal end;

a gate of the first sense amplifying P-transistor is connected to the read bit line, a drain of the first sense amplifying P-transistor is connected to the complementary read bit line, and a source of the first sense amplifying P-transistor is connected to a first signal terminal, wherein when the sense amplifying module is in an amplifying stage, the first signal terminal is electrically connected to a voltage corresponding to a logic 1;

and the grid electrode of the second sensing amplification P tube is connected with the complementary read bit line, the drain electrode of the second sensing amplification P tube is connected with the read bit line, and the source electrode of the second sensing amplification P tube is connected with the first signal end.

12. The readout circuit structure of claim 11, wherein the gate structures of the first sense amplifying N transistor, the second sense amplifying N transistor, the first sense amplifying P transistor and the second sense amplifying P transistor extend in the same direction, the gate structures of the MOS transistors in the isolation module and the offset cancellation module extend in the same direction, and the gate structures of the first sense amplifying N transistor and the MOS transistors in the isolation module extend in the direction perpendicular to each other.

13. The readout circuit structure of claim 11, wherein the first sense amplifier P-transistor, the second sense amplifier P-transistor, the isolation module, and the offset cancellation module are disposed between the first sense amplifier N-transistor and the second sense amplifier N-transistor.

14. The sensing circuit structure of claim 10, wherein the isolation module comprises:

the grid electrode of the first isolation tube is used for receiving the isolation signal, the source electrode of the first isolation tube is connected with the first bit line, and the drain electrode of the first isolation tube is connected with the read bit line;

and the grid of the second isolation tube is used for receiving the isolation signal, the source of the second isolation tube is connected with the first complementary bit line, and the drain of the second isolation tube is connected with the complementary reading bit line.

15. The readout circuit structure of claim 14, wherein the offset cancellation block comprises:

a first offset cancellation tube, wherein a grid electrode is used for receiving the offset cancellation signal, a source electrode is connected with the first bit line, and a drain electrode is connected with the complementary reading bit line;

and the grid of the second offset elimination tube is used for receiving the offset elimination signal, the source of the second offset elimination tube is connected with the first complementary bit line, and the drain of the second offset elimination tube is connected with the read bit line.

16. The sensing circuit structure of claim 15, wherein the source of the first isolation pipe and the source of the first offset cancellation pipe are in communication and are connected to the first bit line; and the source electrode of the second isolation tube is connected with the source electrode of the second offset elimination tube and is connected with the first complementary bit line.

17. A sensing circuit structure of claim 1, further comprising:

a third sense amplifying circuit disposed adjacent to the first sense amplifying circuit, wherein the third sense amplifying circuit couples one of the adjacent memory arrays through a third bitline and couples the other of the adjacent memory arrays through a third complementary bitline;

one of a source electrode or a drain electrode of the fifth equalizing pipe is connected with the third bit line;

one of a source electrode or a drain electrode of the sixth equalizing pipe is connected with the third complementary bit line;

the fifth equalizing tube and the sixth equalizing tube are respectively arranged on two opposite sides of the third sensing amplifying circuit and are used for precharging the voltage of the third bit line and the voltage of the third complementary bit line to the preset voltage according to an equalizing signal;

and the first equalizing pipe is communicated with part of active areas of the fifth equalizing pipe and is used for receiving the preset voltage, and the second equalizing pipe is communicated with part of active areas of the sixth equalizing pipe and is used for receiving the preset voltage.

18. The sensing circuit structure of claim 17, wherein the first equalizing tube and the fifth equalizing tube share a same gate for receiving the equalizing signal; the second equalizing tube and the sixth equalizing tube share the same grid and are used for receiving the equalizing signals.