CN115565568A

CN115565568A - Read-out circuit structure

Info

Publication number: CN115565568A
Application number: CN202110751234.XA
Authority: CN
Inventors: 池性洙; 金书延; 张凤琴
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2021-07-02
Filing date: 2021-07-02
Publication date: 2023-01-03
Anticipated expiration: 2041-07-02
Also published as: CN115565568B

Abstract

The embodiment of the present application provides a readout circuit structure, which is disposed in a gap of a memory array, and includes: the first equalizing pipe group comprises a first equalizing pipe, a third equalizing pipe, a fifth equalizing pipe and a seventh equalizing pipe; the source electrode of the first equalizing tube, the source electrode of the third equalizing tube, the source electrode of the fifth equalizing tube and the source electrode of the seventh equalizing tube are connected, the drain electrode of the first equalizing tube is directly connected to the first bit line, the drain electrode of the third equalizing tube is directly connected to the second bit line, the drain electrode of the fifth equalizing tube is directly connected to the third bit line, and the drain electrode of the seventh equalizing tube is directly connected to the fourth bit line; the grid electrode of the first equalizing tube is connected with the grid electrode of the fifth equalizing tube and is used for receiving a first equalizing signal; and the grid electrode of the third equalizing tube is connected with the grid electrode of the seventh equalizing tube and is used for receiving the second equalizing signal, so that the precharging is controlled based on different control signals on the basis of solving the problem of low precharging speed of the memory, and the layout area of the reading circuit structure is reduced.

Description

Read-out circuit structure

Technical Field

The present application relates to the field of memory layout design, and in particular, to a read circuit structure.

Background

Dynamic Random Access Memory (DRAM) is a semiconductor Memory device commonly used in computers, and is composed of many repetitive Memory cells. Each memory cell generally includes a capacitor and a transistor, a gate of the transistor is connected to a word line, a drain of the transistor is connected to a bit line, and a source of the transistor is connected to the capacitor, and a voltage signal on the word line can control the transistor to be turned on or off, so that data information stored in the capacitor can be read through the bit line or written into the capacitor through the bit line for storage.

The DRAM may be classified into a Double Data Rate (DDR) DRAM, a GDDR DRAM, and a Low Power Double Data Rate (LPDDR) DRAM. With the increasing application fields of DRAM, such as the increasing application of DRAM to mobile fields, the demands of users on DRAM power consumption indexes are higher and higher.

However, the performance of current DRAMs is still to be improved.

Disclosure of Invention

The embodiment of the application provides a read circuit structure, which realizes the control of pre-charging based on different control signals on the basis of solving the problem of low pre-charging speed of a memory and is also used for reducing the layout area of the read circuit structure.

To solve the above technical problem, an embodiment of the present application provides a sensing circuit structure disposed in a gap of a memory array, including: the first equalizing pipe group comprises a first equalizing pipe, a third equalizing pipe, a fifth equalizing pipe and a seventh equalizing pipe; the source electrode of the first equalizing tube, the source electrode of the third equalizing tube, the source electrode of the fifth equalizing tube and the active region where the source electrode of the seventh equalizing tube is located are connected, the drain electrode of the first equalizing tube is directly connected to the first bit line, the drain electrode of the third equalizing tube is directly connected to the second bit line, the drain electrode of the fifth equalizing tube is directly connected to the third bit line, and the drain electrode of the seventh equalizing tube is directly connected to the fourth bit line; the first bit line, the second bit line, the third bit line and the fourth bit line are four adjacent bit lines in the same memory array; the gate of the first equalizing tube is connected with the gate of the fifth equalizing tube, and the first equalizing tube is used for receiving a first equalizing signal and precharging the first bit line and the third bit line to a preset voltage based on the first equalizing signal; and the grid electrode of the third equalizing tube is connected with the grid electrode of the seventh equalizing tube and is used for receiving the second equalizing signal and precharging the second bit line and the fourth bit line to a preset voltage based on the second equalizing signal.

Compared with the prior art, the drain electrode of the first equalizing pipe is directly connected with the first bit line and used for directly precharging the first bit line, the drain electrode of the third equalizing pipe is directly connected with the second bit line and used for directly precharging the second bit line, the drain electrode of the fifth equalizing pipe is directly connected with the third bit line and used for directly precharging the third bit line, and the drain electrode of the seventh equalizing pipe is directly connected with the fourth bit line and used for directly precharging the fourth bit line, namely, the drain electrode of the equalizing pipe is directly connected with the bit line and directly charges the bit line, so that the situation that the bit line can be precharged only by switching on the switching transistor in the precharging process is avoided, and the charging speed of the bit line is accelerated; the source electrode of the first equalizing tube, the source electrode of the third equalizing tube, the source electrode of the fifth equalizing tube and the active region where the source electrode of the seventh equalizing tube is located are connected, namely the source electrode of the first equalizing tube, the source electrode of the third equalizing tube, the source electrode of the fifth equalizing tube and the source electrode of the seventh equalizing tube adopt the same source electrode, so that the layout area of the first equalizing tube group is reduced, and the layout area of the reading circuit structure is reduced; furthermore, the grid electrodes of the first equalizing tube and the fifth equalizing tube are connected and used for receiving the first equalizing signal, and the grid electrodes of the third equalizing tube and the seventh equalizing tube are connected and used for receiving the second equalizing signal, so that the pre-charging of different bit lines is controlled based on different control signals.

In addition, the readout circuit structure further includes: the second equalizing pipe group comprises a second equalizing pipe, a fourth equalizing pipe, a sixth equalizing pipe and an eighth equalizing pipe; the source electrode of the second equalizing tube, the source electrode of the fourth equalizing tube, the source electrode of the sixth equalizing tube and the active region where the source electrode of the eighth equalizing tube is located are connected, the drain electrode of the second equalizing tube is directly connected to the first complementary bit line, the drain electrode of the fourth equalizing tube is directly connected to the second complementary bit line, the drain electrode of the sixth equalizing tube is directly connected to the third complementary bit line, and the drain electrode of the eighth equalizing tube is directly connected to the fourth complementary bit line; the first complementary bit line, the second complementary bit line, the third complementary bit line and the fourth complementary bit line are four adjacent complementary bit lines in the same memory array; the gate of the second equalizing tube is connected with the gate of the sixth equalizing tube, and is used for receiving the third equalizing signal and precharging the first complementary bit line and the third complementary bit line to the precharge voltage based on the third equalizing signal, and the gate of the fourth equalizing tube is connected with the gate of the eighth equalizing tube, and is used for receiving the fourth equalizing signal and precharging the second complementary bit line and the fourth complementary bit line to the precharge voltage based on the fourth equalizing signal. The drain electrode of the second equalizing pipe is directly connected with the first complementary bit line and used for directly precharging the first complementary bit line, the drain electrode of the fourth equalizing pipe is directly connected with the second complementary bit line and used for directly precharging the second complementary bit line, the drain electrode of the sixth equalizing pipe is directly connected with the third complementary bit line and used for directly precharging the third complementary bit line, and the drain electrode of the eighth equalizing pipe is directly connected with the fourth complementary bit line and used for directly precharging the fourth complementary bit line, namely, the equalizing pipe is directly connected with the complementary bit lines and directly charges the complementary bit lines, so that the condition that the complementary bit lines can be precharged only by switching on a switching transistor in the precharging process is avoided, and the charging speed of the complementary bit lines is accelerated; the source electrode of the second equalizing tube, the source electrode of the fourth equalizing tube, the source electrode of the sixth equalizing tube and the source electrode of the eighth equalizing tube are connected in the active region, namely the source electrode of the second equalizing tube, the source electrode of the fourth equalizing tube, the source electrode of the sixth equalizing tube and the source electrode of the eighth equalizing tube adopt the same source electrode, so that the layout area of the second equalizing tube group is reduced, and the layout area of the reading circuit structure is reduced; furthermore, the gates of the second equalizing tube and the sixth equalizing tube are connected and used for receiving the third equalizing signal, and the gates of the fourth equalizing tube and the eighth equalizing tube are connected and used for receiving the fourth equalizing signal, so that the pre-charging of different complementary bit lines is controlled based on different control signals.

In addition, the readout circuit structure further includes: a first sense amplifying circuit and a second sense amplifying circuit adjacently disposed along a bit line extending direction for sensing a voltage of the memory cell and outputting a logic 1 or 0 corresponding to the voltage, wherein the first sense amplifying circuit couples one of the adjacent memory arrays through a first bit line and couples the other of the adjacent memory arrays through a first complementary bit line, and the second sense amplifying circuit couples one of the adjacent memory arrays through a second bit line and couples the other of the adjacent memory arrays through a second complementary bit line; and the third sense amplifying circuit and the fourth sense amplifying circuit are adjacently arranged along the extension direction of the bit line, the third sense amplifying circuit and the first sense amplifying circuit are adjacently arranged in the word line direction, the fourth sense amplifying circuit and the second sense amplifying circuit are adjacently arranged in the word line direction, the third sense amplifying circuit is coupled with one memory array in the adjacent memory arrays through a third bit line, the other memory array in the adjacent memory arrays is coupled through a third complementary bit line, the fourth sense amplifying circuit is coupled with one memory array in the adjacent memory arrays through a fourth bit line, and the other memory array in the adjacent memory arrays is coupled through a fourth complementary bit line.

In addition, the first complementary bit line passes through the area where the second sensing amplifying circuit is located and is coupled with the first sensing amplifying circuit, and is not electrically connected with the second sensing amplifying circuit; the second bit line passes through the area where the first sensing amplifying circuit is located and is coupled with the second sensing amplifying circuit and is not electrically connected with the first sensing amplifying circuit; the third complementary bit line passes through the area where the fourth sensing amplifying circuit is located and is coupled with the third sensing amplifying circuit, and is not electrically connected with the fourth sensing amplifying circuit; the fourth bit line passes through the area where the third sensing amplifying circuit is located and is coupled with the fourth sensing amplifying circuit, and is not electrically connected with the third sensing amplifying circuit. The first complementary bit line penetrates through the region where the second sensing amplifying circuit is located and is coupled with the first sensing amplifying circuit, namely the first complementary bit line does not need to occupy extra layout area to complete wiring, so that the layout area of the reading circuit structure is reduced, the second bit line penetrates through the region where the first sensing amplifying circuit is located and is coupled with the second sensing amplifying circuit, namely the second bit line does not need to occupy extra layout area to complete wiring, so that the layout area of the reading circuit structure is reduced.

In addition, the first equalizing pipe group is arranged on one side of the first sensing amplifying circuit and the third sensing amplifying circuit far away from the second sensing amplifying circuit and the fourth sensing amplifying circuit; the second equalizing pipe group is arranged on one side, away from the first sensing amplifying circuit and the third sensing amplifying circuit, of the second sensing amplifying circuit and the fourth sensing amplifying circuit.

In addition, the readout circuit structure further includes: the read-write conversion circuit is used for writing external data into the storage units of the storage array or reading the data in the storage units; the first equalizing pipe group and the second equalizing pipe group are symmetrically arranged based on the read-write conversion circuit.

In addition, the first equalized signal and the second equalized signal are the same equalized signal.

The third equalized signal and the fourth equalized signal are the same equalized signal.

In addition, the first sense amplifying circuit includes: a sense amplifying module connected to the first bit line through a sense bit line and the first complementary bit line through a complementary sense bit line, for sensing a voltage of the memory cell and outputting a logic 1 or 0 corresponding to the voltage; the isolation module is connected between the complementary read bit line and the first complementary bit line, is connected between the read bit line and the first bit line, and is used for isolating signal interaction among the first bit line, the first complementary bit line, the read bit line and the complementary read bit line according to an isolation signal; and the offset elimination module is connected between the read bit line and the first complementary bit line, is connected between the complementary read bit line and the first bit line, and is used for adjusting the source-drain conduction difference between NMOS tubes or PMOS tubes in the sensing amplification module according to the offset elimination signal.

In addition, the sense amplifying module includes: the gate of the first sense amplification N tube is connected with the first bit line, the drain of the first sense amplification N tube is connected with the complementary read bit line, the source of the first sense amplification N tube is connected with the second signal end, and when the sense amplification module is in an amplification stage, the second signal end is electrically connected with the voltage corresponding to the logic 0; the grid electrode of the second sensing amplification N tube is connected with the first complementary bit line, the drain electrode of the second sensing amplification N tube is connected with the read bit line, and the source electrode of the second sensing amplification N tube is connected with the second signal end; the gate of the first sense amplification P tube is connected with the read bit line, the drain of the first sense amplification P tube is connected with the complementary read bit line, the source of the first sense amplification P tube is connected with the first signal end, and when the sense amplification module is in an amplification stage, the first signal end is electrically connected with the voltage corresponding to the logic 1; and the grid electrode of the second sensing amplifying P tube is connected with the complementary reading bit line, the drain electrode of the second sensing amplifying P tube is connected with the reading bit line, and the source electrode of the second sensing amplifying P tube is connected with the first signal end.

In addition, the extension directions of the grid structure of the first sensing amplification N tube, the grid structure of the second sensing amplification N tube, the grid structure of the first sensing amplification P tube and the grid structure of the second sensing amplification P tube are the same, the extension directions of the grid structure of the MOS tube in the isolation module and the grid structure of the MOS tube in the offset elimination module are the same, and the extension directions of the grid structure of the first sensing amplification N tube and the grid structure of the MOS tube in the isolation module are perpendicular to each other.

In addition, the first sensing amplification P pipe, the second sensing amplification P pipe, the isolation module and the offset elimination module are arranged between the first sensing amplification N pipe and the second sensing amplification N pipe.

In addition, the isolation module includes: the grid electrode of the first isolation tube is used for receiving an isolation signal, the source electrode of the first isolation tube is connected with a first bit line, and the drain electrode of the first isolation tube is connected with a read bit line; and the grid of the second isolation tube is used for receiving an isolation signal, the source of the second isolation tube is connected with the first complementary bit line, and the drain of the second isolation tube is connected with the complementary reading bit line.

In addition, the offset canceling module includes: the grid electrode of the first offset eliminating tube is used for receiving an offset eliminating signal, the source electrode of the first offset eliminating tube is connected with a first bit line, and the drain electrode of the first offset eliminating tube is connected with a complementary reading bit line; and the grid of the second offset eliminating tube is used for receiving the offset eliminating signal, the source of the second offset eliminating tube is connected with the first complementary bit line, and the drain of the second offset eliminating tube is connected with the read bit line.

In addition, the source electrode of the first isolation tube is communicated with the source electrode of the first offset elimination tube and is connected with a first bit line; the source electrode of the second isolation tube is connected with the source electrode of the second offset elimination tube and is connected with the first complementary bit line.

Drawings

Fig. 1 is a schematic structural diagram of a readout circuit structure according to an embodiment of the present disclosure;

fig. 2 is a schematic layout structure diagram of a first equalizing pipe group and a second equalizing pipe group according to an embodiment of the present application;

FIG. 3 is a schematic structural diagram of a first equalization tube bank provided in an embodiment of the present application;

fig. 4 is a schematic structural diagram of a second equalizing pipe group according to an embodiment of the present application;

fig. 5 is a schematic circuit structure diagram of a first sense amplifier circuit and a third sense amplifier circuit provided in an embodiment of the present application;

fig. 6 is a schematic circuit structure diagram of a second sense amplifying circuit and a fourth sense amplifying circuit provided in the embodiment of the present application;

fig. 7 is a layout of a first sense amplifier circuit, a second sense amplifier circuit, a third sense amplifier circuit, and a fourth sense amplifier circuit according to an embodiment of the present disclosure.

Detailed Description

As is known in the art, the performance of the prior art DRAM still remains to be improved.

The applicant finds that, in the pre-charging process of the bit line and the complementary bit line, the existing sense amplifier with the offset compensation function includes the conducting process of the switching transistor, so that the charging speed of the bit line and the complementary bit line is not fast enough, and as the size of the transistor is further reduced, the saturation current of the switching transistor is reduced, which is more serious and is not beneficial to improving the read-write performance of the memory.

To solve the above technical problem, an embodiment of the present application provides a sensing circuit structure disposed in a gap of a memory array, including: the first equalizing pipe group comprises a first equalizing pipe, a third equalizing pipe, a fifth equalizing pipe and a seventh equalizing pipe; the source electrode of the first equalizing tube, the source electrode of the third equalizing tube, the source electrode of the fifth equalizing tube and the active region where the source electrode of the seventh equalizing tube is located are connected, the drain electrode of the first equalizing tube is directly connected to the first bit line, the drain electrode of the third equalizing tube is directly connected to the second bit line, the drain electrode of the fifth equalizing tube is directly connected to the third bit line, and the drain electrode of the seventh equalizing tube is directly connected to the fourth bit line; the first bit line, the second bit line, the third bit line and the fourth bit line are four adjacent bit lines in the same memory array; the gate of the first equalizing tube is connected with the gate of the fifth equalizing tube, and the first equalizing tube is used for receiving a first equalizing signal and precharging the first bit line and the third bit line to a preset voltage based on the first equalizing signal; the grid electrode of the third equalizing tube and the grid electrode of the seventh equalizing tube are connected and used for receiving the second equalizing signal and precharging the second bit line and the fourth bit line to a preset voltage based on the second equalizing signal.

To make the objects, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the examples of the present application, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solutions claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments. The following embodiments are divided for convenience of description, and should not constitute any limitation to the specific implementation manner of the present application, and the embodiments may be combined with each other and referred to each other without contradiction.

Fig. 1 is a schematic structural diagram of a readout circuit structure provided in this embodiment, fig. 2 is a schematic structural diagram of a layout structure of a first equalizing pipe group and a second equalizing pipe group provided in this embodiment, fig. 3 is a schematic structural diagram of a first equalizing pipe group provided in this embodiment, fig. 4 is a schematic structural diagram of a second equalizing pipe group provided in this embodiment, fig. 5 is a schematic structural diagram of a circuit of a first sense amplifier circuit and a circuit of a third sense amplifier circuit provided in this embodiment, fig. 6 is a schematic structural diagram of a circuit of a second sense amplifier circuit and a circuit of a fourth sense amplifier circuit provided in this embodiment, fig. 7 is a layout of a first sense amplifier circuit, a second sense amplifier circuit, a third sense amplifier circuit and a fourth sense amplifier circuit provided in this embodiment, and the following describes in further detail a readout circuit structure provided in this embodiment with reference to the following drawings:

referring to fig. 1 and 2, a sensing circuit structure, disposed in a gap of a memory array 101, includes:

the memory array 101 has n rows and m columns of memory cells, each memory cell is used for storing 1bit (bit) data, that is, a memory array 101 can store n × m bit data, and in the data reading process, the memory cells are gated to read out the memory data in the memory cells or write data in the memory cells.

A first sense amplifier circuit 113 and a second sense amplifier circuit 123 adjacently disposed along a bit line extending direction, for sensing a voltage of the memory cell and outputting a logic 1 or 0 corresponding to the voltage; the first sense amplifying circuit 113 is coupled to one memory array 101 in the adjacent memory arrays 101 through a first bit line BL1, and is coupled to the other memory array 101 in the adjacent memory arrays 101 through a first complementary bit line BLB 1; the second sense amplifier circuit 123 is coupled to one memory array 101 of the adjacent memory arrays 101 through a second bit line BL2, and coupled to the other memory array 101 of the adjacent memory arrays 101 through a second complementary bit line BLB2.

A third sense amplifier circuit 133 and a fourth sense amplifier circuit 143, which are disposed adjacently along the extending direction of the bit lines, wherein the third sense amplifier circuit 133 and the first sense amplifier circuit 113 are disposed adjacently in the word line direction, and the fourth sense amplifier circuit 143 and the second sense amplifier circuit 123 are disposed adjacently in the word line direction, wherein the third sense amplifier circuit 133 is coupled to one memory array 101 of the adjacent memory arrays 101 through a third bit line BL3, and is coupled to the other memory array 101 of the adjacent memory arrays 101 through a third complementary bit line BLB 3; the fourth sense amplifying circuit 143 is coupled to one memory array 101 of the adjacent memory arrays 101 through a fourth bit line BL4, and coupled to the other memory array 101 of the adjacent memory arrays 101 through a fourth complementary bit line BLB 4.

The first bit line BL1, the second bit line BL2, the third bit line BL3 and the fourth bit line BL are four adjacent bit lines in the same memory array; the first complementary bit line BLB1, the second complementary bit line BLB2, the third complementary bit line BLB3, and the fourth complementary bit line BLB4 are four adjacent bit lines in the same memory array.

In the present embodiment, in order to clearly distinguish the above-mentioned one memory array 101 from the other memory array 101, in the following description, the memory array 101 to which the first sense amplifier circuit 113 is connected through the first bit line BL1 is referred to as a "first memory array"; the memory array 101 in which the second sense amplifying circuit 123 is connected through the second complementary bit line BLB2 is referred to as a "second memory array".

In this embodiment, the readout circuit structure further includes: and a read-write conversion circuit 102 for writing external data into the memory cells of the memory array 101 or reading data from the memory cells.

In the present embodiment, the read-write conversion circuit 102 is provided between the first sense amplifier circuit 113 and the third sense amplifier circuit 133, and the second sense amplifier circuit 123 and the fourth sense amplifier circuit 143; in other embodiments, the read-write conversion circuit may also be disposed between the first sense amplifier circuit and the third sense amplifier circuit or between the second sense amplifier circuit and the fourth sense amplifier circuit and the memory array.

The first equalizing tube set 114 includes a first equalizing tube < N1>, a third equalizing tube < N3>, a fifth equalizing tube < N5>, and a seventh equalizing tube < N7>.

The source electrode of the first equalizing tube < N1>, the source electrode of the third equalizing tube < N3>, the source electrode of the fifth equalizing tube < N5> and the source electrode of the seventh equalizing tube < N7> are connected in the active area; the drain electrode of the first equalizing pipe < N1> is directly connected with the first bit line BL1, the drain electrode of the third equalizing pipe < N3> is directly connected with the second bit line BL2, the drain electrode of the fifth equalizing pipe < N5> is directly connected with the third bit line BL3, and the drain electrode of the seventh equalizing pipe < N7> is directly connected with the fourth bit line BL4; the gate of the first equalizing tube < N1> is connected to the gate of the fifth equalizing tube < N5>, and the first equalizing tube < N1> is configured to receive a first equalizing signal and precharge the first bit line BL1 and the third bit line BL3 to a predetermined voltage based on the first equalizing signal; the gate of the third equalizing pipe < N3> and the gate of the seventh equalizing pipe < N7> are connected to receive the second equalizing signal, and precharge the second bit line BL2 and the fourth bit line BL4 to a predetermined voltage based on the second equalizing signal.

Since the first sense amplifier circuit 113 and the third sense amplifier circuit 133 are disposed at a position close to the first equalizing tube bank 114, and the second sense amplifier circuit 123 and the fourth sense amplifier circuit 143 are disposed at a position far from the first equalizing tube bank 114, that is, the line length of the second bit line BL2 and the line length of the fourth bit line BL4 are greater than the line length of the first bit line BL1 and the line length of the third bit line BL3, it is possible to set the second equalizing signal to be greater than the first equalizing signal, so that the charging speeds of the second bit line BL2 and the fourth bit line BL4 are greater than the charging speeds of the first bit line BL1 and the third bit line BL4, and the first bit line BL1 and the third bit line BL3 are precharged and the second bit line BL2 and the fourth bit line BL4 are precharged differently by different equalizing signals, thereby ensuring that the times for precharging the bit lines to the preset voltages are the same.

Referring to FIG. 3, a first equalizing pipe<N1>Source electrode, third equalizing tube<N3>Source electrode, fifth equalizing tube<N5>Source electrode and seventh equalizing tube<N7>Are connected and are commonly used for receiving the same preset voltage V _BLP (ii) a In the present embodiment, the precharge voltage V _BLP ＝1/2V _DD Wherein V is _DD Is the chip internal power supply voltage; in other embodiments, the precharge voltage V _BLP The setting can be carried out according to specific application scenes.

With continued reference to fig. 1 and 2, the second equalization tube bank 124 includes a second equalization tube < N2>, a fourth equalization tube < N4>, a sixth equalization tube < N6> and an eighth equalization tube < N8>.

The source electrode of the second equalizing pipe < N2>, the source electrode of the fourth equalizing pipe < N4>, the source electrode of the sixth equalizing pipe < N6> and the active region where the source electrode of the eighth equalizing pipe < N8> are positioned are connected; the drain electrode of the second equalizing pipe < N2> is directly connected with the first complementary bit line BLB1, the drain electrode of the fourth equalizing pipe < N4> is directly connected with the second complementary bit line BLB2, the drain electrode of the sixth equalizing pipe < N6> is directly connected with the third complementary bit line BLB3, and the drain electrode of the eighth equalizing pipe < N8> is directly connected with the fourth complementary bit line BLB4; the gate of the second equalizing transistor < N2> is connected to the gate of the sixth equalizing transistor < N6>, and the second equalizing transistor is configured to receive the third equalizing signal and precharge the first complementary bitline BLB1 and the third complementary bitline BLB3 to a predetermined voltage based on the third equalizing signal; the gate of the fourth equalizing pipe < N4> and the gate of the eighth equalizing pipe < N8> are connected to receive the fourth equalizing signal, and precharge the second complementary bit line BLB2 and the fourth complementary bit line BLB4 to a predetermined voltage based on the fourth equalizing signal.

Since the second sense amplifier circuit 123 and the fourth sense amplifier circuit 143 are disposed at a position close to the second equalizing pipe group 124, and the first sense amplifier circuit 113 and the third sense amplifier circuit 133 are disposed at a position far from the second equalizing pipe group 124, that is, the line length of the first complementary bit line BLB1 and the line length of the third complementary bit line BLB3 are greater than the line length of the second complementary bit line BLB2 and the line length of the fourth complementary bit line BLB4, it can be known that the third equalizing signal is set greater than the fourth equalizing signal, so that the charging speeds of the first complementary bit line BLB1 and the third complementary bit line BLB3 are greater than the charging speeds of the second complementary bit line BLB2 and the fourth complementary bit line BLB4, and the first complementary bit line BLB1 and the third complementary bit line BLB3 are precharged and the second complementary bit line BLB2 and the fourth complementary bit line BLB4 are precharged to the different complementary bit lines for the same time.

Referring to FIG. 4, a second equalizing tube<N2>Source electrode, fourth equalizing tube<N4>Source electrode, sixth equalizing tube<N6>Source electrode and eighth equalizing pipe of<N8>Are connected and are commonly used for receiving the same preset voltage V _BLP (ii) a In the present embodiment, the precharge voltage V _BLP ＝1/2V _DD Wherein, V _DD Is the chip internal power supply voltage; in other embodiments, the precharge voltage V _BLP The setting can be carried out according to specific application scenes.

The drain of the first equalizing pipe < N1> is directly connected with the first bit line BL1 for directly precharging the first bit line BL1, the drain of the second equalizing pipe < N2> is directly connected with the first complementary bit line BLB1 for directly precharging the first complementary bit line BLB1, the drain of the third equalizing pipe < N3> is directly connected with the second bit line BL2 for directly precharging the second bit line BL2, the drain of the fourth equalizing pipe < N4> is directly connected with the second complementary bit line BLB2 for directly precharging the second complementary bit line BLB2, the drain of the fifth equalizing pipe < N5> is directly connected with the third bit line BL3 for directly precharging the third bit line BL3, the drain of the sixth equalizing pipe < N6> is directly connected with the third complementary bit line BLB3 for directly precharging the third complementary bit line BLB3, the drain of the seventh equalizing pipe < N7> is directly connected with the fourth bit line BL4 for directly precharging the fourth bit line BL4, the drain of the eighth equalizing pipe < N8> is directly connected with the fourth complementary bit line BLB4, and the fourth equalizing pipe < b 4> is directly connected with the fourth bit line BLB4 for precharging, thereby preventing the direct precharging of the fourth bit line BL4 and the complementary bit line, the direct precharging transistor, and the direct precharging of the fourth equalizing pipe, and the complementary bit line, and the equalizing pipe, and the direct precharging of the complementary bit line, thereby preventing the direct precharging transistor from being conducted by the direct bit line.

In addition, the source electrode of the first equalizing tube, the source electrode of the third equalizing tube, the source electrode of the fifth equalizing tube and the active region where the source electrode of the seventh equalizing tube is located are connected, namely the source electrode of the first equalizing tube, the source electrode of the third equalizing tube, the source electrode of the fifth equalizing tube and the source electrode of the seventh equalizing tube adopt the same source electrode, so that the layout area of the first equalizing tube group is reduced; the source electrode of the second equalizing tube, the source electrode of the fourth equalizing tube, the source electrode of the sixth equalizing tube and the active region where the source electrode of the eighth equalizing tube are located are connected, namely the source electrode of the second equalizing tube, the source electrode of the fourth equalizing tube, the source electrode of the sixth equalizing tube and the source electrode of the eighth equalizing tube adopt the same source electrode, so that the layout area of the second equalizing tube group is reduced, and the layout area of the reading circuit structure is reduced.

Further, the first equalizing tube is connected with the grid of the fifth equalizing tube and used for receiving the first equalizing signal, the third equalizing tube is connected with the grid of the third equalizing tube and used for receiving the second equalizing signal, the second equalizing tube is connected with the grid of the sixth equalizing tube and used for receiving the third equalizing signal, and the fourth equalizing tube is connected with the grid of the eighth equalizing tube and used for receiving the fourth equalizing signal, so that the pre-charging of different complementary bit lines is controlled based on different control signals.

It should be noted that, in the above description, the connection manner of the specific "source" and the specific "drain" does not constitute a limitation to this embodiment, and in other embodiments, the connection manner of the "drain" instead of the "source" may be adopted, and the connection manner of the "source" instead of the "drain" may also be adopted.

It should be noted that, the above-mentioned "preset voltage" is the voltage required for precharging in the memory precharging stage, and the specific voltage magnitude is set according to the precharge voltage required for normal operation of the memory, and this embodiment does not constitute a limitation on the value of the "preset voltage".

In the example of the related art, a first equalizing pipe < N1> and a third equalizing pipe < N3> that precharge the first sense amplifying circuit 113 are respectively provided on both sides of the first sense amplifying circuit 113; a second equalizing tube < N2> and a fourth equalizing tube < N4> for precharging the second sense amplifying circuit 123 are respectively disposed at both sides of the second sense amplifying circuit 123; a fifth equalizing pipe < N5> and a seventh equalizing pipe < N7> for precharging the third sensing amplifying circuit 133 are respectively disposed at both sides of the third sensing amplifying circuit 133; a sixth equalizing pipe < N6> and an eighth equalizing pipe < N8> for precharging the fourth sensing amplifying circuit 143 are respectively disposed at both sides of the fourth sensing amplifying circuit 143.

With the present embodiment, the first equalizing tube group 114 is disposed on the side of the first sense amplifying circuit 113 and the third sense amplifying circuit 133 away from the second sense amplifying circuit 123 and the fourth sense amplifying circuit 143; namely, the second equalizing pipe < N2> pre-charged by the first complementary bit line BLB1 is disposed at a side of the second sense amplifying circuit 123 far from the first sense amplifying circuit 113, and the fourth equalizing pipe < N4> is originally disposed at a side of the second sense amplifying circuit 123 far from the first sense amplifying circuit 113, that is, the second equalizing pipe < N2> is disposed at a region where the fourth equalizing pipe < N4> is located, so as to reduce a layout region required by the layout of the original second equalizing pipe < N2>, thereby reducing the layout area of the readout circuit structure. The third equalizing pipe < N3> for precharging the second bit line BL2 is disposed on a side of the first sense amplifying circuit 113 away from the second sense amplifying circuit 123, and the first equalizing pipe < N1> is originally disposed on a side of the first sense amplifying circuit 113 away from the second sense amplifying circuit 123, that is, the third equalizing pipe < N3> is disposed in a region where the first equalizing pipe < N1> is located, so that a layout region required by the layout of the original third equalizing pipe < N3> is reduced, thereby reducing the layout area of the read circuit structure. The second equalizing pipe group 124 is disposed on a side of the second sense amplifying circuit 123 and the fourth sense amplifying circuit 143 away from the first sense amplifying circuit 113 and the third sense amplifying circuit 133; that is, the sixth equalizing pipe < N6> for precharging the third complementary bit line BLB3 is disposed on the side of the fourth sense amplifying circuit 143 away from the third sense amplifying circuit 133, and the eighth equalizing pipe < N8> is originally disposed on the side of the fourth sense amplifying circuit 143 away from the third sense amplifying circuit 133, that is, the sixth equalizing pipe < N6> is disposed in the region where the eighth equalizing pipe < N8> is located, so as to reduce the layout region required by the layout of the sixth equalizing pipe < N6>, thereby reducing the layout area of the read circuit structure. The seventh equalizer < N7> for precharging the fourth bit line BL4 is disposed on a side of the third sense amplifier circuit 133 away from the fourth sense amplifier circuit 143, and the fifth equalizer < N5> is originally disposed on a side of the third sense amplifier circuit 133 away from the fourth sense amplifier circuit 143, that is, the seventh equalizer < N7> is disposed in a region where the fifth equalizer < N5> is located, so as to reduce a layout region required for layout of the seventh equalizer < N7>, thereby reducing a layout area of the readout circuit structure.

The first complementary bit line BLB1 passes through the region where the second sense amplifier circuit 123 is located, and is coupled to the first sense amplifier circuit 113, and is not electrically connected to the second sense amplifier circuit 123; the second bit line BL2 is coupled to the second sense amplifying circuit 123 through the region where the first sense amplifying circuit 113 is located, and is not electrically connected to the first sense amplifying circuit 113; the third complementary bit line BLB3 is coupled to the third sense amplifying circuit 133 through a region where the fourth sense amplifying circuit 143 is located, and is not electrically connected to the fourth sense amplifying circuit 143; the fourth bit line BL4 is coupled to the fourth sense amplifier circuit 143 across the region where the third sense amplifier circuit 133 is located, and is not electrically connected to the third sense amplifier circuit 133.

The first complementary bit line BLB1 passes through the region where the second sensing amplifying circuit 123 is located to be coupled with the first sensing amplifying circuit 113, that is, the first complementary bit line BLB1 does not need to occupy an extra layout area to complete the wiring, thereby further reducing the layout area of the sensing circuit structure, and the second bit line BL2 passes through the region where the first sensing amplifying circuit 113 is located to be coupled with the second sensing amplifying circuit 123, that is, the second bit line BL2 does not need to occupy an extra layout area to complete the wiring, thereby further reducing the layout area of the sensing circuit structure; the third complementary bit line BLB3 passes through the region where the fourth sense amplifier circuit 143 is located to be coupled to the third sense amplifier circuit 133, that is, the third complementary bit line BLB3 does not need to occupy an extra layout area to complete the wiring, thereby further reducing the layout area of the readout circuit structure, and the fourth bit line BL4 passes through the region where the third sense amplifier circuit 133 is located to be coupled to the fourth sense amplifier circuit 143, that is, the fourth bit line BL4 does not need to occupy an extra layout area to complete the wiring, thereby further reducing the layout area of the readout circuit structure.

Further, in this embodiment, a first equalizing pipe < N1> and a second equalizing pipe < N2> are symmetrically disposed based on the read-write converting circuit 102, a third equalizing pipe < N3> and a fourth equalizing pipe < N4> are symmetrically disposed based on the read-write converting circuit 102, a fifth equalizing pipe < N5> and a sixth equalizing pipe < N6> are symmetrically disposed based on the read-write converting circuit 102, and a seventh equalizing pipe < N7> and an eighth equalizing pipe < N8> are symmetrically disposed based on the read-write converting circuit 102.

For a first equalizing tube < N1>, a second equalizing tube < N2>, a third equalizing tube < N3>, a fourth equalizing tube < N4>, a fifth equalizing tube < N5>, a sixth equalizing tube < N6>, a seventh equalizing tube < N7> and an eighth equalizing tube < N8>:

in one example, the first equalizing pipe < N1> and the fifth equalizing pipe < N5> share the same gate for receiving the first equalizing signal; the third equalizing pipe < N3> and the seventh equalizing pipe < N7> share the same grid and are used for receiving a second equalizing signal; the second equalizing tube < N2> and the sixth equalizing tube < N6> share the same grid and are used for receiving a third equalizing signal; the fourth equalizing pipe < N4> and the eighth equalizing pipe < N8> share the same grid and are used for receiving a fourth equalizing signal;

that is, the first equalization signal is used to precharge the first bit line BL1 connected to the first sense amplifier circuit 113 near the first equalization pipe group and the third bit line BL3 connected to the third sense amplifier circuit 133; the second equalization signal is used for precharging the second bit line BL2 connected to the second sense amplifier circuit 123 close to the second equalization pipe group and the fourth bit line BL4 connected to the fourth sense amplifier circuit 143; the third equalizing signal is used for precharging a second complementary bit line BLB2 connected to the second sense amplifying circuit 123 close to the second equalizing pipe group and a fourth complementary bit line BLB4 connected to the fourth sense amplifying circuit; the first equalization signal is used for precharging a first complementary bit line BLB1 connected to a first sense amplifying circuit 113 close to the first equalization pipe group and a third complementary bit line BLB3 connected to a third sense amplifying circuit;

the first equalizing pipe < N1>, the third equalizing pipe < N3>, the fifth equalizing pipe < N5> and the seventh equalizing pipe < N7> which are arranged in the same equalizing pipe group share a source electrode, so that the distance between an active area of the first equalizing pipe < N1>, an active area of the third equalizing pipe < N3>, an active area of the fifth equalizing pipe < N5> and an active area of the seventh equalizing pipe < N7> is reduced, and the area occupied by the first equalizing pipe group is reduced; the second equalizing pipe < N2>, the fourth equalizing pipe < N4>, the sixth equalizing pipe < N6> and the eighth equalizing pipe < N8> arranged in the same equalizing pipe group share the source electrode, so that the distance between the active area of the second equalizing pipe < N2>, the active area of the fourth equalizing pipe < N4>, the active area of the sixth equalizing pipe < N6> and the active area of the eighth equalizing pipe < N8> is reduced, and the occupied area of the second equalizing pipe group is reduced.

In another example, the first equalization signal and the second equalization signal are the same equalization signal, and the third equalization signal and the fourth equalization signal are the same equalization signal, i.e., the equalization pipes for precharging the bit lines are controlled by the same signal, and the equalization pipes for precharging the complementary bit lines are controlled by the same signal.

Furthermore, the first equalization signal, the second equalization signal, the third equalization signal and the fourth equalization signal are the same equalization signal, that is, the equalization pipes for precharging the first sensing amplification circuit, the second sensing amplification circuit, the third sensing amplification circuit and the fourth sensing amplification circuit are controlled by the same signal.

Referring to fig. 5 and 6, as for the first sense amplifier circuit 113 and the third sense amplifier circuit 133, the first sense amplifier circuit 113 is taken as an example and the first sense amplifier circuit 113 (refer to fig. 2) includes:

and a sense amplifying block connected to the first bit line BL1 through the sense bit line SABL and connected to the first complementary bit line BLB1 through the complementary sense bit line SABLB for sensing a voltage of the memory cell and outputting a logic 1 or 0 corresponding to the voltage.

Specifically, a sense amplifier module includes: the first sensing amplifying N tube < N1400>, the grid electrode is connected with the first bit line BL1, the drain electrode is connected with the complementary reading bit line SABLB, the source electrode is connected with the second signal end NCS, and when the sensing amplifying module is in an amplifying stage, the second signal end NCS is electrically connected with the voltage corresponding to the logic 0; a second sense amplifying N transistor < N1405>, having a gate connected to the first complementary bit line BLB1, a drain connected to the readout bit line SABL, and a source connected to the second signal terminal NCS; the first sensing amplifying P pipe < P1401>, the grid is connected with the reading bit line SABL, the drain is connected with the complementary reading bit line SABLB, the source is connected with the first signal end PCS, when the sensing amplifying module is in the amplifying stage, the first signal end PCS is electrically connected with the voltage corresponding to the logic 1; the second sense amplifier P transistor < P1400>, the gate connected to the complementary sense bitline SABLB, the drain connected to the sense bitline SABL, and the source connected to the first signal terminal PCS.

And an isolation module connected between the complementary sensing bit line SABLB and the first complementary bit line BLB1, and connected between the sensing bit line SABL and the first bit line BL1, for isolating the first bit line BL1, the first complementary bit line BLB1 and signal interaction between the sensing bit line SABL and the complementary sensing bit line SABLB according to an isolation signal ISO.

Specifically, an isolation module includes: a first isolation transistor < N1402>, a gate for receiving an isolation signal ISO, a source connected to the first bit line BL1, a drain connected to the sense bit line SABL, and a second isolation transistor < N1403>, a gate for receiving the isolation signal ISO, a source connected to the first complementary bit line BLB1, and a drain connected to the complementary sense bit line SABLB.

And the offset elimination module is connected between the sensing bit line SABL and the first complementary bit line BLB1, and connected between the complementary sensing bit line SABLB and the first bit line BL1, and is used for adjusting the source-drain conduction difference between the NMOS tubes or the PMOS tubes in the sensing amplification module according to the offset elimination signal OC.

It should be noted that the above-mentioned "source-drain conduction difference" refers to: the first and second sense-amplifying N-tubes < N1400> and < N1405> and the first and second sense-amplifying P-tubes < P1401> and < P1400> may have different threshold voltages from each other due to variations in manufacturing processes, temperature, etc. In this case, the sense amplifying module may cause offset noise due to a difference between threshold voltages of the first and second sense amplifying P-tubes < P1401> and < P1400> and the first and second sense amplifying N-tubes < N1400> and < N1405 >.

Specifically, the offset canceling module includes: a first offset cancellation transistor < N1401>, having a gate for receiving an offset cancellation signal OC, a source connected to the first bit line BL1, and a drain connected to the complementary sensing bit line SABLB; a second offset cancellation transistor < N1404>, a gate for receiving an offset cancellation signal OC, a source connected to the first complementary bit line BLB1, and a drain connected to the sense bit line SABL.

It is understood by those skilled in the art that the structure of the third sense amplifier circuit 133 is the same as that of the first sense amplifier circuit 113, and the above description applies equally after replacing the features of the corresponding structure. Specifically, the corresponding structure includes: the first bit line BL1 corresponds to BL3, the first complementary bit line BLB1 corresponds to BLB3, the first equalizing pipe < N1> corresponds to < N5>, the third equalizing pipe < N3> corresponds to < N7>, the first sense amplifier N pipe < N1400> corresponds to < N1410>, the second sense amplifier N pipe < N1405> corresponds to < N1415>, the first sense amplifier P pipe < P > corresponds to < P1411>, the second sense amplifier P pipe < P1400> corresponds to < P1410>, the first isolation pipe < N1402> corresponds to < N1412>, the second isolation pipe < N1403> corresponds to < N1413>, the first offset canceller pipe < N1401> corresponds to < N1411> and the second offset canceller pipe < N > 1404 corresponds to < N1414>.

Referring to fig. 5 and 6, regarding the second sense amplifying circuit 123 and the fourth sense amplifying circuit 143, the second sense amplifying circuit 123 is taken as an example to be described in detail below, and the second sense amplifying circuit 123 (refer to fig. 2) includes:

and a sense amplifying block connected to the second bit line BL2 through the sense bit line SABL and connected to the second complementary bit line BLB2 through the complementary sense bit line SABLB for sensing a voltage of the memory cell and outputting a logic 1 or 0 corresponding to the voltage.

Specifically, a sense amplifier module includes: a third sense amplifying N transistor < N1425>, the gate is connected to the second bit line BL2, the drain is connected to the complementary read bit line SABLB, the source is connected to the second signal terminal NCS, and when the sense amplifying module is in an amplifying stage, the second signal terminal NCS is electrically connected to a voltage corresponding to logic 0; a fourth sense amplifying N transistor < N1420>, the gate of which is connected to the second complementary bit line BLB2, the drain of which is connected to the readout bit line SABL, and the source of which is connected to the second signal terminal NCS; a third sense amplifying P-transistor < P1421>, a gate is connected to a readout bit line SABL, a drain is connected to a complementary readout bit line SABLB, a source is connected to a first signal terminal PCS, and when the sense amplifying module is in an amplifying stage, the first signal terminal PCS is electrically connected to a voltage corresponding to a logic 1; the fourth sense amplifier P pipe < P1420>, the gate is connected to the complementary sense bitline SABLB, the drain is connected to the sense bitline SABL, and the source is connected to the first signal terminal PCS.

And an isolation module connected between the complementary sensing bit line SABLB and the second complementary bit line BLB2, and connected between the sensing bit line SABL and the second bit line BL2, for isolating the second bit line BL2, the second complementary bit line BLB2 from signal interaction between the sensing bit line SABL and the complementary sensing bit line SABLB according to an isolation signal ISO.

Specifically, an isolation module comprising: a first isolation transistor < N1423>, a gate for receiving the isolation signal ISO, a source connected to the second bit line BL2, a drain connected to the sense bit line SABL, and a second isolation transistor < N1422>, a gate for receiving the isolation signal ISO, a source connected to the second complementary bit line BLB2, and a drain connected to the complementary sense bit line SABLB.

And the offset elimination module is connected between the sensing bit line SABL and the second complementary bit line BLB2, and connected between the complementary sensing bit line SABLB and the second bit line BL2, and is used for adjusting the source-drain conduction difference between the NMOS tubes or the PMOS tubes in the sensing amplification module according to the offset elimination signal OC.

It should be noted that the above-mentioned "source-drain conduction difference" refers to: the third and fourth sense amp Npipe < N1425> and N1420> and the third and fourth sense amp pT < P1421> and P1420> may have different threshold voltages from each other due to variations in manufacturing processes, temperatures, etc. In this case, the sense amplification module may cause offset noise due to a difference between threshold voltages of the third and fourth sense amplification P-tubes < P1421> and P1420> and the third and fourth sense amplification N-tubes < N1445> and N1420 >.

Specifically, the offset canceling module includes: a third offset cancellation transistor < N1424>, having a gate for receiving an offset cancellation signal OC, a source connected to the second bit line BL2, and a drain connected to the complementary sensing bit line SABLB; a fourth offset cancellation transistor < N1421>, having a gate for receiving the offset cancellation signal OC, a source connected to the second complementary bit line BLB2, and a drain connected to the sensing bit line SABL.

It is known to those skilled in the art that the structure of the fourth sense amplifier circuit 143 is the same as that of the second sense amplifier circuit 123, and the above description is also applicable after replacing the features of the corresponding structure. Specifically, the corresponding structure includes: the second bitline BL2 corresponds to BL4, the second complementary bitline BLB2 corresponds to BLB4, the second equalizing pipe < N2> corresponds to < N6>, the fourth equalizing pipe < N4> corresponds to < N8>, the third sense-amp N pipe < N1425> corresponds to < N1435>, the fourth sense-amp N pipe < N1420> corresponds to < N1430>, the third sense-amp P pipe < P1421> corresponds to < P1431>, the fourth sense-amp P pipe < P1420> corresponds to < P >, the third isolation pipe < N1423> corresponds to < N1433>, the fourth isolation pipe < N1422> corresponds to < N1432>, the third offset-cancel pipe < N1424> corresponds to < N1434>, the fourth offset-cancel pipe < N1421> corresponds to < N1431.

Referring to fig. 7, the left side is the layout of the first sense amplifier circuit 113 (refer to fig. 1) and the third sense amplifier circuit 133 (refer to fig. 1), and the right side is the layout of the second sense amplifier circuit 123 (refer to fig. 1) and the fourth sense amplifier circuit 143 (refer to fig. 1).

For fig. 7, the oblique frame region is the layout of the active layer, the white frame region is the layout of the gate layer, and the shadow region is the layout of the contact layer. In the figure, a solid arrow passes through the layout of the contact layer, which shows that the structure represented by the solid arrow is in contact with the contact layer; any areas through which the dashed arrows pass do not touch each other.

For the left-side layout, the following steps are performed from top to bottom in sequence: the device comprises a first balanced tube group layout, a first sensing amplification N tube layout, a first offset isolation layout, a first sensing amplification P tube layout, a second offset isolation layout and a second sensing amplification N tube layout.

As can be seen from the figure, in the present embodiment, the gate structures of the first sense amplifying N transistor < N1400>, the second sense amplifying N transistor < N1405>, the first sense amplifying P transistor < P1401> and the second sense amplifying P transistor < P1400 extend in the same direction, the gate structures of the MOS transistors in the isolation module and the offset canceling module extend in the same direction, and the gate structures of the first sense amplifying N transistor < N1400> and the isolation module extend in the direction perpendicular to each other.

As can be seen, in the present embodiment, the first sense amplifier P pipe < P1401>, the second sense amplifier P pipe < P1400>, the isolation module and the offset cancellation module are disposed between the first sense amplifier N pipe < N1400> and the second sense amplifier N pipe < N1405 >.

Wherein, the layout of the equalizing structure comprises a first equalizing pipe<N1>The third equalizing tube<N3>The fifth equalizing tube<N5>And a seventh equalizing tube<N7>First equalizing pipe<N1>The third equalizing tube<N3>The fifth equalizing tube<N5>And a seventh equalizing pipe<N7>For receiving the same pre-charge voltage V _BLP I.e. the first equalizing tube<N1>Part of active region connected with pre-charging voltage, third equalizing tube<N3>Part of active region connected with pre-charging voltage, fifth equalizing tube<N5>Connection ofPartial active area of pre-charging voltage and seventh equalizing tube<N7>The active regions connected to the precharge voltage are partially connected.

The first equalizing pipe < N1> and the fifth equalizing pipe < N5> are used for receiving a first equalizing signal and pre-charging a first bit line BL1 connected with a first sensing amplifying circuit and a third bit line BL3 connected with a third sensing amplifying circuit, which are close to the layout of the first equalizing pipe group, based on the first equalizing signal; the third equalizing pipe < N3> and the seventh equalizing pipe < N7> are used for receiving the second equalizing signal and precharging a third bit line BL2 connected with the second sensing amplifying circuit and a fourth bit line BL4 connected with the fourth sensing amplifying circuit, which are close to the layout of the second equalizing pipe group, based on the second equalizing signal.

For the first offset isolation layout and the second offset isolation layout, the source of the first isolation pipe < N1402> and the source of the first offset cancellation pipe < N1401> are communicated and connected with the first bit line BL1; the source of the second isolation transistor < N1403> and the source of the second offset cancellation transistor < N1404> are connected and connected to the first complementary bit line BLB1.

For the right layout, the following steps are performed from top to bottom: the device comprises a first sensing amplification N pipe layout, a first deviation isolation layout, a first sensing amplification P pipe layout, a first deviation isolation layout, a first sensing amplification N pipe layout and a first balance structure layout.

As can be seen from the figure, in the present embodiment, the gate structures of the third sense amplifying N-transistor < N1425>, the fourth sense amplifying N-transistor < N1420>, the third sense amplifying P-transistor < P1421> and the fourth sense amplifying P-transistor < P1420> have the same extending direction, the gate structures of the MOS transistors in the isolation module and the offset canceling module have the same extending direction, and the gate structures of the third sense amplifying N-transistor < N1425> and the MOS transistors in the isolation module have the perpendicular extending direction.

As can be seen, in the present embodiment, the third sense amplifier P-pipe < P1421>, the fourth sense amplifier P-pipe < P1420>, the isolation module and the offset cancellation module are disposed between the third sense amplifier N-pipe < N1425> and the fourth sense amplifier N-pipe < N1420 >.

Wherein the layout of the equalizing structure comprises a second equalizing pipe<N2>Fourth equalizing tube<N4>Sixth equalizing tube<N6>And an eighth equalizing tube<N8>Second equalizing tube<N2>The fourth equalizing tube<N4>Sixth equalizing tube<N6>And an eighth equalizing pipe<N8>For receiving the same precharge voltage V _BLP I.e. second equalizing pipe<N2>Partial active region connected with pre-charging voltage, fourth equalizing tube<N4>Part of active region connected with pre-charging voltage, sixth equalizing tube<N6>A part of the active region connected with the pre-charge voltage and an eighth equalizing tube<N8>The active regions connected to the precharge voltage are partially connected.

The second equalizing pipe < N2> and the sixth equalizing pipe < N6> are used for receiving a third equalizing signal and pre-charging a second complementary bit line BLB2 connected with a second sensing amplifying circuit and a fourth complementary bit line BLB4 connected with a fourth sensing amplifying circuit, which are close to the layout of the second equalizing pipe group, based on the third equalizing signal; the fourth equalizing pipe < N4> and the eighth equalizing pipe < N8> are used for receiving the fourth equalizing signal and precharging the first complementary bit line BLB1 connected to the first sense amplifying circuit and the third complementary bit line BLB3 connected to the third sense amplifying circuit which are close to the layout of the first equalizing pipe group based on the fourth equalizing signal.

For the third offset isolation layout and the fourth offset isolation layout, the source of the third isolation pipe < N1423> is communicated with the source of the third offset cancellation pipe < N1424>, and is connected with the second bit line BL2; the source of the fourth isolation pipe < N1422> is connected to the source of the fourth offset cancellation pipe < N1421>, and the second complementary bit line BLB2 is connected.

Compared with the prior art, the drain electrode of the first equalizing pipe is directly connected with the first bit line and used for directly precharging the first bit line, the drain electrode of the third equalizing pipe is directly connected with the second bit line and used for directly precharging the second bit line, the drain electrode of the fifth equalizing pipe is directly connected with the third bit line and used for directly precharging the third bit line, and the drain electrode of the seventh equalizing pipe is directly connected with the fourth bit line and used for directly precharging the fourth bit line, namely, the drain electrode of the equalizing pipe is directly connected with the bit line and directly charges the bit line, so that the situation that the bit line can be precharged only by switching on the switching transistor in the precharging process is avoided, and the charging speed of the bit line is accelerated; the source electrode of the first equalizing tube, the source electrode of the third equalizing tube, the source electrode of the fifth equalizing tube and the active region where the source electrode of the seventh equalizing tube is located are connected, namely the source electrode of the first equalizing tube, the source electrode of the third equalizing tube, the source electrode of the fifth equalizing tube and the source electrode of the seventh equalizing tube adopt the same source electrode, so that the layout area of the first equalizing tube group is reduced, and the layout area of the reading circuit structure is reduced; furthermore, the first equalizing tube is connected with the grid electrode of the fifth equalizing tube and used for receiving the first equalizing signal, and the third equalizing tube is connected with the grid electrode of the third equalizing tube and used for receiving the second equalizing signal, so that the pre-charging of different bit lines is controlled based on different control signals.

The drain electrode of the second equalizing pipe is directly connected with the first complementary bit line and used for directly precharging the first complementary bit line, the drain electrode of the fourth equalizing pipe is directly connected with the second complementary bit line and used for directly precharging the second complementary bit line, the drain electrode of the sixth equalizing pipe is directly connected with the third complementary bit line and used for directly precharging the third complementary bit line, and the drain electrode of the eighth equalizing pipe is directly connected with the fourth complementary bit line and used for directly precharging the fourth complementary bit line, namely, the equalizing pipe is directly connected with the complementary bit lines and directly charges the complementary bit lines, so that the condition that the complementary bit lines can be precharged only by switching on a switching transistor in the precharging process is avoided, and the charging speed of the complementary bit lines is accelerated; the source electrode of the second equalizing tube, the source electrode of the fourth equalizing tube, the source electrode of the sixth equalizing tube and the source electrode of the eighth equalizing tube are connected in the active region, namely the source electrode of the second equalizing tube, the source electrode of the fourth equalizing tube, the source electrode of the sixth equalizing tube and the source electrode of the eighth equalizing tube adopt the same source electrode, so that the layout area of the second equalizing tube group is reduced, and the layout area of the reading circuit structure is reduced; furthermore, the gates of the second equalizing tube and the sixth equalizing tube are connected and used for receiving the third equalizing signal, and the gates of the fourth equalizing tube and the eighth equalizing tube are connected and used for receiving the fourth equalizing signal, so that the pre-charging of different complementary bit lines is controlled based on different control signals.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the present application, and that various changes in form and details may be made therein without departing from the spirit and scope of the present application in practice.

Claims

1. A sensing circuit structure disposed in a gap between adjacent memory arrays, comprising:

the first equalizing pipe group comprises a first equalizing pipe, a third equalizing pipe, a fifth equalizing pipe and a seventh equalizing pipe;

the source electrode of the first equalizing tube, the source electrode of the third equalizing tube, the source electrode of the fifth equalizing tube and the active region where the source electrode of the seventh equalizing tube is located are connected, the drain electrode of the first equalizing tube is directly connected to a first bit line, the drain electrode of the third equalizing tube is directly connected to a second bit line, the drain electrode of the fifth equalizing tube is directly connected to a third bit line, and the drain electrode of the seventh equalizing tube is directly connected to a fourth bit line;

the first bit line, the second bit line, the third bit line and the fourth bit line are four adjacent bit lines in the same memory array;

the gate of the first equalizing tube is connected with the gate of the fifth equalizing tube, and the first equalizing tube is used for receiving a first equalizing signal and precharging the first bit line and the third bit line to a preset voltage based on the first equalizing signal; the gate of the third equalizing tube is connected with the gate of the seventh equalizing tube, and is used for receiving a second equalizing signal and precharging the second bit line and the fourth bit line to a preset voltage based on the second equalizing signal.

2. The sensing circuit structure of claim 1, further comprising:

the second equalizing pipe group corresponds to the first equalizing pipe group and comprises a second equalizing pipe, a fourth equalizing pipe, a sixth equalizing pipe and an eighth equalizing pipe;

the source electrode of the second equalizing tube, the source electrode of the fourth equalizing tube, the source electrode of the sixth equalizing tube and the active region where the source electrode of the eighth equalizing tube are located are connected, the drain electrode of the second equalizing tube is directly connected to a first complementary bit line, the drain electrode of the fourth equalizing tube is directly connected to a second complementary bit line, the drain electrode of the sixth equalizing tube is directly connected to a third complementary bit line, and the drain electrode of the eighth equalizing tube is directly connected to a fourth complementary bit line;

the first complementary bit line, the second complementary bit line, the third complementary bit line and the fourth complementary bit line are four adjacent complementary bit lines in the same memory array;

the gate of the second equalizing pipe is connected with the gate of the sixth equalizing pipe, and is used for receiving a third equalizing signal and precharging the first complementary bit line and the third complementary bit line to a precharge voltage based on the third equalizing signal, and the gate of the fourth equalizing pipe is connected with the gate of the eighth equalizing pipe, and is used for receiving a fourth equalizing signal and precharging the second complementary bit line and the fourth complementary bit line to a precharge voltage based on the fourth equalizing signal.

3. A sensing circuit structure of claim 2, further comprising:

a first sense amplifier circuit and a second sense amplifier circuit, which are adjacently disposed along a bit line extending direction, for sensing a voltage of the memory cell and outputting a logic 1 or 0 corresponding to the voltage, wherein the first sense amplifier circuit couples one of the adjacent memory arrays through the first bit line and couples the other of the adjacent memory arrays through the first complementary bit line, and the second sense amplifier circuit couples one of the adjacent memory arrays through the second bit line and couples the other of the adjacent memory arrays through the second complementary bit line;

and the third sense amplifying circuit and the fourth sense amplifying circuit are adjacently arranged along the extension direction of the bit line, the third sense amplifying circuit and the first sense amplifying circuit are adjacently arranged in the word line direction, the fourth sense amplifying circuit and the second sense amplifying circuit are adjacently arranged in the word line direction, the third sense amplifying circuit is coupled with one memory array in the adjacent memory arrays through the third bit line, the third complementary bit line is coupled with the other memory array in the adjacent memory arrays, the fourth sense amplifying circuit is coupled with one memory array in the adjacent memory arrays through the fourth bit line, and the fourth complementary bit line is coupled with the other memory array in the adjacent memory arrays.

4. A sensing circuit structure of claim 3, comprising:

the first complementary bit line passes through the area where the second sensing amplification circuit is located and is coupled with the first sensing amplification circuit and is not electrically connected with the second sensing amplification circuit; the second bit line passes through the area where the first sensing amplifying circuit is located and is coupled with the second sensing amplifying circuit, and is not electrically connected with the first sensing amplifying circuit;

the third complementary bit line passes through the area where the fourth sensing amplifying circuit is located and is coupled with the third sensing amplifying circuit and is not electrically connected with the fourth sensing amplifying circuit; the fourth bit line is coupled with the fourth sensing amplifying circuit through the region where the third sensing amplifying circuit is located, and is not electrically connected with the third sensing amplifying circuit.

5. A sensing circuit structure of claim 3, comprising: the first equalizing pipe group is arranged on one side, away from the second sensing amplifying circuit and the fourth sensing amplifying circuit, of the first sensing amplifying circuit and the third sensing amplifying circuit; the second equalizing pipe group is arranged on one side of the second sensing amplifying circuit and the fourth sensing amplifying circuit far away from the first sensing amplifying circuit and the third sensing amplifying circuit.

6. The sensing circuit structure of claim 5, further comprising:

the read-write conversion circuit is used for writing external data into the storage units of the storage array or reading the data in the storage units;

the first equalizing pipe group and the second equalizing pipe group are symmetrically arranged based on the read-write conversion circuit.

7. A sensing circuit arrangement according to claim 1, wherein the first equalized signal and the second equalized signal are the same equalized signal.

8. A sensing circuit arrangement according to claim 2, wherein the third equalized signal and the fourth equalized signal are the same equalized signal.

9. A readout circuit structure according to claim 3, wherein the first sense amplifying circuit includes:

a sense amplifying module connected to the first bit line through a sense bit line and the first complementary bit line through a complementary sense bit line, for sensing a voltage of the memory cell and outputting a logic 1 or 0 corresponding to the voltage;

the isolation module is connected between the complementary sensing bit line and the first complementary bit line, is connected between the sensing bit line and the first bit line, and is used for isolating signal interaction between the first bit line and the first complementary bit line and between the sensing bit line and the complementary sensing bit line according to an isolation signal;

and the offset elimination module is connected between the read bit line and the first complementary bit line, is connected between the complementary read bit line and the first bit line, and is used for adjusting the source-drain conduction difference between NMOS tubes or PMOS tubes in the sensing amplification module according to an offset elimination signal.

10. The readout circuit structure of claim 9, wherein the sense amplification module comprises:

a gate of the first sense amplifying N transistor is connected with the first bit line, a drain of the first sense amplifying N transistor is connected with the complementary read bit line, and a source of the first sense amplifying N transistor is connected with a second signal end;

a grid electrode of the second sensing amplification N tube is connected with the first complementary bit line, a drain electrode of the second sensing amplification N tube is connected with the read bit line, and a source electrode of the second sensing amplification N tube is connected with the second signal end;

a gate of the first sense amplifying P transistor is connected with the read bit line, a drain of the first sense amplifying P transistor is connected with the complementary read bit line, a source of the first sense amplifying P transistor is connected with a first signal end, and when the sense amplifying module is in an amplifying stage, the first signal end is electrically connected with a voltage corresponding to a logic 1;

and the grid electrode of the second sensing amplification P tube is connected with the complementary read bit line, the drain electrode of the second sensing amplification P tube is connected with the read bit line, and the source electrode of the second sensing amplification P tube is connected with the first signal end.

11. The readout circuit structure of claim 10, wherein the gate structures of the first sense amplifying N-transistor, the second sense amplifying N-transistor, the first sense amplifying P-transistor and the second sense amplifying P-transistor extend in the same direction, the gate structures of the MOS transistors in the isolation module and the offset cancellation module extend in the same direction, and the gate structures of the first sense amplifying N-transistor and the MOS transistors in the isolation module extend in the direction perpendicular to each other.

12. The readout circuit structure of claim 10, wherein the first sense amplifier P-transistor, the second sense amplifier P-transistor, the isolation module, and the offset cancellation module are disposed between the first sense amplifier N-transistor and the second sense amplifier N-transistor.

13. The sensing circuit structure of claim 9, wherein the isolation module comprises:

the grid electrode of the first isolation tube is used for receiving the isolation signal, the source electrode of the first isolation tube is connected with the first bit line, and the drain electrode of the first isolation tube is connected with the read bit line;

and the grid of the second isolation tube is used for receiving the isolation signal, the source of the second isolation tube is connected with the first complementary bit line, and the drain of the second isolation tube is connected with the complementary reading bit line.

14. The sensing circuit structure of claim 13, wherein the offset cancellation block comprises:

a first offset cancellation tube, wherein a grid electrode is used for receiving the offset cancellation signal, a source electrode is connected with the first bit line, and a drain electrode is connected with the complementary reading bit line;

and the grid of the second offset elimination tube is used for receiving the offset elimination signal, the source of the second offset elimination tube is connected with the first complementary bit line, and the drain of the second offset elimination tube is connected with the read bit line.

15. The sensing circuit structure of claim 14, wherein the source of the first isolation pipe and the source of the first offset cancellation pipe are in communication and connected to the first bit line; and the source electrode of the second isolation tube is connected with the source electrode of the second offset elimination tube and is connected with the first complementary bit line.