CN102820055A - Data readout circuit for phase change memorizer - Google Patents
Data readout circuit for phase change memorizer Download PDFInfo
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- CN102820055A CN102820055A CN2011101517384A CN201110151738A CN102820055A CN 102820055 A CN102820055 A CN 102820055A CN 2011101517384 A CN2011101517384 A CN 2011101517384A CN 201110151738 A CN201110151738 A CN 201110151738A CN 102820055 A CN102820055 A CN 102820055A
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Abstract
The invention relates to a voltage-reading/current-reading switchable data readout circuit for a phase change memorizer. The data readout circuit comprises a clamping voltage generating circuit, a pre-charge circuit, a clamping circuit which has a first working mode for generating a clamping current and a second working mode for generating a pre-amplifier voltage, a reading mode switching circuit which selects a current-reading mode or a voltage-reading mode under the control of reading mode selection signals; a current/voltage switching circuit which calculates a clamping current and a reference current under the current-reading mode, transforms into two complementary voltages; and a comparative amplifying circuit which compares the selected two voltages and outputs readout results, wherein, in the current-reading mode, the two voltages are the two voltages formed by transformation of the current/voltage switching circuit; and in the voltage-reading mode, the two voltages are the pre-amplifier voltage and the reference voltage under the voltage-reading mode. Compared with a conventional data readout circuit, the data readout circuit provided by the invention realizes the switch of the voltage-reading/current-reading, and can select matching reading modes to different loading conditions.
Description
Technical field
The present invention relates to phase transition storage, relate in particular to the data reading circuit of reading the switchable phase transition storage of voltage/read current.
Background technology
Phase transition storage (PC-RAM) is a kind of novel resistance variant nonvolatile semiconductor memory; It is compared with present existing multiple semiconductor memory technologies; Have low-power consumption, non-volatile, high density, anti-irradiation, non-volatile, read, have extended cycle life (＞10 at a high speed
13Inferior), device size contractibility (nanoscale); The simple advantages such as (ability and prior integrated circuit process are complementary) of high-low temperature resistant (55 ℃ to 125 ℃), anti-vibration, anti-electronic interferences and manufacturing process; Be at present by the strongest rival in the extensively good storer of future generation of industry member, have vast market prospect.
Phase transition storage is a storage medium with the chalcogenide compound material; The Joule heat that utilizes electric pulse or light pulse to produce makes phase-change storage material between amorphous state (material is high-impedance state) and crystalline state (material is low resistive state), reversible transition take place and realizes writing and wiping of data, and reading then of data realizes through the state of measuring resistance.
The data of storing in the phase transition storage (being the crystalline state or the amorphous state of phase change cells) will read through data reading circuit; Consider that its characteristic directly perceived that shows is low resistance state or high-impedance state; Therefore; Phase transition storage all is through under the control of reading enable signal and data reading circuit, imports the electric current or the voltage of less value to the phase-change memory cell of phase transition storage, measures then that magnitude of voltage or current value on the phase-change memory cell realize.
Generally, data reading circuit is given phase-change memory cell through sending a small current value (magnitude of voltage), this moment reading bit line voltage (electric current), if bit-line voltage higher (electric current is less) then represent that phase change cells is a high-impedance state, i.e. " 1 "; If bit-line voltage lower (electric current is bigger) then represent that phase change cells is a low resistance state, i.e. " 0 ".Yet in the process of reading, when electric current flow through phase-change memory cell, phase-change memory cell can produce Joule heat, if the power of Joule heat during greater than the radiating efficiency of phase-change memory cell, this thermal effect can influence the basic status of phase-change memory cell; Simultaneously, when the voltage difference at phase-change memory cell two ends surpassed some threshold values, punch-through effect can take place in the inner charge carrier of phase-change material, and charge carrier increases suddenly, shows the characteristic of low-resistance, but the material of this moment itself does not undergo phase transition.Above-mentioned two phenomenons are the so-called bad phenomenon of reading a character with two or more ways of pronunciation.
For fear of the above-mentioned bad phenomenon of reading a character with two or more ways of pronunciation occurring, data reading circuit need satisfy following requirement: read current (voltage) must be very little, so that produce the radiating efficiency that the power of Joule heat is no more than phase-change memory cell; When in the scope of allowing, selecting suitably big read current (voltage); Must guarantee that reading speed is very fast; So that make the Joule heat of generation also have little time to make the basic status of unit to change; And the maximal value of read current (voltage) must be less than the inside charge carrier breakdown threshold of phase change cells, to prevent the inner charge carrier generation of phase-change material punch-through effect.
For the phase transition storage under the ideal situation, it is attainable more than requiring.Yet, in the phase transition storage of reality,, make the action need long time of read current (voltage) because the existence of stray capacitance on the bit line can cause when satisfying above-mentioned requirements.Because data reading circuit need be waited for read current (voltage) and charge the state of reading phase-change memory cell that electricity later on could be correct to bit line capacitance, so just greatly restrict the velocity characteristic of phase transition storage.
In general; The phase transition storage sensing circuit can be divided into the read current pattern and read voltage mode; Wherein, The phase transition storage sensing circuit of read current pattern has read-out speed faster with respect to the phase transition storage sensing circuit of reading voltage mode, and the phase transition storage sensing circuit of reading voltage mode has lower power consumption with respect to the phase transition storage sensing circuit of read current pattern.Simultaneously; Read-out speed and power consumption all receive the size and the interval restriction of the high low resistance state resistance of phase-change memory cell of load parasitic capacitance; And the high low resistance state resistance of the load parasitic capacitance of sensing circuit and phase-change memory cell links together with manufacture craft, and these uncertain parameters have constituted serious challenge to high-performance sensing circuit how to design a high-speed low-power-consumption.
Therefore, how to improve problems such as the high low resistance state resistance of above-mentioned load parasitic capacitance and storage unit interval is lower to sense data oversize, high low resistance state resolution consuming time, power consumption is big, become the technical task that those skilled in the art need to be resolved hurrily in fact.
Summary of the invention
The object of the present invention is to provide a kind of data reading circuit of reading the switchable phase transition storage of voltage/read current, be used to solve the problem that data read-out speed and power consumption in the prior art can not get both.
For solving above-mentioned and other problems; The present invention provides a kind of data reading circuit of reading the switchable phase transition storage of voltage/read current; Said phase transition storage comprises one or more phase-change memory cells, and each phase-change memory cell links to each other with control circuit with word line through bit line; Said data are read packet and drawn together: paper tinsel position voltage generation circuit is used to produce paper tinsel position voltage; Pre-charge circuit, the bit line to said storage unit under the control of said paper tinsel position voltage carries out rapid charge; Paper tinsel position circuit by the control of paper tinsel position voltage, has and carries out the paper tinsel position in pairs of bit line under the read current pattern and produce first mode of operation of paper tinsel digit current and reading that pairs of bit line signal under the voltage mode amplifies in advance and second mode of operation that produces preparatory amplifying voltage; The reading mode commutation circuit; Select to select the read current pattern under the signal controlling or read voltage mode at reading mode; Control paper tinsel position circuit is carried out first mode of operation or corresponding second mode of operation of reading voltage mode of corresponding read current pattern, and selection needs two-way voltage relatively; Current-to-voltage converting circuit is selected in said reading mode commutation circuit under the situation of read current pattern, and paper tinsel digit current that produces and the reference current under the read current pattern are carried out computing and then converted complementary two-way voltage into; Compare amplifying circuit; The two-way voltage that said reading mode commutation circuit is selected compares; The result is read in output: under the read current pattern, the two-way voltage that said reading mode commutation circuit is selected comprises the two-way voltage of the complementation that said current-to-voltage converting circuit conversion back forms; Reading under the voltage mode, the two-way voltage that said reading mode commutation circuit is selected comprises the preparatory amplifying voltage that paper tinsel position circuit pairs of bit line signal amplifies in advance and reads the reference voltage under the voltage mode.
Alternatively, said data reading circuit also is included in the bit line transmission gate that is connected in series on the said bit line, makes said pre-charge circuit and said paper tinsel digit current produce circuit and is connected with said bit line via said bit line transmission gate.
Alternatively, said data reading circuit also comprises discharge circuit, is used for comparing on the said bit line of releasing after amplifieroperation is compared in the amplifying circuit completion and the remaining electric charge of said data reading circuit load end said.
Alternatively, said discharge circuit comprises that controlled nMOS pipe that is connected between said pre-charge circuit and the ground wire and controlled the 2nd nMOS that is connected between said bit line and the ground wire manage.
Alternatively, said data reading circuit also comprises the bit line bias current circuit, is used for bias current to bit line being provided.
Alternatively, said bit line bias current circuit comprises the current-mirror structure that is formed by two pMOS pipes, and wherein, the drain electrode of pMOS pipe is connected with bias current sources, and the drain electrode of the 2nd pMOS pipe is connected with said paper tinsel position circuit.
Alternatively, said bit line bias current circuit is in respectively that its bias current sources has different electric currents when reading voltage mode with the read current pattern.
Alternatively; Said paper tinsel position voltage generation circuit comprises current source, connects into the nMOS pipe of diode and the 2nd nMOS pipe that is connected in series with nMOS pipe; The drain electrode of the one nMOS pipe is connected with the current output terminal of said current source; The grid of the one nMOS pipe is connected with the grid of the 2nd nMOS pipe, and the source electrode of nMOS pipe is connected with the drain electrode of the 2nd nMOS pipe, the source ground of the 2nd nMOS pipe.
Alternatively, said pre-charge circuit comprises the precharge switch pipe and the precharge paper tinsel position nMOS that connects with said precharge switch pipe pipe.
Alternatively, said paper tinsel position circuit comprises paper tinsel position nMOS pipe.
Alternatively, said reading mode commutation circuit comprises: the current-to-voltage converting circuit CS; Amplifying circuit input signal SS relatively comprises being used for connecting respectively first voltage and the comparison amplifier positive input terminal that are produced by current-to-voltage converting circuit under the read current pattern, reading under preparatory amplifying voltage and comparison amplifier positive input terminal under the voltage mode, the read current pattern by second voltage and the comparison amplifier negative input end of current-to-voltage converting circuit generation, reading four transmission gates of reference voltage and comparison amplifier negative input end under the voltage mode; And be used for reading mode selection signal is carried out anti-phase and obtains the phase inverter that reading mode is selected the signal designature.
Alternatively, reading mode is selected signal and is selected the signal designature to be carried in the control end and the current-to-voltage converting circuit CS control end of four transmission gates respectively through the reading mode of phase inverter; When selecting signal to be " 1 ", the current-to-voltage converting circuit CS cuts out, and is connected the transmission gate of preparatory amplifying voltage and comparison amplifier positive input terminal and is connected the transmission gate conducting of reading voltage mode reference voltage and comparison amplifier negative input end; Otherwise; When selecting signal to be " 0 "; The current-to-voltage converting circuit CS is opened, and is connected under the read current pattern transmission gate of first voltage that produced by current-to-voltage converting circuit and comparison amplifier positive input terminal and is connected under the read current pattern by second voltage of current-to-voltage converting circuit generation and the transmission gate conducting of comparison amplifier negative input end.
Alternatively, said relatively amplifying circuit comprises voltage comparator.
The data reading circuit of reading the switchable phase transition storage of voltage/read current provided by the invention; Can select under the control of signal in the read current pattern and read to select between the voltage mode at reading mode; Thereby the reading mode that can be complementary with it to different loading condition selections, the optimum efficiency of realization read-out speed, high low resistance state resolution, power consumption.
In addition, the data reading circuit of phase transition storage provided by the invention also comprises discharge circuit, and the remaining electric charge of can effectively releasing reduces even stops data-crosstalk, improves the reliability that data reading speed and data are read.
Description of drawings
Fig. 1 is the data reading circuit load array structure synoptic diagram of phase transition storage;
Fig. 2 is an electrical block diagram of reading the data reading circuit of the switchable phase transition storage of voltage/read current of the present invention;
Fig. 3 is the electrical block diagram of data reading circuit in a specific embodiment of reading the switchable phase transition storage of voltage/read current of the present invention.
Embodiment
Inventor of the present invention finds: what the data reading circuit of traditional phase transition storage adopted is that single reading mode (is the read current pattern; Be to read voltage mode); A little less than existing adaptability; Can not be according to the reading mode of loading condition selection with its coupling, data reading speed and power consumption can not get both, be difficult to obtain the optimum performance effect.
Therefore; For preventing above-mentioned generation of defects; Inventor of the present invention improves prior art, has proposed a kind of switchable data reading circuit of voltage/read current of reading, and possesses the read current pattern simultaneously and reads voltage mode; And can select with the read current pattern of its coupling or read voltage mode, thereby realize the optimum efficiency of read-out speed, high low resistance state resolution, power consumption according to different loading condition.
Below will come the data reading circuit of phase transition storage of invention is elaborated through specific embodiment.
Below in conjunction with the more complete description the present invention of diagram, preferred embodiment provided by the invention, but should not be considered to only limit in the embodiment of this elaboration.Reference diagram is a synoptic diagram of the present invention, and the expression among the figure is an illustrative nature, should not be considered to limit scope of the present invention.
Fig. 1 is the structural representation of load array of the data reading circuit of phase transition storage.As shown in Figure 1, the load end of a data sensing circuit will be connected respectively on a plurality of (for example being p) bit line through a plurality of bit line transmission gates, be parallel with a plurality of (for example being q) phase-change memory cell simultaneously on each bit line.In addition, be connected with stray capacitance Cp_, be connected with stray capacitance Cp at the load end of each bit line transmission gate at the load end of data reading circuit.
Fig. 2 is an electrical block diagram of reading the data reading circuit of the switchable phase transition storage of voltage/read current of the present invention.Show like Fig. 2; Storage unit in the phase transition storage has bit line and word line, and the said switchable data reading circuit of voltage of reading comprises: bit line transmission gate, paper tinsel position voltage generation circuit, pre-charge circuit, paper tinsel position circuit, bit line bias current circuit, reading mode commutation circuit, current-to-voltage converting circuit, comparison amplifying circuit and discharge circuit.
Data reading circuit is connected with the bit line BL of storage unit through the bit line transmission gate;
Paper tinsel position voltage generation circuit is used to produce paper tinsel position voltage.In the present invention, said paper tinsel position voltage generation circuit comprises: bias current sources I
Bias, connect into the nMOS pipe M11 of diode and the nMOS that be connected in series with nMOS pipe M11 manages M12.
Pre-charge circuit is used for the bit line of said storage unit is carried out rapid charge.In the present invention, said pre-charge circuit comprises precharge switch pipe M3 and the precharge paper tinsel position nMOS that connects with precharge switch pipe M3 pipe M2b.
Paper tinsel position circuit has and carries out the paper tinsel position in pairs of bit line under the read current pattern and produce first mode of operation of paper tinsel digit current and reading that pairs of bit line signal under the voltage mode amplifies in advance and second mode of operation that produces preparatory amplifying voltage.In the present invention, said paper tinsel position circuit comprises paper tinsel position nMOS pipe M2a.
The bit line bias current circuit is used for bias current to bit line being provided.In the present invention, said bit line bias current circuit comprises the current-mirror structure that is formed by two pMOS pipe M4, M5a.
The reading mode commutation circuit; Select to select the read current pattern under the signal controlling or read voltage mode at reading mode; Control paper tinsel position circuit is carried out first mode of operation or corresponding second mode of operation of reading voltage mode of corresponding read current pattern, and selection needs two-way voltage relatively.In the present invention, the reading mode commutation circuit is made up of nMOS pipe M7 and comparison amplifier input selection circuit (CMP input selector), and receives reading mode to select signal controlling.
Current-to-voltage converting circuit is selected in said reading mode commutation circuit under the situation of read current pattern, and the paper tinsel digit current that will under the read current pattern, produce converts voltage into.
Amplifying circuit relatively will be read the result thereby export being compared by the voltage of current/voltage conversion under the read current pattern or will under the voltage mode preparatory amplifying voltage and reference voltage being compared reading.In the present invention, relatively amplifying circuit is a voltage comparator.
Data reading circuit of the present invention also comprises discharge circuit, is used for comparing on the said bit line of releasing after amplifieroperation is compared in the amplifying circuit completion and the remaining electric charge of said data reading circuit load end said.In the present invention, discharge circuit comprise the controlled nMOS pipe M1a that is connected between pre-charge circuit and the ground wire and be connected bit line and ground wire between controlled nMOS pipe M1b.
Fig. 3 is the electrical block diagram of data reading circuit in a specific embodiment of reading the switchable phase transition storage of voltage/read current of the present invention.As shown in Figure 3, said data reading circuit comprises: bit line transmission gate, paper tinsel position voltage generation circuit, pre-charge circuit, paper tinsel position circuit, bit line bias current circuit, reading mode commutation circuit, current-to-voltage converting circuit, comparison amplifying circuit and discharge circuit.
Data reading circuit is connected with the bit line BL of storage unit through the bit line transmission gate;
Paper tinsel position voltage generation circuit is used to produce paper tinsel position voltage.In the present embodiment, said paper tinsel position voltage generation circuit comprises: bias current sources I
Bias, connect into the nMOS pipe M11 of diode and the nMOS pipe M12 that be connected in series with nMOS pipe M11, nMOS manages drain electrode and the bias current sources I of M11
BiasCurrent output terminal connect, the grid of nMOS pipe M11 is connected with the grid of the drain electrode of nMOS pipe M11, nMOS pipe M12, the source electrode of nMOS pipe M11 is connected with the drain electrode that nMOS manages M12, nMOS manages the source ground of M12.
Pre-charge circuit, the bit line to said storage unit under the control of said paper tinsel position voltage carries out rapid charge.In the present embodiment, said pre-charge circuit comprises precharge switch pipe M3 and the precharge paper tinsel position nMOS that connects with precharge switch pipe M3 pipe M2b.Precharge switch pipe M3 is actual to be a pMOS pipe; The grid of pMOS pipe M3 connects the precharge enable signal; The source electrode of pMOS pipe M3 meets voltage source V dd; The drain electrode of pMOS pipe M3 is connected with the drain electrode of precharge paper tinsel position nMOS pipe M2b, and the grid of precharge paper tinsel position nMOS pipe M2b is connected (receiving paper tinsel position voltage) with the grid of the grid of nMOS pipe M11, nMOS pipe M12, and the source electrode of precharge paper tinsel position nMOS pipe M2b is connected with the bit line transmission gate.
Paper tinsel position circuit by the control of paper tinsel position voltage, has and carries out the paper tinsel position in pairs of bit line under the read current pattern and produce first mode of operation of paper tinsel digit current and reading that pairs of bit line signal under the voltage mode amplifies in advance and second mode of operation that produces preparatory amplifying voltage.In the present embodiment; Said paper tinsel position circuit comprises paper tinsel position nMOS pipe M2a; Wherein, The grid of paper tinsel position nMOS pipe M2a is connected (receiving paper tinsel position voltage) with the grid of the grid of nMOS pipe M11, nMOS pipe M12, and the source electrode of paper tinsel position nMOS pipe M2a is connected with source electrode, the bit line transmission gate of precharge paper tinsel position nMOS pipe M2b, the drain electrode output paper tinsel digit current I of paper tinsel position nMOS pipe M2a
Cell
The bit line bias current circuit is used for bias current to bit line being provided.In the present embodiment, said bit line bias current circuit comprises the current-mirror structure that is formed by two pMOS pipe M4, M5a, wherein; The grid of pMOS pipe M4 is connected with the grid of pMOS pipe M5a; And the grid of pMOS pipe M4 is connected with the drain electrode of pMOS pipe M4, and the source electrode of pMOS pipe M4 meets supply voltage Vdd, and the drain electrode of pMOS pipe M4 is connected with bias current sources; The source electrode of pMOS pipe M5a meets supply voltage Vdd, and the drain electrode of pMOS pipe M5a is connected with the drain electrode of paper tinsel position nMOS pipe M2a in the circuit of said paper tinsel position.
The reading mode commutation circuit; Select to select the read current pattern under the signal controlling or read voltage mode at reading mode; Control paper tinsel position circuit is carried out first mode of operation or corresponding second mode of operation of reading voltage mode of corresponding read current pattern, and selection needs two-way voltage relatively.In the present embodiment, said reading mode commutation circuit comprises: the current-to-voltage converting circuit CS comprises the comparison amplifying circuit input signal SS of four transmission gate TG0, TG1, TG2, TG3 and phase inverter INV0.
Particularly; Said current-to-voltage converting circuit CS is to be made up of reading mode SS pipe (pMOS pipe M9a, M9b); Wherein, The grid of pMOS pipe M9a is connected with the grid of pMOS pipe M9b, and the source electrode of pMOS pipe M9a is connected (grid of pMOS pipe M5b is connected with the drain electrode of pMOS pipe M5b, and the source electrode of pMOS pipe M5b meets supply voltage Vdd) with the drain electrode of pMOS pipe M5b; The drain electrode of pMOS pipe M9a is connected with the drain electrode of paper tinsel position nMOS pipe M2a in the circuit of said paper tinsel position; The source electrode of pMOS pipe M9b is connected (grid of pMOS pipe M8 is connected with the drain electrode of pMOS pipe M8, and the source electrode of pMOS pipe M8 meets supply voltage Vdd) with the drain electrode of pMOS pipe M8, the drain electrode of pMOS pipe M9b meets reference current source I
RefSaid current-to-voltage converting circuit CS is to receive reading mode to select signal RMod to control, and here, the grid of the grid of pMOS pipe M9a and pMOS pipe M9b is used to receive reading mode and selects signal RMod.
Transmission gate TG0 is used to connect the first voltage C1 and the comparison amplifier positive input terminal that is produced by current-to-voltage converting circuit under the read current pattern; Transmission gate TG1 is used for connecting and reads preparatory amplifying voltage V1 and comparison amplifier positive input terminal under the voltage mode, and transmission gate TG1 is used to connect under the read current pattern to be used to be connected by the second voltage C2 of current-to-voltage converting circuit generation and comparison amplifier negative input end, transmission gate TG1 and reads that reference voltage V2 (is V under the voltage mode
Ref) and the comparison amplifier negative input end.In the present embodiment, said comparison amplifier is voltage comparator (CMP).
Phase inverter INV0 is used for selecting signal to carry out anti-phase to reading mode to be handled.Particularly; Phase inverter INV0 input end is used to receive reading mode and selects signal RMod; And be connected with the control end of each transmission gate TG0, TG1, TG2, TG3, phase inverter INV0 output terminal output reading mode selects the signal designature to be connected with the control end of each transmission gate TG0, TG1, TG2, TG3.Utilize the reading mode selection signal after reading mode is selected signal and process phase inverter INV0 thereof, can control the switching of each transmission gate TG0, TG1, TG2, TG3.
Current-to-voltage converting circuit is selected in said reading mode commutation circuit under the situation of read current pattern, and the paper tinsel digit current that will under the read current pattern, produce converts voltage into.In the present embodiment; Said current-to-voltage converting circuit is to be made up of pMOS pipe M6a, M6b, M6c, M6d and nMOS pipe M7a, M7b, M7c, M7d, and wherein, the grid of pMOS pipe M6a is connected with the drain electrode of the grid of pMOS pipe M5b, pMOS pipe M5b; The source electrode of pMOS pipe M6a meets supply voltage Vdd; The drain electrode of pMOS pipe M6a is connected with the drain electrode of nMOS pipe M7a, and the grid of nMOS pipe M7a is connected with the drain electrode of nMOS pipe M7a, the source ground of nMOS pipe M7a; The grid of pMOS pipe M6b is connected with the grid of pMOS pipe M6a; The source electrode of pMOS pipe M6b meets supply voltage Vdd; The drain electrode of pMOS pipe M6b is connected with the drain electrode of nMOS pipe M7b, and the grid of nMOS pipe M7b is connected with the grid of nMOS pipe M7d, the source ground of nMOS pipe M7b; The grid of pMOS pipe M6c is connected with the grid of pMOS pipe M6d; The source electrode of pMOS pipe M6c meets supply voltage Vdd; The drain electrode of pMOS pipe M6c is connected with the drain electrode of nMOS pipe M7c, and the grid of nMOS pipe M7c is connected with the grid of nMOS pipe M7a, the source ground of nMOS pipe M7c; The grid of pMOS pipe M6d is connected with the grid of pMOS pipe M8; The source electrode of pMOS pipe M6d meets supply voltage Vdd; The drain electrode of pMOS pipe M6d is connected with the drain electrode of nMOS pipe M7d, and the grid of nMOS pipe M7d is connected with the drain electrode of nMOS pipe M7d, the source ground of nMOS pipe M7d.
Discharge circuit is used for comparing on the said bit line of releasing after amplifieroperation is compared in the amplifying circuit completion and the remaining electric charge of said data reading circuit load end said.In the present embodiment, said discharge circuit comprises that controlled nMOS pipe M1a that is connected between said pre-charge circuit and the ground wire and the controlled nMOS that is connected between said bit line and the ground wire manage M1b.The grid of controlled nMOS pipe M1a connects sparking voltage, and precharge paper tinsel position nMOS manages the source electrode of M2b in the source ground of controlled nMOS pipe M1a, the drain electrode of controlled nMOS pipe M1a and said pre-charge circuit, an end of transmission gate is connected; The grid of controlled nMOS pipe M1b connects sparking voltage, the source ground of controlled nMOS pipe M1b, and the drain electrode of controlled nMOS pipe M1b is connected with the other end of said bit line, transmission gate.Preferably, the control signal of the pipe of the nMOS in discharge circuit M1a is effective and effective when each read operation is accomplished when sheet is selected invalidating signal to read; The control signal of nMOS pipe M1b in the discharge circuit is effective when each read operation is accomplished.Utilize discharge circuit, can be with falling with the remaining charge discharging resisting of data reading circuit load end on the bit line, thus reduce even stop data-crosstalk, improve the reliability that data reading speed and data are read.
When using the data reading circuit of reading the switchable phase transition storage of voltage/read current shown in Figure 3,
When reading mode selects signal RMod to be high level " 1 "; Said data reading circuit is operated in reads voltage mode; PMOS pipe M9a, M9b as reading mode SS pipe break off, and transmission gate TG1, TG3 conducting (transmission gate TG0, TG2 turn-off) are through the bias current I of adjustment
BiasBe poured on the bit line BL through pMOS pipe M4, M5a; Paper tinsel position nMOS pipe M2a in the circuit of paper tinsel position plays preparatory amplification; Obtain preparatory amplifying voltage V1; Like this, in advance amplifying voltage V1 and reference voltage Vref are sent to the input end of voltage comparator CMP respectively through transmission gate TG1, TG3, and voltage comparator CMP compares preparatory amplifying voltage V1 afterwards to export with reference voltage Vref and reads the result; When reading mode selects signal RMod to be low level " 0 "; Said data reading circuit is operated in the read current pattern; PMOS pipe M9a, M9b as reading mode SS pipe are closed; Transmission gate TG0, TG2 conducting (transmission gate TG1, TG3 turn-off), paper tinsel position nMOS pipe M2a plays clamping action in the circuit of paper tinsel position, produces clamp current I
Cell, since the existence of pMOS pipe M5b pipe, paper tinsel digit current I
CellWith difference I through adjusted bias current
C(I
C=I
Cell-mgI
Bias) will flow through pMOS pipe M5b, and then with reference current I
RefThe input current voltage conversion circuit, by it with difference I
CWith reference current I
RefCarry out computing and then convert complementary two-way voltage C1, C2 into, two-way voltage C1, C2 are sent to the input end of voltage comparator CMP respectively through transmission gate TG0, TG2, and voltage comparator CMP compares back output with voltage C1, C2 and reads the result.
In sum; The data reading circuit of reading the switchable phase transition storage of voltage of the present invention; Can compare read current effectively and read the serviceability of voltage mode under the different loads condition through mode switch; And, realize the optimum efficiency of read-out speed, high low resistance state resolution, power consumption to the reading mode that different loading condition selections is complementary with it.
The foregoing description is just listed expressivity principle of the present invention and effect is described, but not is used to limit the present invention.Any personnel that are familiar with this technology all can make amendment to the foregoing description under spirit of the present invention and scope.Therefore, rights protection scope of the present invention should be listed like claims.
Claims (13)
1. data reading circuit of reading the switchable phase transition storage of voltage/read current, said phase transition storage comprises one or more phase-change memory cells, each phase-change memory cell links to each other with control circuit with word line through bit line; It is characterized in that said data are read packet and drawn together:
Paper tinsel position voltage generation circuit is used to produce paper tinsel position voltage;
Pre-charge circuit, the bit line to said storage unit under the control of said paper tinsel position voltage carries out rapid charge;
Paper tinsel position circuit by the control of paper tinsel position voltage, has and carries out the paper tinsel position in pairs of bit line under the read current pattern and produce first mode of operation of paper tinsel digit current and reading that pairs of bit line signal under the voltage mode amplifies in advance and second mode of operation that produces preparatory amplifying voltage;
The reading mode commutation circuit; Select to select the read current pattern under the signal controlling or read voltage mode at reading mode; Control paper tinsel position circuit is carried out first mode of operation or corresponding second mode of operation of reading voltage mode of corresponding read current pattern, and selection needs two-way voltage relatively;
Current-to-voltage converting circuit is selected in said reading mode commutation circuit under the situation of read current pattern paper tinsel digit current that produces and the reference current under the read current pattern to be carried out computing, and then is converted complementary two-way voltage into;
Compare amplifying circuit, the two-way voltage that said reading mode commutation circuit is selected compares, and the result is read in output; Under the read current pattern, the two-way voltage that said reading mode commutation circuit is selected comprises that said current-to-voltage converting circuit conversion back forms complementary two-way voltage; Reading under the voltage mode, the two-way voltage that said reading mode commutation circuit is selected comprises the preparatory amplifying voltage that paper tinsel position circuit pairs of bit line signal amplifies in advance and reads the reference voltage under the voltage mode.
2. the data reading circuit of phase transition storage as claimed in claim 1; It is characterized in that; Also be included in the bit line transmission gate that is connected in series on the said bit line, make said pre-charge circuit and said paper tinsel digit current produce circuit and be connected with said bit line via said bit line transmission gate.
3. the data reading circuit of phase transition storage as claimed in claim 1; It is characterized in that; Also comprise discharge circuit, be used for comparing on the said bit line of releasing after amplifieroperation is compared in the amplifying circuit completion and the remaining electric charge of said data reading circuit load end said.
4. the data reading circuit of phase transition storage as claimed in claim 3; It is characterized in that said discharge circuit comprises that controlled nMOS pipe that is connected between said pre-charge circuit and the ground wire and controlled the 2nd nMOS that is connected between said bit line and the ground wire manage.
5. like the data reading circuit of claim 1 or 3 described phase transition storages, it is characterized in that, also comprise the bit line bias current circuit, be used for bias current being provided to bit line.
6. the data reading circuit of phase transition storage as claimed in claim 5; It is characterized in that; Said bit line bias current circuit comprises the current-mirror structure that is formed by two pMOS pipes; Wherein, the drain electrode of pMOS pipe is connected with bias current sources, and the drain electrode of the 2nd pMOS pipe is connected with said paper tinsel position circuit.
7. the data reading circuit of phase transition storage as claimed in claim 6 is characterized in that, said bit line bias current circuit is in respectively that its bias current sources has different electric currents when reading voltage mode with the read current pattern.
8. the data reading circuit of phase transition storage as claimed in claim 1; It is characterized in that; Said paper tinsel position voltage generation circuit comprises current source, connects into the nMOS pipe of diode and the 2nd nMOS pipe that is connected in series with nMOS pipe, and the drain electrode of nMOS pipe is connected with the current output terminal of said current source, and the grid of nMOS pipe is connected with the grid of the 2nd nMOS pipe; The source electrode of the one nMOS pipe is connected with the drain electrode of the 2nd nMOS pipe, the source ground of the 2nd nMOS pipe.
9. the data reading circuit of phase transition storage as claimed in claim 1 is characterized in that, the precharge paper tinsel position nMOS pipe that said pre-charge circuit comprises the precharge switch pipe and connects with said precharge switch pipe.
10. the data reading circuit of phase transition storage as claimed in claim 1 is characterized in that, said paper tinsel position circuit comprises paper tinsel position nMOS pipe.
11. the data reading circuit of phase transition storage as claimed in claim 1 is characterized in that, said reading mode commutation circuit comprises: the current-to-voltage converting circuit CS; Amplifying circuit input signal SS relatively comprises being used for connecting respectively first voltage and the comparison amplifier positive input terminal that are produced by current-to-voltage converting circuit under the read current pattern, reading under preparatory amplifying voltage and comparison amplifier positive input terminal under the voltage mode, the read current pattern by second voltage and the comparison amplifier negative input end of current-to-voltage converting circuit generation, reading four transmission gates of reference voltage and comparison amplifier negative input end under the voltage mode; And be used for reading mode selection signal is carried out anti-phase and obtains the phase inverter that reading mode is selected the signal designature.
12. the data reading circuit of phase transition storage as claimed in claim 11; It is characterized in that; Reading mode is selected signal and is selected the signal designature to be carried in the control end and the current-to-voltage converting circuit CS control end of four transmission gates respectively through the reading mode of phase inverter: when selecting signal for " 1 "; The current-to-voltage converting circuit CS cuts out, and is connected the transmission gate of preparatory amplifying voltage and comparison amplifier positive input terminal and is connected the transmission gate conducting of reading voltage mode reference voltage and comparison amplifier negative input end; Otherwise; When selecting signal to be " 0 "; The current-to-voltage converting circuit CS is opened, and is connected under the read current pattern transmission gate of first voltage that produced by current-to-voltage converting circuit and comparison amplifier positive input terminal and is connected under the read current pattern by second voltage of current-to-voltage converting circuit generation and the transmission gate conducting of comparison amplifier negative input end.
13. the data reading circuit like claim 1,11 or 12 described phase transition storages is characterized in that, said relatively amplifying circuit comprises voltage comparator.
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| CN201110151738.4A CN102820055B (en) | 2011-06-07 | 2011-06-07 | Data readout circuit for phase change memorizer |
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| CN201110151738.4A CN102820055B (en) | 2011-06-07 | 2011-06-07 | Data readout circuit for phase change memorizer |
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| CN107622780A (en) * | 2017-09-27 | 2018-01-23 | 中国科学院上海微系统与信息技术研究所 | Three-dimensional perpendicular type memory readout circuit and its reading method |
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