CN101246740A - Ultra-low power consumption nonvolatile static random access memory cell and operation method thereof - Google Patents
Ultra-low power consumption nonvolatile static random access memory cell and operation method thereof Download PDFInfo
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- CN101246740A CN101246740A CNA2008100345459A CN200810034545A CN101246740A CN 101246740 A CN101246740 A CN 101246740A CN A2008100345459 A CNA2008100345459 A CN A2008100345459A CN 200810034545 A CN200810034545 A CN 200810034545A CN 101246740 A CN101246740 A CN 101246740A
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Abstract
The invention belongs to the field of service integrated circuit technology. Specifically, the invention is an ultra-low power consumption non-volatile static random access memory cell. The memory cell employs a two-element or over-two-element multi-element metal oxide as a non-volatile memory resistance, comprising a six-transistor static random access memory cell, two complementary memory resistances, two gating transistors respectively coupled with the two memory resistances and a read buffer composed of two NMOS transistors; the internal transistors of the non-volatile static memory cell are subthreshold at proper time, thus realizing ultra-low power consumption.
Description
Technical field
The invention belongs to technical field of integrated circuits, be specifically related to a kind of ultra-low power consumption nonvolatile static random access memory cell (SRAM) and method of operating thereof.
Background technology
Static RAM (static random access memory is called for short SRAM) is a kind of storer with static access facility, does not need refresh circuit can preserve the data of its storage inside.SRAM has higher performance, and outstanding behaviours is fast in speed, and is energy-conservation, needn't cooperate the memory refresh circuit, can improve whole work efficiency.But SRAM also has its shortcoming, and is lower as its integrated level.In addition, the defective of SRAM maximum be exactly after the power down canned data can lose, be called volatibility or volatility.
Resistance random access memory (resistive random access memory abbreviates RRAM as) is because it is non-volatile, high density, low cost, the characteristics that can break through the technology generation development restriction cause and show great attention to, and employed material has phase-change material
[1], the SrZrO that mixes
3 [2], ferroelectric material PbZrTiO
3 [3], ferromagnetic material Pr
1-xCa
xMnO
3 [4], the binary metal oxide material
[5], organic material
[6]Deng.This is Cu wherein
xThe characteristic that O can be used as storage medium is proved
[7]
Fig. 1 is the characteristic synoptic diagram of I-V of the resistive memory cell that has been in the news
[7], adopt the different voltage of polarity to carry out transition cases between high resistant and low-resistance, curve 101 has represented that primary state is the IV curve of high resistant, the voltage scanning direction increases to V when voltage since 0 to forward as shown by arrows gradually
T1The time, electric current can increase rapidly suddenly, shows that memory resistor is mutated into low resistive state from high resistant, and the electric current increase is not unconfined in the synoptic diagram, but be subjected to the constraint of current limiting element in the loop, no longer increase after arriving maximal value (hereinafter referred to as the value of clamping down on) with voltage.Curve 100 has represented that primary state is the state of low-resistance, gradually increases to V by 0 to negative sense when voltage
T2The time, electric current can reduce rapidly suddenly, shows that memory resistor is mutated into high-impedance state from low-resistance.High resistant is represented different data modes respectively with low-resistance, and this change is repeatedly reversible, can realize data storage thus.
Non-volatilization SRAM (NVSRAM) combines the advantage of SRAM and nonvolatile memory, be applicable to and require the continuous high speed data to write and guarantee the occasion that non-volatile data is perfectly safe, application is extensive, for example: network communication class (router, high-end switch, fire wall etc.); Printing device class (printer, facsimile recorder, scanner); Industry Control class (industrial control board, railway/subway signal control system, high-tension electricity relay etc.); Auto electronics (Tachographs etc.); Medical Devices (as color ultrasound); Server category (Redundant Arrays of Inexpensive Disks server).
Along with diminishing gradually of integrated circuit technology size, low-power consumption has become the integrated circuit main development tendency.Reduce power consumption and can extend the life of a cell on the one hand, can save resource on the other hand, and then reduce the operating cost of system.In recent years, subthreshold value low consumption circuit technology has had large development.Therefore, in order to reduce the power consumption of non-volatilization SRAM, allowing wherein transistor work in the subthreshold value zone is unusual effective measures.
Summary of the invention
The object of the present invention is to provide a kind of NVSRAM unit of super low-power consumption, and propose corresponding method of operation.
The super low-power consumption NVSRAM unit that the present invention proposes, with binary or the multi-element metal oxide more than the binary as non-volatile memory resistor, comprise six traditional pipe SRAM, the memory resistor of two complementations, two gate tube and sense buffers of forming by two NMOS pipes that are coupled respectively with memory resistor; The top electrode of two memory resistor respectively with SRAM the drain terminal of last trombone slide (following trombone slide) be coupled, the drain terminal of the other end and gate tube is coupled.The grid of the gate tube that is coupled with memory resistor and the control signal of source end need not to add, and are provided by the circuit internal signal.Two NMOS pipes of sense buffer, the complementary storing value of the grid of one of them NMOS and static random access memory (sram) cell is coupled, and source end and ground wire are coupled, and the source end of another NMOS pipe of drain terminal and sense buffer is coupled; The grid and the readout word line of another NMOS pipe are coupled, and drain terminal and sense bit line are coupled, and the drain terminal of source end and previous NMOS pipe is coupled.The grid and the write word line of two gate tubes of SRAM are coupled, and drain terminal is coupled with write bit line and complementary write bit line respectively.Two pull-down NMOS pipe of SRAM can design by minimum dimension, and can not cause reducing of read noise tolerance limit.Memory resistor adopts the two-phase voltage-programming.
Metal oxide of the present invention has quick conversion characteristic, the characteristics of low operating current voltage, and very high with the compatibility of modern COMS technology.This metal oxide is oxide, titanyl compound, the oxide of nickel, the oxide of zirconium, the oxide of aluminium, the oxide of niobium, the oxide of tantalum, the SrZrO of copper
3Perhaps PbZrTiO
3, or Pr
1-xCa
xMnO
3(0.2≤x≤0.5).
The method of operating of the super low-power consumption NVSRAM unit that the present invention proposes comprises reset operation, read-write operation, non-volatile storage operation, write back operations.Reset operation is meant to be wanted earlier memory resistor to be reset to original state before write operation.Read-write operation is undertaken by read-write gate tube and read-write bit line respectively.Non-volatile storage operation is meant when power supply monitoring circuit detects power supply power-fail, and the information in the six pipe static random access memory (sram) cells is written in the memory resistor.After write back operations is meant and treats the power up power supply, the information in the memory resistor is written back to six pipe static random access memory (sram) cells.
The supply voltage of the super low-power consumption NVSRAM unit that the present invention proposes is dynamic change.When this unit carried out read-write operation, supply voltage was lower than the threshold voltage of NMOS, and all crystals pipe of NVSRAM works in sub-threshold region or cut-off region; When this unit carried out reset operation, non-volatile operation and write back operations, supply voltage was lifted to analog value, to satisfy the condition of each operation.
The nonvolatile static memory cell of the present invention's design, its inner transistor can enter the subthreshold value zone in due course, finally realizes super low-power consumption.
Description of drawings
Fig. 1 is the I-V family curve of the resistance random access memory of report at present.
The real example of the super low-power consumption NVSRAM cellular construction that Fig. 2 the present invention proposes.
The operational flowchart of Fig. 3 super low-power consumption NVSRAM unit.
The sectional view (part) of Fig. 4 super low-power consumption NVSRAM cellular construction embodiment.
Fig. 5 super low-power consumption NVSRAM unit one the reverse voltage time sequential routine embodiment.
The structure of Fig. 6 super low-power consumption NVSRAM memory array.
Embodiment
Hereinafter more specifically describe the present invention, the invention provides preferred embodiment, but should not be considered to only limit to embodiment set forth herein in conjunction with diagram and reference example.
At this reference diagram is the synoptic diagram of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in the zone shown in the figure.
Should be appreciated that this element can directly connect or be couple to another element, also can have insertion element when claiming an element with " another element is connected " or " coupling with another element ".On the contrary, when claiming an element " directly to be connected " or when " direct and another element couples ", not having insertion element with another element.
It is the I-V curve of the material of representative with CuxO that accompanying drawing 1 has provided.
The embodiment of the super low-power consumption NVSRAM structure that the present invention proposes is described below with reference to Fig. 2.Fig. 2 has provided the circuit structure of a super low-power consumption NVSRAM unit.Among this embodiment, metal-oxide-semiconductor 221-226 has constituted a traditional SRAM structure.Two memory resistor 227 and 228 top electrode respectively with SRAM the drain terminal 212 and 213 of last trombone slide (following trombone slide) be coupled, the other end is coupled with the drain terminal of gate tube 217 and 218 respectively.Gate tube 217 that is coupled with memory resistor and 218 grid and the control signal of source end need not to add, and are provided by the circuit internal signal.Two NMOS pipes 219 and 220 of sense buffer, the grid of one of them NMOS pipe 219 and the complementary storing value 212 of static random access memory (sram) cell are coupled, and source end and ground wire 216 are coupled, and the source end of another NMOS pipe 220 of drain terminal and sense buffer is coupled; The grid and the readout word line 201 of another NMOS pipe 220 are coupled, and drain terminal and sense bit line are coupled, and the drain terminal of source end and previous NMOS pipe 219 is coupled.Two gate tubes 221 of SRAM and 222 grid and write word line 202 are coupled, and drain terminal is coupled with write bit line 210 and complementary write bit line 204 respectively.Two pull-down NMOS pipe 225 of SRAM and 226 can design by minimum dimension, and can not cause reducing of read noise tolerance limit.Memory resistor 227 and 228 adopts the two-phase voltage-programming.
Fig. 3 has provided an embodiment of the operating process of NVSRAM unit among the present invention.After NVSRAM was finished reset operation, this moment, supply voltage dropped to below the metal-oxide-semiconductor threshold voltage, can carry out the read-write operation of extremely low power dissipation.Simultaneously, NVSRAM is in detecting power supply power-fail whether hold mode, in case detect power supply power-fail, then enters store status.Automatically enter the write-back state after restoring electricity.Before the NVSRAM unit being carried out write operation, need carry out reset operation with two all erasable one-tenth low resistance states of memory resistor at every turn.Before power down, implement storage operation, carry out write back operations after restoring electricity.The read-write operation of NVSRAM is undertaken by read-write word line, bit line respectively.
Fig. 4 has provided a part of sectional view of super low-power consumption NVSRAM cellular construction embodiment, comprises memory resistor 227, gate tube 217 and respective gut.
Fig. 5 has provided an embodiment who super low-power consumption NVSRAM unit is carried out the reverse voltage time sequential routine.
Illustrate below, at first memory resistor 607 is reset to high-impedance state.Before memory resistor is operated, earlier supply voltage 203 is lifted to general supply voltage v2 from the v1 that is lower than the metal-oxide-semiconductor threshold voltage, reset operation can be carried out.Again that sel signal and control is effective, will on memory resistor 227 and 228, produce enough negative voltages like this.By the value of sel and control suitably is set, the negative pressure on the memory resistor 227 and 228 satisfies the condition that CuxO resets, and they all convert high resistant to.Then, sel signal and control are invalid, and supply voltage comes back to the v1 that is lower than threshold voltage, and reset operation is finished.
Just can carry out read-write operation behind the reset operation to the NVSRAM unit.When carrying out write operation, write word line wwl is effective, by apply suitable write signal on write bit line wbl and complementary write bit line wblb, can finish write operation; When carrying out read operation, at first sense bit line is charged to v1, readout word line rwl is effective then, and the value of storing according to SRAM is 0 or 1, and sense bit line will discharge or keep, and then realizes reading.The solid line of rbl represents to read 1 among Fig. 5, and dotted line represents to read 0.
When power supply monitoring circuit detected power supply power-fail, supply voltage vdd was elevated to v2, and the sel signal is effective simultaneously, and the control signal is a low level, and storage operation can be carried out.The value of supposing SRAM is 1, and promptly 213 electromotive force is v2, and 212 electromotive force is 0.At this moment, memory resistor 227 both end voltage are approximately v2, and memory resistor 228 both end voltage are approximately 0.By suitable v2 value is set, v2 can satisfy the condition of memory resistor set, and memory resistor 227 transfers low-resistance to by high resistant like this.Then, sel is invalid, and storage operation is finished, and power supply can break.The value of SRAM is that 0 situation and aforesaid operations process are similar.
When carrying out write back operations, sel and control signal are effective earlier, because the value difference of two memory resistor, SRAM charges on both sides, and low-resistance one side charging rate is fast, and electromotive force rises fast.Supply voltage 202 rises to v2 then, and through the positive feedback of SRAM inside, the memory node electromotive force of final low-resistance one side is v2, and the memory node electromotive force of high resistant one side is 0.
Fig. 6 has provided the memory construction of the super low-power consumption NVSRAM of the present invention's proposition.The gating device that is arranged in the different storage unit of delegation links to each other with write word line WWL with same readout word line RWL, samely lists different storage unit and all links to each other with write bit line with identical sense bit line and be positioned at.Readout word line, write word line link to each other with line decoder 601, and sense bit line, write bit line link to each other with column decoder 604, and the storage unit of row and column infall is exactly to choose the unit that will operate.Control module 601 produces the control signal of whole storer, comprises enable signal (not drawing among the figure), supply voltage 203, sel signal 205 and control signal 206 to other modules.The variation of pairs of bit line voltage was sensitive when the bit line that the effect of module 603 produces when being write operation was write voltage and read operation amplifies.
List of references:
[1]An?Chen，Sameer?Haddad，Yi-Ching(Jean)Wu，Tzu-Ning?Fang，Zhida?Lan，Steven?Avanzino，Suzette?Pangrle，Matthew?Buynoski，Manuj?Rathor，Wei(Daisy)Cai，Nick?Tripsas，Colin?Bill，Michael?VanBuskirk，and?MasaoTaguchi，“Non-Volatile?Resistive?Switching?for?Advanced?Memory?Applications，”IEEE，2005.
[2]Naveen?Verma，Anantha?P.Chandrakasan，“A?65nm?8T?Sub-Vt?SRAM?Employing?Sense?AmplifierRedundancy，”ISSCC，pp.327-328，2007.
Claims (7)
1, a kind of ultra-low power consumption nonvolatile static random access memory cell, it is characterized in that adopting the above multi-element metal oxide of binary or binary as non-volatile memory resistor, comprise one six pipe static random access memory (sram) cell, the memory resistor of two complementations, two gate tube and sense buffers of forming by two NMOS pipes that are coupled respectively with memory resistor; Wherein, two memory resistor one ends are coupled with the last trombone slide of six pipe static random access memory (sram) cells or the drain terminal of following trombone slide respectively, and the drain terminal of the other end and gate tube is coupled; The grid of the gate tube that is coupled with memory resistor and the control signal of source end need not to add, and are provided by the circuit internal signal; Two NMOS pipes of sense buffer, the complementary storing value of the grid of one of them NMOS and static random access memory (sram) cell is coupled, and source end and ground wire are coupled, and the source end of another NMOS pipe of drain terminal and sense buffer is coupled; The grid and the readout word line of another NMOS pipe are coupled, and drain terminal and sense bit line are coupled, and the drain terminal of source end and previous NMOS pipe is coupled.
2, ultra-low power consumption nonvolatile static random access memory cell according to claim 1 is characterized in that: the grid and the write word line of two gate tubes of six pipe static random access memory (sram) cells are coupled, and drain terminal is coupled with write bit line and complementary write bit line respectively.
3, ultra-low power consumption nonvolatile static random access memory cell according to claim 1 is characterized in that: two pull-down NMOS pipe of six pipe static random access memory (sram) cells can not cause reducing of read noise tolerance limit by minimum dimension.
4, ultra-low power consumption nonvolatile static random access memory cell according to claim 1 is characterized in that: memory resistor two-phase voltage-programming.
5, ultra-low power consumption nonvolatile static random access memory cell according to claim 1 is characterized in that: described metal oxide is oxide, titanyl compound, the oxide of nickel, the oxide of zirconium, the oxide of aluminium, the oxide of niobium, the oxide of tantalum, the SrZrO of copper
3, PbZrTiO
3Perhaps Pr
1-xCa
xMnO
3, 0.2≤x≤0.5.
6, ultra-low power consumption nonvolatile static random access memory cell according to claim 1 is characterized in that: the supply voltage that is coupled with six pipe static random access memory (sram) cells is dynamic change.
7, a kind of the described ultra-low power consumption nonvolatile static random access memory cell of claim 1 is carried out method of operating, comprises reset operation, read-write operation, non-volatile storage operation and write back operations, it is characterized in that:
Reset operation: before write operation, want earlier memory resistor to be reset to original state, before memory resistor is operated, by the operation of pairs of bit line and six pipe static random access memory (sram) cell gate tubes, guarantee the gate tube conducting of memory resistor, reset operation can be carried out;
Read-write operation: write fashionablely, choose the storage unit that need write by address signal, the write word line signal of selected unit enables, and is operated on it by the write bit line of configuration register by two complementations; When reading, choose the storage unit that need read by address signal, the read word line signal of selected unit enables, and data are exported by sense amplifier through sense bit line;
Non-volatile storage operation: when power supply monitoring circuit detects power supply power-fail,, memory resistor is operated, the information in the six pipe static random access memory (sram) cells is written in the memory resistor by corresponding control signal is set;
Write back operations: after treating the power up power supply,, memory resistor is operated, the information in the memory resistor is written back to six pipe static random access memory (sram) cells by corresponding control signal is set.
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| CN101872642A (en) * | 2009-04-23 | 2010-10-27 | 无锡华润上华半导体有限公司 | Storing and reading method for random access memory |
| CN101923893A (en) * | 2009-06-10 | 2010-12-22 | 台湾积体电路制造股份有限公司 | Static random access memory array |
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| CN101625891B (en) * | 2009-08-12 | 2011-08-03 | 东南大学 | Sub-threshold storing unit circuit with high density and high robustness |
| CN102290096A (en) * | 2010-06-18 | 2011-12-21 | 黄效华 | decoding and logic control circuit of static random access memory |
| US8422295B1 (en) | 2011-11-08 | 2013-04-16 | Industrial Technology Research Institute | Non-volatile random access memory coupled to a first, second and third voltage and operation method thereof |
| CN102411990A (en) * | 2011-11-11 | 2012-04-11 | 上海新储集成电路有限公司 | Bit-level twin-port nonvolatile static random access memory and implementation method thereof |
| CN102411990B (en) * | 2011-11-11 | 2014-04-16 | 上海新储集成电路有限公司 | Bit-level twin-port nonvolatile static random access memory and implementation method thereof |
| CN102760486A (en) * | 2012-07-20 | 2012-10-31 | 北京大学 | SRAM (Static Random Access Memory) cell and memory array |
| CN105144381A (en) * | 2013-03-15 | 2015-12-09 | 高通股份有限公司 | Three-dimensional (3D) memory cell with read/write ports and access logic on different tiers of integrated circuit |
| CN105144381B (en) * | 2013-03-15 | 2018-01-19 | 高通股份有限公司 | Three-dimensional (3D) memory cell with the read/write port on the different layers of integrated circuit and access logic unit |
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| CN105408959B (en) * | 2013-07-30 | 2018-03-27 | 高通股份有限公司 | It is used for the circuit and related systems and methods to static RAM bit location making alive or current bias during static RAM resets operation |
| CN104617943A (en) * | 2015-02-06 | 2015-05-13 | 中国人民解放军国防科学技术大学 | Multi-threshold low-power D-type CR register |
| CN104617943B (en) * | 2015-02-06 | 2016-03-30 | 中国人民解放军国防科学技术大学 | Multi thresholds low-power consumption D type CR register |
| CN105261392A (en) * | 2015-11-16 | 2016-01-20 | 西安华芯半导体有限公司 | Memorizing unit and method based on resistive random access memory (RRAM) |
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| CN105976859B (en) * | 2016-05-20 | 2019-05-17 | 西安紫光国芯半导体有限公司 | A kind of control method of the ultralow Static RAM write operation for writing power consumption |
| WO2021083356A1 (en) * | 2019-11-01 | 2021-05-06 | 华为技术有限公司 | Storage and computation unit and chip |
| CN112634957A (en) * | 2020-12-29 | 2021-04-09 | 中国科学院上海微系统与信息技术研究所 | Low-power consumption static random access memory unit and memory |
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