CN110070904B

CN110070904B - Memory, chip and circuit control method

Info

Publication number: CN110070904B
Application number: CN201910314248.8A
Authority: CN
Inventors: 黄瑞峰; 杨昌楷; 王建龙
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2019-04-18
Filing date: 2019-04-18
Publication date: 2021-01-29
Anticipated expiration: 2039-04-18
Also published as: CN110070904A

Abstract

The embodiment of the invention provides a memory, a chip and a circuit control method, wherein the memory comprises: a word line; a redundant word line; memory cells connected to the word lines; redundant memory cells connected to the redundant word lines; wherein, when there is no abnormal memory cell, a sense amplifier is implemented using the redundant memory cell; when an abnormal memory cell exists, at least one redundant memory cell is reserved to realize a sense amplifier, and the other target redundant memory cells are used for replacing the abnormal memory cell. The embodiment of the invention can improve the area ratio of the memory unit in the memory and reduce the area consumption of the memory on the basis of effectively utilizing the redundant memory unit.

Description

Memory, chip and circuit control method

Technical Field

The embodiment of the invention relates to the technical field of memories, in particular to a memory, a chip and a circuit control method.

Background

The Memory is a device for storing data widely used in a chip, and particularly, an SRAM (Static Random-Access Memory) is a typical Memory, and is widely used in a chip due to advantages of low power consumption, high reading speed, and the like.

The memory cell is used as a basic structure of the memory, and the memory generally stores data through a memory cell array consisting of a plurality of memory cells; in the design of the memory, in order to avoid the memory performance of the memory from being affected by abnormal memory cells (such as damaged memory cells), the memory is generally designed with a redundant memory cell in addition to the memory cells, so that when the memory cells are abnormal, the abnormal memory cells can be replaced by the redundant memory cells, thereby reducing the performance loss of the memory; however, if the memory cells in the memory are not abnormal, the redundant memory cells become useless, and thus the redundant memory cells are not effectively utilized in the prior art, which wastes the area of the memory to a certain extent.

Disclosure of Invention

In view of this, embodiments of the present invention provide a memory, a chip and a circuit control method to effectively utilize redundant memory cells and achieve efficient utilization of memory area.

In order to achieve the above purpose, the embodiments of the present invention provide the following technical solutions:

a memory, comprising:

a word line;

a redundant word line;

memory cells connected to the word lines;

redundant memory cells connected to the redundant word lines;

wherein, when there is no abnormal memory cell, a sense amplifier is implemented using the redundant memory cell; when an abnormal memory cell exists, at least one redundant memory cell is reserved to realize a sense amplifier, and the other target redundant memory cells are used for replacing the abnormal memory cell.

Optionally, the memory further includes: a control transistor connected to the redundant memory cell;

if the signal control end of the control transistor connected with the redundant storage unit is connected with a sensitive amplifier enabling signal, the redundant storage unit is used for realizing a sensitive amplifier; and if the signal control end of the control transistor connected with the redundant memory cell is connected with the first signal, the redundant memory cell is used for replacing the abnormal memory cell.

Optionally, the memory further includes: a control circuit; the control circuit is connected with the word lines, the redundant word lines and the signal control ends of the control transistors;

the control circuit is used for connecting a signal control end of a control transistor connected with the redundant storage unit to a sense amplifier enabling signal when an abnormal storage unit does not exist;

when an abnormal storage unit exists, a signal control end of a control transistor connected with at least one redundant storage unit is connected with a sensitive amplifier enabling signal; and shifting the word line address of the word line connected with the abnormal memory cell to the redundancy word line connected with the target redundancy memory cell by decoding, and switching the signal control end of the control transistor connected with the target redundancy memory cell into a first signal.

Optionally, the control circuit is further configured to:

when an abnormal storage unit does not exist, accessing a redundant word line connected with the redundant storage unit into a word line enabling signal;

when an abnormal storage unit exists, the redundant word line connected with the at least one redundant storage unit is switched into a word line enabling signal, the word line connected with the abnormal storage unit is set as a second signal, and the first signal and the second signal are opposite in logic.

Optionally, the control circuit includes: the device comprises a decoding circuit for generating a word line decoding signal, a word line enabling signal generating circuit for generating a word line enabling signal, a sensitive amplifier enabling signal generating circuit for generating a sensitive amplifier enabling signal, an AND gate, a first multiplexer and a second multiplexer;

the redundant memory cell includes: replaceable redundant memory cells and non-replaceable redundant memory cells; determining a target redundant memory cell from the replaceable redundant memory cells;

the decoding circuit and the word line enabling signal generating circuit are connected with a word line connected with the storage unit through an AND gate;

the decoding circuit and the word line enabling signal generating circuit are connected with a redundancy word line connected with a replaceable redundancy storage unit through a first multiplexer;

the decoding circuit and the sensitive amplifier enable signal generating circuit are connected with a signal control end of a control transistor connected with the replaceable redundant storage unit through a second multiplexer;

the redundancy word line connected with the non-replaceable redundancy memory unit is directly connected with the word line enabling signal generating circuit; and the signal control end of the control transistor connected with the irreplaceable redundant memory unit is directly connected with the sensitive amplifier enabling signal generating circuit.

Optionally, the and gate is a two-input and gate; the first input end of the two-input AND gate is connected with the word line enabling signal generating circuit, the second input end of the two-input AND gate is connected with the decoding circuit, and the output end of the two-input AND gate is connected with a word line connected with the storage unit;

the first multiplexer is a first second multiplexer; the first input end of the first two-way transmitter is connected with the word line enabling signal generating circuit, the second input end of the first two-way transmitter is connected with the decoding circuit, and the output end of the first two-way transmitter is connected with a redundant word line connected with the replaceable redundant memory unit;

the second multiplexer is a second multiplexer, a first input end of the second multiplexer is connected with the sense amplifier enabling signal generating circuit, a second input end of the second multiplexer is connected with the decoding circuit to receive the first signal, and an output end of the second multiplexer is connected with a signal control end of a control transistor connected with the replaceable redundant storage unit.

Optionally, the first two-way transmitter is configured to select a word line enable signal input by the first input terminal when there is no abnormal memory cell; when an abnormal memory cell exists, selecting a second input terminal to introduce a word line decoding signal to the redundant word line;

the second two-way transmitter is used for selecting the SAEN signal input by the first input end when no abnormal storage unit exists; when an abnormal memory cell exists, selecting the second input end to lead in a first signal to the signal control end of the control transistor connected with the output end;

the decoding circuit is used for shifting the word line address of the word line connected with the abnormal memory cell to the redundancy word line connected with the target redundancy memory cell through decoding when the abnormal memory cell exists.

Optionally, the control transistor is an NMOS transistor; the grid electrode of the control transistor is a control signal end, the drain electrode of the control transistor is connected with the redundant storage unit, and the source electrode of the control transistor is grounded.

Optionally, the redundant memory unit includes:

a first PMOS transistor P1, a first NMOS transistor N1, a second PMOS transistor P2, a second NMOS transistor N2, a third NMOS transistor N3 and a fourth NMOS transistor N4;

the grid electrode of the first PMOS tube P1, the grid electrode of the first NMOS tube N1, the drain electrode of the second PMOS tube P2, the drain electrode of the second NMOS tube N2 and the source electrode of the third NMOS tube N3 are connected to form a data node Q; the grid electrode of the second PMOS tube P2, the grid electrode of the second NMOS tube N2, the drain electrode of the first PMOS tube P1, the drain electrode of the first NMOS tube N1 and the source electrode of the fourth NMOS tube N4 are connected to form a data node QB;

the gates of the third NMOS transistor N3 and the fourth NMOS transistor N4 are connected with a word line WL, the drain of the third NMOS transistor N3 is connected with a bit line BL, and the drain of the fourth NMOS transistor N4 is connected with a bit line BLB; the source electrode of the first PMOS pipe P1 and the source electrode of the second PMOS pipe P2 are connected with a power supply voltage VDD; the source electrode of the first NMOS transistor N1 and the source electrode of the second NMOS transistor N2 are connected with the drain electrode of the control transistor.

Optionally, the memory further includes:

a plurality of pairs of bit lines connected in parallel with the word lines and redundant word lines.

An embodiment of the present invention further provides a chip, including: the memory described above.

An embodiment of the present invention further provides a circuit control method, based on the memory described above, the method includes:

when an abnormal storage unit does not exist in the memory, the sense amplifier is realized by using a redundant storage unit;

when an abnormal memory cell exists in the memory, at least one redundant memory cell is reserved to realize the sensitive amplifier, and the other target redundant memory cells are used for replacing the abnormal memory cell.

Optionally, the implementing the sense amplifier using the redundant memory cell includes:

connecting a signal control end of a control transistor connected with the redundant storage unit into a sense amplifier enabling signal;

the replacing the abnormal memory cell with the remaining target redundant memory cell comprises:

and shifting the word line address of the word line connected with the abnormal memory cell to the redundancy word line connected with the target redundancy memory cell by decoding, and switching the signal control end of the control transistor connected with the target redundancy memory cell into a first signal.

Optionally, the implementing the sense amplifier using the redundant memory cell further includes:

accessing a redundant word line connected with the redundant memory unit into a word line enabling signal;

the method further comprises the following steps:

when an abnormal memory cell exists in the memory, a word line connected with the abnormal memory cell is set as a second signal, and the first signal and the second signal are signals with opposite logics.

Optionally, the redundant memory unit includes: replaceable redundant memory cells and non-replaceable redundant memory cells; determining a target redundant memory cell from the replaceable redundant memory cells;

the accessing of the redundancy word line connecting the redundancy memory cells to the word line enable signal includes:

selecting a word line enabling signal accessed by a first input end of a first two-way transmitter, accessing the word line enabling signal by the first input end of the first two-way transmitter, accessing a word line decoding signal by a second input end of the first two-way transmitter, and connecting an output end of the first two-way transmitter with a redundant word line of a replaceable redundant memory unit;

the step of connecting a signal control end of a control transistor for connecting the redundant memory cell to a sense amplifier enabling signal comprises the following steps:

and selecting a sensitive amplifier enabling signal accessed by a first input end of the second two-way transmitter, accessing the sensitive amplifier enabling signal by the first input end of the second two-way transmitter, accessing the first signal by a second input end of the second two-way transmitter, and connecting an output end of the second two-way transmitter with a signal control end of a control transistor of the replaceable redundant storage unit.

The memory provided by the embodiment of the invention can realize the sense amplifier by using the redundant memory cell when the abnormal memory cell does not exist, thereby avoiding the condition that the redundant memory cell is useless when the memory cell is abnormal, and realizing the high-efficiency utilization of the redundant memory cell and the realization of the function of the sense amplifier of the memory; meanwhile, when an abnormal storage unit exists, at least one redundant storage unit can be reserved to realize a sensitive amplifier, and the rest target redundant storage units can be used for replacing the abnormal storage unit, so that the performance loss of the memory when the storage unit is abnormal is reduced; because the area of the memory cell is smaller than that of the traditional sense amplifier, the embodiment of the invention can improve the area ratio of the memory cell in the memory and reduce the area consumption of the memory on the basis of effectively utilizing the redundant memory cell.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a diagram of a memory of conventional design;

FIG. 2 is a schematic structural diagram of a memory according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a memory cell structure;

FIG. 4 is a schematic diagram of a conventional sense amplifier;

FIG. 5 is a schematic diagram of another structure of a memory according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a connection structure of a redundant memory cell and a control transistor;

FIG. 7 is a schematic diagram of the connection of a sense amplifier implemented using redundant memory cells;

FIG. 8 is a schematic diagram of waveforms;

FIG. 9 is a schematic diagram of the connection of an abnormal memory cell replaced with a redundant memory cell;

FIG. 10 is a diagram illustrating another structure of a memory according to an embodiment of the present invention;

FIG. 11 is a flowchart of a circuit control method according to an embodiment of the present invention;

FIG. 12 is a flowchart of a circuit control method according to an embodiment of the present invention;

FIG. 13 is a diagram illustrating another structure of a memory according to an embodiment of the present invention;

FIG. 14 is a flow chart of a method for implementing a sense amplifier using redundant memory cells;

FIG. 15 is a schematic diagram of a memory with signal routing;

FIG. 16 is a flow chart of a method for replacing an abnormal memory cell with a replaceable redundant memory cell;

FIG. 17 is a schematic diagram of another structure of a memory with signal routing;

FIG. 18 is another waveform diagram;

FIG. 19 is a schematic diagram of a redundant memory cell.

Detailed Description

Alternatively, fig. 1 shows a schematic diagram of a memory of conventional design, which is generally arranged in a matrix structure of rows and columns of memory cells, so that the memory may have a plurality of memory cell arrays, each of which may have a plurality of memory cells;

referring to FIG. 1, a memory is designed with a bit Line pair (BL and BLB), Word lines (Word Line, WL), redundant Word lines (denoted Red-WL), memory cells (denoted Cell), redundant memory cells (Red-Cell, which may be a shorthand for the Reduncyny Cell), and sense amplifiers (denoted SA); SA connection Data Output port (DO);

wherein, the English full spelling of BL is Bit Line, which represents Bit Line; the bit line pair can be formed by a bit line BL and a bit line bar BLB which are opposite in logic; the number of the bit line pairs can be multiple pairs, the number of the word lines can be multiple, the number of the redundant word lines can also be multiple, and the bit line pairs can be connected to the word lines and the redundant word lines in parallel;

for example, FIG. 1 illustrates a pair of bit line pairs, n +1 word lines and 2 redundant word lines, i.e., a pair of bit line pairs is coupled in parallel to n +1 word lines and 2 redundant word lines, n +1 word lines are WL [0] to WL [ n ], 2 redundant word lines are Red-WL [0] and Red-WL [1], respectively, the number of n can be set according to the actual design condition of the memory, and the embodiment of the present invention is not limited thereto; FIG. 1 shows only one pair of bit line pairs for ease of illustration, and multiple pairs may be present in a practical design;

the number of the memory cells may be plural, and the number of the redundant memory cells may also be plural, and fig. 1 shows that the case of 2 redundant memory cells is merely an illustration.

Based on the memory with the traditional design, when the memory unit is abnormal, the abnormal memory unit can be replaced by the redundant memory unit, and the performance loss of the memory when the memory unit is abnormal is reduced.

It can be seen that in the memory of the conventional design, the memory is not only designed with a storage unit for storing data, but also designed with a redundant storage unit for replacing the abnormal storage unit when the storage unit is abnormal, and meanwhile, the memory is also designed with a sense amplifier; however, the redundant memory cell can be effectively used only when the memory cell is abnormal, and when the memory cell is not abnormal, the redundant memory cell becomes useless, which does not allow effective use of the redundant memory cell; meanwhile, the sense amplifier of the memory consumes the area of the memory very much; therefore, how to realize the effective utilization of redundant memory cells in a memory, reduce the area consumption of the memory, and realize the efficient utilization of the area of the memory becomes a problem to be considered by those skilled in the art.

Based on this, the embodiment of the invention realizes effective utilization of the redundant memory unit by improving the memory, improves the area ratio occupied by the memory unit in the memory, reduces the area consumption of the memory, and realizes the efficient utilization of the area of the memory; the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As an optional implementation of the disclosure in the embodiment of the present invention, fig. 2 shows a schematic structural diagram of a memory provided in the embodiment of the present invention, and referring to fig. 2, the memory provided in the embodiment of the present invention may include:

word lines (denoted WL); the number of word lines may be multiple, for example, fig. 2 illustrates n +1 word lines (WL [0] to WL [ n ]), and the number of n may be determined according to the actual design situation;

redundant word lines (denoted Pro-WL); the number of redundant word lines may be multiple, and fig. 2 illustrates that 4 redundant word lines (Pro-WL [0] to Pro-WL [3]) are provided, however, the number of redundant word lines shown in fig. 2 is only exemplary, and the number of redundant word lines is not limited by the embodiment of the present invention, and may be determined according to actual design conditions;

a bit line pair (BL and BLB) connected in parallel with the word line and the redundancy word line; the number of bit line pairs may be multiple pairs, and for ease of illustration, only one pair is shown in FIG. 2;

memory cells (denoted by Cell); the number of the memory cells can be multiple, and the memory cells can be connected with word lines; for example, FIG. 2 shows a memory Cell connected to a word line, for example, the memory cells are divided into Cell [0] to Cell [ n ], Cell [0] is connected to WL [0], Cell [1] is connected to WL [1], and so on; obviously, the schematic connection between the memory cell and the word line shown in fig. 2 is only an optional example, and the embodiment of the present invention may also support other connection manners between the memory cell and the word line, as long as each memory cell is matched with the connected word line;

redundant memory cells (denoted Pro-Cell); the number of the redundant memory cells can be multiple, and the redundant memory cells can be connected with redundant word lines; for example, FIG. 2 illustrates a redundant memory Cell connected to a redundant word line, such as a redundant memory Cell that can be divided into Pro-Cell [0] to Pro-Cell [3],

Pro-Cell [0] is connected with Pro-WL [0], Pro-Cell [1] is connected with Pro-WL [1], and the like; it is obvious that the illustration of the connection of the redundant memory cells and the redundant word lines shown in fig. 2 is only an optional example, and other connection manners of the redundant memory cells and the redundant word lines can be supported by the embodiment of the present invention, as long as each redundant memory cell is matched with the connected redundant word line.

The memory provided by the embodiment of the invention is not designed with a traditional sense amplifier, and in the embodiment of the invention, the sense amplifier can be realized by a redundant storage unit; specifically, when there are no abnormal memory cells (e.g., there are no defective memory cells), embodiments of the present invention may implement a sense amplifier using redundant memory cells, for example, FIG. 2 illustrates an example of implementing a sense amplifier with Pro-Cell [0] to Pro-Cell [3 ];

when an abnormal storage unit exists, at least one redundant storage unit can be reserved to realize a sense amplifier (in order to enable the sense amplifier to exist in the memory and further realize data amplification output, at least one redundant storage unit needs to be reserved to realize the sense amplifier in the embodiment of the invention), and the rest redundant storage units can be used for replacing the abnormal storage unit; for convenience of description, the remaining redundant memory cells that are used to replace the abnormal memory cell may be referred to as target redundant memory cells in the embodiments of the present invention.

It can be understood that the area of the conventional sense amplifier is larger, if the conventional sense amplifier is designed in a memory, the area of the memory is greatly consumed, and the structure of the redundant memory cell can be consistent with that of the memory cell, and the use of the redundant memory cell to realize the sense amplifier can effectively improve the area ratio occupied by the memory cell in the memory (i.e. the memory with the same area can be distributed with more memory cells, that is, the area of the memory can be smaller under the same number of memory cells), and reduce the area consumption of the memory, on the other hand, in the embodiment of the present invention, the redundant memory cell can also be used for replacing an abnormal memory cell, and when the abnormal memory cell exists, the performance loss of the memory is reduced;

For ease of understanding, the following is an exemplary description of an alternative conventional sense amplifier and memory cell configuration; alternatively, fig. 3 shows an alternative structure of a memory Cell, and the structure shown in fig. 3 can be applied to the memory Cell shown in fig. 2 and can also be applied to the redundant memory Cell Pro-Cell; for example, in a memory (particularly an SRAM memory), the redundant memory cell and the memory cell may be implemented by using a 6T structure (that is, the memory cell is formed by a structure of 6 MOS transistors); the redundant memory unit adopts a 6T structure, so that the area of the redundant memory unit can be reduced, and the redundant memory unit and the memory unit can be seamlessly jointed;

as shown in fig. 3, the memory cell of the 6T structure may include:

a first PMOS tube P1 and a first NMOS tube N1 form a phase inverter, a second PMOS tube P2 and a second NMOS tube N2 form another phase inverter, a third NMOS tube N3 is an access tube of a data node Q, and a fourth NMOS tube N4 is an access tube of a data node QB, so that the two phase inverters form a stable data latch;

in specific connection, the grid electrode of the first PMOS tube P1, the grid electrode of the first NMOS tube N1, the drain electrode of the second PMOS tube P2, the drain electrode of the second NMOS tube N2 and the source electrode of the third NMOS tube N3 are connected to form a data node Q; the grid electrode of the second PMOS tube P2, the grid electrode of the second NMOS tube N2, the drain electrode of the first PMOS tube P1, the drain electrode of the first NMOS tube N1 and the source electrode of the fourth NMOS tube N4 are connected to form a data node QB;

the gates of the third NMOS transistor N3 and the fourth NMOS transistor N4 are connected to a word line WL (if a redundant memory cell is selected, the word line WL shown in fig. 3 may be replaced by a redundant word line Pro-WL), the drain of the third NMOS transistor N3 is connected to a bit line BL, and the drain of the fourth NMOS transistor N4 is connected to a bit bar line BLB; the source electrode of the first PMOS pipe P1 and the source electrode of the second PMOS pipe P2 are connected with a power supply voltage VDD; the source electrode of the first NMOS transistor N1 and the source electrode of the second NMOS transistor N2 are connected to a ground line VSS.

Alternatively, fig. 4 shows an alternative structure of a conventional sense amplifier, as shown in fig. 4, in which a charging circuit 101 may charge data nodes Q and QB to a supply voltage VDD before a read operation; when reading and writing starts, the charging circuit 101 is hung up, the voltage of the bit line BL is partially pulled down by the storage unit and is conducted to the data node Q through the PMOS tube 104; when the sense amplifier enable Signal (SAEN) is enabled, the NMOS transistor 103 is turned on, and the

PMOS transistors

104 and 105 are turned off; when SAEN is logic 1, the voltage of the signal P-VSS is pulled down to 0, and at this time, the latch 102 continues to pull down the voltage of the data node Q to 0 (for example, the power voltage VDD is 1V, and the voltage of the data node Q is already pulled down to 0.8V, then the latch 102 may continue to pull down the voltage of the data node Q to 0), so as to achieve the voltage amplification effect, and output the data to the data output terminal DO through output circuits.

Referring to fig. 3 and 4, it can be seen that the conventional sense amplifier is a circuit that consumes a large amount of memory area, and particularly, the conventional sense amplifier consumes a large amount of memory area when the number of Multiplexers (MUXs) is small; therefore, the embodiment of the invention abandons the traditional sense amplifier in the memory and realizes the sense amplifier by the redundant memory cell, thereby greatly reducing the consumed area of the memory.

As an optional implementation, the embodiment of the present invention may connect a control transistor outside the redundant memory cell, and control whether the word line of the redundant memory cell is used as the word line of the memory cell or the word line of the sense amplifier by controlling an access signal at a signal control end of the transistor, so as to implement switching between the replacement of the abnormal memory cell by the redundant memory cell and the implementation of the function of the sense amplifier, thereby achieving the functions of saving the memory area and providing the replacement of the abnormal memory cell;

optionally, if a signal control end of the control transistor connected to the redundant storage unit is connected to a sense amplifier enable signal, the redundant storage unit is used for implementing a sense amplifier; if the signal control terminal of the control transistor connected with the redundant memory cell is connected with a first signal (optionally, the first signal is logic 1), the redundant memory cell is used for replacing the abnormal memory cell.

Optionally, fig. 5 is a schematic diagram illustrating another structure of the memory according to an embodiment of the present invention, which is shown in fig. 2 and fig. 5:

in FIG. 5, the redundant memory Cell can be connected to a control transistor M in addition to the redundant word line, e.g., Pro-Cell [0] is connected to M [0], Pro-Cell [1] is connected to M [1], and so on; it should be noted that the control transistor is optionally not disposed in the memory cell array, but disposed outside the memory cell, and the redundant memory cell is externally connected to the control transistor, because the memory cell array may not have a redundant space for disposing the control transistor M, and meanwhile, the redundant memory cell is externally connected to the control transistor, which can reduce the modification to the memory cell array;

for example, in fig. 5, the control transistor is illustrated by taking an NMOS transistor as an example, a gate of the control transistor is a signal control terminal for accessing a control signal (Program-Sig may represent a control signal, for example, M [0] accesses the Program-Sig [0], M [1] accesses the Program-Sig [1], and so on), a drain is connected to the redundant memory cell, and a source is grounded.

As an alternative example, fig. 6 shows an alternative connection structure of the redundant memory cell and the control transistor, and in conjunction with fig. 3 and 6, the source of the first NMOS transistor N1 and the source of the second NMOS transistor N2 of the redundant memory cell are no longer connected to the ground line VSS but connected to the drain of the control transistor M to form a data point P-VSS as shown in fig. 6, the source of the control transistor M is connected to the ground line VSS, and the gate is connected to the signal control terminal control signal Program-Sig.

Taking 4 redundant memory cells shown in FIG. 5 as an example, Pro-WL [0] to Pro-WL [3] are redundant word lines connected to the redundant memory cells, when the redundant memory cells are all used to implement a sense amplifier, the redundant word lines can be connected to word line enable signals, so that the redundant word lines are in the same phase with the word lines WL, that is, any one of the word lines is turned on, the redundant word lines are all turned on, and at this time, the voltage difference between the bit line pair BL and BLB is introduced into the redundant memory cells; and, the signal control terminal of the control transistor connected to the redundant memory cell can receive a sense amplifier enable Signal (SAEN), i.e., Program-Sig is SAEN, so that the connected redundant word line of the redundant memory cell can be used as the word line of the sense amplifier.

Taking the 4 redundant memory cells shown in fig. 5 as an example, when part of the redundant memory cells in the redundant memory cells are used to replace the abnormal memory cells, the embodiment of the invention can reserve at least one redundant memory cell for implementing the sense amplifier, the redundant word line of the at least one redundant memory cell can be accessed to the word line enable signal so as to be in phase with the word line WL, and the signal control terminal of the connected control transistor can be accessed to SAEN;

the word line address of the word line connected with the abnormal memory cell is decoded and shifted, so that the redundancy word line connected with the target redundancy memory cell of the abnormal memory cell can be replaced by the word line of the abnormal memory cell; for example, one, two or three of Pro-WL [0] to Pro-WL [3] may be replaced with one, two or three of word lines WL [0] to WL [ n ] (the replaced word line may be a word line connected to an abnormal memory cell), and a control signal of a control transistor connected to the target redundant memory cell may be set to logic 1, so that the data point P-VSS in the target redundant memory cell may be always maintained to 0, and thus the connected redundant word line of the target redundant memory cell may be used as the word line of the memory cell;

for example, in the case of 4 redundant memory cells, up to 3 redundant memory cells can be used for replacing an abnormal memory cell, i.e. at least one redundant memory cell must be reserved for implementing a sense amplifier.

Alternatively, fig. 7 illustrates a connection diagram of a sense amplifier implemented by using redundant memory cells, for example, if 4 redundant memory cells Pro-WL [0] to Pro-WL [3] are all used to implement the sense amplifier, the redundant word lines Pro-WL connected to each of the redundant memory cells are all turned on, for example, the redundant word lines connected to each of the redundant memory cells are connected to a word line enable signal (WLEN), and the signal control terminals of the control transistors connected to the redundant memory cells are connected to a sense amplifier enable Signal (SAEN);

alternatively, fig. 8 shows a waveform diagram corresponding to fig. 7; as shown in fig. 5, fig. 6, fig. 7, and fig. 8, the sense amplifier is implemented by using the redundant memory cell, and the specific process may be as follows:

when the redundant word line connected with the redundant memory cell is opened, the word line WL [ n ] is selected (namely the word line connected with the tail end memory cell is selected), the memory cell starts to pull down the voltage of BL (taking the BL terminal voltage of a pull-up bit line pair as an example for explanation), and the voltage difference between BL and BLB is led into the redundant memory cell;

before WLEN and WL [ n ] are turned off, SAEN is turned on, and along with the turning on of SAEN, the signal control end of a control transistor connected with the redundant storage unit can be connected to SAEN, so that the data point P-VSS in the redundant storage unit is pulled down to 0, and at the moment, one redundant storage unit forms a latch, namely, one redundant storage unit can be regarded as a sensitive amplifier; through the voltage difference between the BL and the BLB and the unstable state of the redundant memory cell, the redundant memory cell can quickly pull down the voltage of the BL to 0; the stable BL and BLB may then have sufficient voltage difference (i.e., logic 0 and logic 1) to be provided for use by other circuits in the chip; here, the more redundant memory cells are used to implement the sense amplifier, the faster the voltage of BL is pulled down to 0, and the higher the performance of the sense amplifier.

Alternatively, FIG. 9 illustrates an alternative connection scheme for replacing an abnormal memory cell with a redundant memory cell, where the memory cell that is crossed in FIG. 9 needs to be replaced due to an abnormality (e.g., a defect); at this time, the word line WL connected to the abnormal memory cell can be set to logic 0, for example, Tie0 is set, so that the abnormal memory cell cannot be turned on; as shown in FIG. 9, the memory cells Cell [ n-1] and Cell [ n ] are damaged, and the word line connecting the memory cells Cell [ n-1] and Cell [ n ] is set to Tie 0;

the word line address of the word line connected with the abnormal memory cell can be decoded and shifted to corresponding number of redundant word lines, so that the target redundant memory cell connected with the redundant word line can replace the damaged memory cell; word line addresses such as word lines WL [ n-1] and WL [ n ] may be shifted by decoding to redundant word lines to which redundant memory cells Pro-Cell [0] and Pro-Cell [1] are connected;

the remaining redundant memory cells can be used to implement a sense amplifier; for example, Pro-Cell [2] and Pro-Cell [3] can be used to implement the sense amplifier, and the implementation and corresponding waveform schematic can be referred to the previous description, and will not be described in detail here.

It can be understood that at least one redundant memory cell must be reserved in the embodiment of the present invention to implement the sense amplifier, so that the embodiment of the present invention may further divide the redundant memory cells into replaceable redundant memory cells and non-replaceable redundant memory cells; wherein the replaceable redundant memory cell can be used to replace an abnormal memory cell, and the non-replaceable redundant memory cell can be used to implement a sense amplifier only;

optionally, the number of replaceable redundant memory units may be multiple, and the number of non-replaceable redundant memory units may be at least one; when the number of the abnormal storage units is larger than or equal to the number of the replaceable redundant storage units, the embodiment of the invention only uses the replaceable redundant storage units to replace the corresponding number of the abnormal storage units, and reserves the irreplaceable redundant storage units to realize the sense amplifier;

for example, in the case of setting 4 redundant memory cells, where 2 are replaceable redundant memory cells and the other 2 are non-replaceable redundant memory cells, if the abnormal memory cells are greater than or equal to 2, the embodiment of the present invention only uses 2 replaceable redundant memory cells to replace the 2 abnormal memory cells, and does not use 2 non-replaceable redundant memory cells to replace the abnormal memory cells, that is, at least 2 non-replaceable redundant memory cells are reserved to implement the sense amplifier; therefore, the embodiment of the invention can efficiently utilize the redundant memory unit to the maximum extent under the condition of keeping the function of the sensitive amplifier of the memory, and reduce the performance loss of the memory caused by the abnormity of the memory unit;

when the number of the abnormal storage units is smaller than the number of the replaceable redundant storage units, the replaceable redundant storage units corresponding to the number of the abnormal storage units can be used for replacing the abnormal storage units, and the remaining replaceable redundant storage units can be combined with the non-replaceable redundant storage units to realize the sense amplifier;

for example, in the case of setting 4 redundant memory cells, 2 of which are replaceable redundant memory cells and the other 2 of which are non-replaceable redundant memory cells, if the abnormal memory cell is 1, the embodiment of the present invention may replace the abnormal memory cell with 1 replaceable redundant memory cell, and implement the sense amplifier using the remaining 1 replaceable redundant memory cell and 2 non-replaceable redundant memory cells, so as to implement efficient utilization of the redundant memory cell.

As an optional implementation of the disclosure of the embodiment of the invention, the embodiment of the invention can control the redundant storage unit to replace the abnormal storage unit and control the redundant storage unit to realize the sense amplifier by setting the control circuit; optionally, fig. 10 is a schematic diagram illustrating another structure of the memory according to the embodiment of the present invention, and in combination with fig. 5 and fig. 10, the memory according to the embodiment of the present invention may further include: a control circuit 20;

the control circuit 20 may be connected to the word line WL of the memory Cell, the redundant word line Pro-WL of the redundant memory Cell Pro-Cell, and the signal control terminal of the control transistor; thereby, the control circuit 20 controls the redundant memory cell to replace the abnormal memory cell and controls the redundant memory cell to realize the sense amplifier.

Alternatively, in the case of implementing a sense amplifier by using a redundant memory cell, fig. 11 shows an optional flow of a circuit control method provided by the embodiment of the present invention, where the circuit control method can be implemented by a control circuit, and with reference to fig. 10 and fig. 11, the method can include:

step S100, when the abnormal memory cell does not exist, the redundant word line connected with the redundant memory cell is switched into a word line enabling signal.

Alternatively, the control circuit may input a word line enable signal WLEN to a redundancy word line to which the redundancy memory Cell is connected, so that the redundancy word line is turned on and is in phase with the word line to which the memory Cell is connected.

And step S110, connecting the signal control end of the control transistor connected with the redundant memory cell, and enabling a signal by the sensitive amplifier.

Alternatively, the control circuit may input the SAEN signal to the control transistor.

Optionally, the steps S100 and S110 may not be in sequence, or the sequence may be reversed.

Optionally, in a case where a redundant memory cell is used to replace an abnormal memory cell, fig. 12 shows a further optional flow of a circuit control method provided in an embodiment of the present invention, where the circuit control method may be implemented by a control circuit, and in conjunction with fig. 10 and 12, the method may include:

step S200, when an abnormal memory cell exists, setting a word line connected to the abnormal memory cell to logic 0.

After the word line connected with the abnormal memory cell is set to be logic 0, the abnormal memory cell cannot be opened; alternatively, a logic 0 may be considered as an alternative form of the second signal, the second signal may be a signal that is logically opposite to the first signal, the first signal may be a logic 1, the second signal may be a logic 0, the signal of the logic 1 referred to below may be considered as an alternative form of the first signal, and the signal of the logic 0 referred to below may be considered as an alternative form of the second signal; of course, the forms of the first signal and the second signal in the embodiment of the present invention are not limited thereto as long as the first signal and the second signal are logically opposite.

Step S210, shifting the word line address of the word line connected to the abnormal memory cell to the redundant word line connected to the target redundant memory cell by decoding, and setting the signal control terminal of the control transistor connected to the target redundant memory cell to logic 1.

Optionally, the steps S200 and S210 may not be in sequence, or the sequence may be reversed.

Optionally, the target redundant memory cell may be determined from the replaceable redundant memory cells, and how to select the target redundant memory cell may refer to the foregoing description of the replaceable redundant memory cells and the non-replaceable redundant memory cells, which is not described herein again;

through word line shift decoding, the embodiment of the invention can shift the word line address of the word line connected with the abnormal memory cell to the redundancy word line connected with the target redundancy memory cell, thereby replacing the abnormal memory cell with the target redundancy memory cell; and the signal control end of the control transistor connected with the target redundant memory cell is Tie1, and the SAEN signal is not accessed any more.

It is understood that, the non-replaceable redundant memory cell of the redundant memory cells can also implement a sense amplifier according to the method shown in fig. 11; when the number of replaceable redundant memory cells is greater than that of abnormal memory cells, the replaceable redundant memory cells not used for replacing the abnormal memory cells can be implemented together with the non-replaceable redundant memory cells according to the method shown in fig. 11.

In one alternative example, the control circuit may include: a decoding circuit for generating a word line decoding signal, a word line enable signal generating circuit for generating a word line enable signal, and a sense amplifier enable signal generating circuit for generating a sense amplifier enable signal; the control circuit can realize the connection of the decoding circuit, the word line enabling signal generating circuit and the sensitive amplifier enabling signal generating circuit with the word line, the redundant word line and the signal control end of the control transistor by arranging an AND gate and a multiplexer;

alternatively, fig. 13 is a schematic diagram of another structure of a memory provided in an embodiment of the present invention, and as shown in fig. 10 and 13, in the memory provided in the embodiment of the present invention, redundant memory cells may be divided into replaceable redundant memory cells (fig. 13 exemplarily shows the replaceable redundant memory cells as redundant memory cells Pro-Cell [0] and Pro-Cell [1]), and non-replaceable redundant memory cells (fig. 13 exemplarily shows the non-replaceable redundant memory cells as redundant memory cells Pro-Cell [2] and Pro-Cell [3 ]);

the control circuit 20 may include:

a decoding circuit 21, the decoding circuit 21 can decode the word line WL (e.g. decoding signals WLE 0 to WLE n) and the redundant word line Pro-WL connected with the non-replaceable redundant memory unit (e.g. decoding signals Pro-WLE 0 and Pro-WLE 1), so that when there is an abnormal memory unit, the word line address of the word line WL of the abnormal memory unit can be decoded and shifted to the redundant word line connected with the non-replaceable redundant memory unit; optionally, the decoding circuit 21 may select an X-direction decoder, and the X direction may be considered as a row direction of the memory;

a Word Line enable signal generating circuit 22 for generating a Word Line enable signal WLEN, such as a Word Line Clock (Word Line Clock Pulse), which is matched with the decoding circuit to select a Word Line from the Word lines WL [0] to WL [ n ];

a sense amplifier enable signal generation circuit 23 for generating a sense amplifier enable signal;

a two-input and gate 24;

a first two-way transmitter 25;

a second two-way transmitter 26.

With continued reference to fig. 13, the word line to which the memory cell is connected may be connected to the decoding circuit 21 and the word line enable signal generation circuit 22 via a two-input and gate 24 (a two-input and gate is only an alternative form of an and gate, and other types of and gates may be supported by embodiments of the present invention); specifically, the output end of the two-input and gate is connected to the word line of the memory Cell, the first input end is connected to the word line enable signal generation circuit 22 for receiving the word line enable signal (see WLEN as shown in the figure), and the second input end is connected to the decoding circuit for receiving the word line decoding signals (see WLE [0] to WLE [ n ]);

the redundant word lines, which can replace the redundant memory cells, can be connected to the decoding circuit 21 and the word line enable signal generation circuit 22 through a first two-way transmitter 25 (the two-way transmitter is only an alternative form of a multiplexer, and other types of multiplexers can be supported by the embodiment of the present invention); specifically, the output end of the first two-way transmitter is connected with the redundant word line of the replaceable redundant memory unit, the first input end (such as logic 0 input end) is connected with the word line enable signal generating circuit and is used for receiving the word line enable signal (WLEN as shown in the figure), and the second input end (such as logic 1 input end) is connected with the decoding circuit and is used for receiving the word line decoding signals (Pro-WLE [0] to Pro-WLE [1] as shown in the figure);

the signal control terminal of the transistor connected with the replaceable redundant memory cell can be connected with the decoding circuit 21 and the sensitive amplifier enabling signal generating circuit 23 through the second two-way transmitter 26; specifically, the output end of the second two-way transmitter 26 is connected to replace the signal control end of the transistor connected to the redundant memory cell, the first input end (e.g. logic 0 input end) is connected to the sense amplifier enable signal generating circuit 23 for receiving the SAEN signal, and the second input end (e.g. logic 1 input end) is connected to the decoding circuit 21 for receiving the Tie1 signal;

the redundancy word line of the non-replaceable redundancy memory unit is directly connected with the word line enable signal generating circuit 22 and used for receiving the word line enable signal, and the signal control end of the control transistor connected with the non-replaceable redundancy memory unit is directly connected with the sensitive amplifier enable signal generating circuit 23 and used for receiving the SAEN signal; therefore, the non-replaceable redundant storage unit can keep receiving the SAEN signal and the WLEN signal, and the replaceable redundant storage unit does not need to select signals through the first two-way transmitter and the second two-way transmitter, so that the embodiment of the invention can keep the non-replaceable redundant storage unit to realize the sensitive amplifier.

Based on the memory shown in fig. 13, when there is no abnormal memory cell, the method flow of using the redundant memory cell to implement the sense amplifier can be shown in fig. 14, the corresponding signal trend can be shown with reference to fig. 15, and the dashed line of fig. 15 shows the signal trend; referring to fig. 13, 14 and 15, the method may include:

in step S300, the first two-way transmitter selects the word line enable signal input from the first input terminal.

Optionally, each first two-way transmitter may select the logic 0 input terminal, and then the word line enable signal is introduced into the redundant word line connected to the non-replaceable redundant memory cell.

In step S310, the second two-way transmitter selects the SAEN signal input from the first input terminal.

Optionally, each second transmitter may select a logic 0 input terminal, and the SAEN signal may be led to a signal control terminal of a control transistor connected to the non-replaceable redundant memory cell, so that the signal control terminal of the control transistor is controlled by the SAEN signal.

As can be seen from FIG. 15, when there are no abnormal memory cells, the redundant memory cells Pro-Cell [0] to Pro-Cell [3] implement sense amplifiers, the signal control terminal of the connected control transistor M is connected to the SAEN signal, and the redundant word lines connected to the redundant memory cells Pro-Cell [0] to Pro-Cell [1] can be replaced to be connected to WLEN; in this case, the Cell Cel [ n ] is selected (i.e., the end Cell at this time is selected), and then the voltages of BL and BLB are pulled down, and Pro-Cell [0] to Pro-Cell [3] are used as SA, and signals are amplified and outputted.

Based on the memory shown in FIG. 13, when an abnormal memory cell exists, the flow of the method for replacing the abnormal memory cell by the replaceable redundant memory cell can be shown in FIG. 16, the corresponding signal trend can be shown with reference to FIG. 17, and the signal trend is shown by the dashed line in FIG. 17; referring to fig. 13, 16 and 17, the method may include:

in step S400, the decoding circuit decodes and shifts the word line address of the word line connected to the damaged memory cell to the redundancy word line connected to the target redundancy memory cell.

As shown in FIG. 17, if the memory cells Cell [ n-1] and Cell [ n ] are abnormal, the word line address of the connected word line WL [ n-1] of the memory Cell Cell [ n-1] can be decoded and shifted to the redundant word line Pro-WL [0], as shown by the connection of WLE [ n-1] to Pro-WLE [0], and the word line address of the word line WL [ n ] of the memory Cell Cell [ n ] can be decoded and shifted to the redundant word line Pro-WL [1], as shown by the connection of WLE [ n ] to Pro-WLE [1 ].

Optionally, the word line to which the defective memory cell is connected may also be set to Tie 0.

Step S410, the first two-way transmitter of the target redundant memory cell selects the second input terminal, and introduces a word line decoding signal to the redundant word line of the target redundant memory cell.

As shown in fig. 17, the first two-way transmitter of the target redundant memory cell may select the logic 1 input terminal.

And step S420, selecting a second input end by a second two-way transmitter of the target redundant storage unit, and setting a signal control end of a control transistor connected with the target redundant storage unit to be logic 1.

As shown in FIG. 17, the second router of the target redundant memory cell selects the logic 1 input.

As can be seen from FIG. 17, when two memory cells Cell [ n-1] and Cell [ n ] are damaged, redundant memory cells Pro-Cell [0] and Pro-Cell [1] can be replaced as target redundant memory cells for replacing memory cells Cell [ n-1] and Cell [ n ], and then the signal control terminal of the control transistor M connected to Pro-Cell [0] and Pro-Cell [1] is set to Tie1 (meanwhile, the word line connected to Cell [ n-1] and Cell [ n ] can also be set to Tie0), while the redundant memory cells Pro-Cell [2] and Pro-Cell [3] cannot be replaced to realize a sense amplifier. In this case, the redundant memory Cell Pro-Cell [1] is selected (i.e., the end memory Cell at this time is selected), and then the voltages of BL and BLB are pulled down, Pro-Cell [2] and Pro-Cell [3] are used as SA, and the signal is amplified and outputted.

It should be noted that the placement position of the control transistor is not limited to that shown in the above figures, and may be arranged outside the memory cell array and connected to the redundant memory cell; optionally, the closer the control transistor is to the connected redundant memory cell, the better the control effect of the control transistor is.

Optionally, although the foregoing examples take BL and BLB scenarios as examples for signal amplification output, such a scenario of double-ended amplification output is only an optional example of the embodiment of the present invention, and the embodiment of the present invention may also be applied to a single-ended output circuit, where the single-ended output circuit may perform logic output through one BL or BLB.

Optionally, in order to improve the speed and efficiency of the memory, the embodiment of the present invention may also perform boosting processing on the voltage of the WLEN accessing the redundant word line, which may be shown as the waveform in fig. 18.

Optionally, in order to improve the speed and efficiency of the memory, in the redundant memory cell, the embodiment of the present invention may also connect the data node Q and the bit line BL in the redundant memory cell with a 6T structure, and connect the data node QB and the inverted bit line BLB, as shown in fig. 19.

The memory structure provided by the embodiment of the invention can realize the sense amplifier by the redundant memory unit, thereby omitting the circuit structure of the traditional sense amplifier in the memory, realizing the sense amplifier by the redundant memory unit with smaller area, replacing the abnormal memory unit by part of the redundant memory unit, improving the area ratio occupied by the memory unit in the memory, reducing the area consumption of the memory and realizing the efficient utilization of the area of the memory on the basis of effectively utilizing the redundant memory unit.

As an optional implementation, an embodiment of the present invention further provides a chip, where the chip may include the memory provided in the foregoing embodiment of the present invention.

As an optional implementation, the embodiment of the present invention may further provide a corresponding circuit control method for the provided memory, and the corresponding method content may refer to the foregoing description, which is not repeated herein.

While various embodiments of the present invention have been described above, various alternatives described in the various embodiments can be combined and cross-referenced without conflict to extend the variety of possible embodiments that can be considered disclosed and disclosed in connection with the embodiments of the present invention.

Although the embodiments of the present invention have been disclosed, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A memory, comprising:

a word line;

a redundant word line;

memory cells connected to the word lines;

redundant memory cells connected to the redundant word lines;

2. The memory of claim 1, further comprising: a control transistor connected to the redundant memory cell;

3. The memory of claim 2, further comprising: a control circuit; the control circuit is connected with the word lines, the redundant word lines and the signal control ends of the control transistors;

4. The memory of claim 3, wherein the control circuit is further configured to:

5. The memory of claim 4, wherein the control circuit comprises: the device comprises a decoding circuit for generating a word line decoding signal, a word line enabling signal generating circuit for generating a word line enabling signal, a sensitive amplifier enabling signal generating circuit for generating a sensitive amplifier enabling signal, an AND gate, a first multiplexer and a second multiplexer;

6. The memory of claim 5, wherein the AND gate is a two-input AND gate; the first input end of the two-input AND gate is connected with the word line enabling signal generating circuit, the second input end of the two-input AND gate is connected with the decoding circuit, and the output end of the two-input AND gate is connected with a word line connected with the storage unit;

7. The memory according to claim 6, wherein the first two-way transmitter is configured to select the word line enable signal input from the first input terminal when there is no abnormal memory cell; when an abnormal memory cell exists, selecting a second input terminal to introduce a word line decoding signal to the redundant word line;

8. The memory according to claim 2, wherein the control transistor is an NMOS transistor; the grid electrode of the control transistor is a control signal end, the drain electrode of the control transistor is connected with the redundant storage unit, and the source electrode of the control transistor is grounded.

9. The memory of claim 8, wherein the redundant memory cell comprises:

10. The memory of claim 1, further comprising:

11. A chip, comprising: the memory of any one of claims 1-10.

12. A circuit control method, based on the memory according to any one of claims 1 to 10, the method comprising:

13. The circuit control method of claim 12, wherein implementing the sense amplifier using the redundant memory cell comprises:

14. The circuit control method of claim 13, wherein implementing the sense amplifier using the redundant memory cell further comprises:

the method further comprises the following steps:

15. The circuit control method according to claim 13, wherein the redundant memory cell comprises: replaceable redundant memory cells and non-replaceable redundant memory cells; determining a target redundant memory cell from the replaceable redundant memory cells;