CN110070904A - A kind of memory, chip and circuit control method - Google Patents
A kind of memory, chip and circuit control method Download PDFInfo
- Publication number
- CN110070904A CN110070904A CN201910314248.8A CN201910314248A CN110070904A CN 110070904 A CN110070904 A CN 110070904A CN 201910314248 A CN201910314248 A CN 201910314248A CN 110070904 A CN110070904 A CN 110070904A
- Authority
- CN
- China
- Prior art keywords
- storage unit
- redundant
- signal
- wordline
- word line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015654 memory Effects 0.000 title claims abstract description 114
- 238000000034 method Methods 0.000 title claims abstract description 34
- 230000002159 abnormal effect Effects 0.000 claims abstract description 109
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 30
- 230000008676 import Effects 0.000 claims description 8
- 230000005611 electricity Effects 0.000 claims description 4
- 230000008859 change Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 25
- 230000003321 amplification Effects 0.000 description 8
- 238000003199 nucleic acid amplification method Methods 0.000 description 8
- 230000006870 function Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000012163 sequencing technique Methods 0.000 description 4
- 208000000044 Amnesia Diseases 0.000 description 3
- 101100481404 Danio rerio tie1 gene Proteins 0.000 description 3
- 101100481406 Mus musculus Tie1 gene Proteins 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 231100000863 loss of memory Toxicity 0.000 description 3
- 230000007334 memory performance Effects 0.000 description 3
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
It includes: wordline that the embodiment of the present invention, which provides a kind of memory, chip and circuit control method, memory,；Redundant word line；Connect the storage unit of the wordline；Connect the redundant storage unit of the redundant word line；Wherein, when there is no abnormal storage unit, sense amplifier is realized using the redundant storage unit；When there is abnormal storage unit, retaining at least one redundant storage unit and realizing sense amplifier, and replacing abnormal storage unit using remaining target redundancy storage unit.The embodiment of the present invention can improve area ratio shared by storage unit in memory, reduce the area consumption of memory on the basis of efficiently using redundant storage unit.
Description
Technical field
The present embodiments relate to memory technology fields, and in particular to a kind of memory, chip and circuit control method.
Background technique
Memory is the device of widely applied storing data in chip, particularly, SRAM (Static Random-
Access Memory, static random access memory) as a kind of typical memory, since its small power consumption, reading speed are fast etc. excellent
Point is more widely applied in the chips.
Basic structure of the storage unit as memory, the storage unit that memory is generally made up of multiple storage units
Array carrys out storing data；In the design of memory, storage is influenced to avoid storage unit abnormal (such as storage unit damage)
The storage performance of device, memory is generally also devised with redundant storage unit in addition to design has storage unit, so as in storage unit
When abnormal, the abnormal storage unit of redundant storage unit replacement can be used, the performance loss of memory is reduced with this；However,
If the storage unit in memory is without abnormal, redundant storage unit will become useless, it is seen then that redundant storage unit is existing
It is not used effectively in technology, this wastes the area of memory to a certain extent.
Summary of the invention
In view of this, the embodiment of the present invention provides a kind of memory, chip and circuit control method, to efficiently use redundancy
Storage unit realizes the efficient utilization of memory area.
To achieve the above object, the embodiment of the present invention provides the following technical solutions:
A kind of memory, comprising:
Wordline；
Redundant word line；
Connect the storage unit of the wordline；
Connect the redundant storage unit of the redundant word line；
Wherein, when there is no abnormal storage unit, sense amplifier is realized using the redundant storage unit；When depositing
In abnormal storage unit, retains at least one redundant storage unit and realize sense amplifier, and is superfluous using remaining target
The abnormal storage unit of balance storage unit replacement.
Optionally, the memory further include: connect the control transistor of the redundant storage unit；
Wherein, if the enabled letter of signal control terminal access sense amplifier of the control transistor of redundant storage unit connection
Number, the redundant storage unit is for realizing sense amplifier；If the signal control of the control transistor of redundant storage unit connection
System is terminated into the first signal, and the redundant storage unit is for replacing abnormal storage unit.
Optionally, the memory further include: control circuit；The control circuit connects the wordline, the redundancy word
The signal control terminal of line and the control transistor；
The control circuit, the control for when there is no abnormal storage unit, the redundant storage unit to be connected
The signal control terminal of transistor processed accesses sense amplifier enable signal；
When there is abnormal storage unit, the signal control for the control transistor that at least one redundant storage unit is connected
Sense amplifier enable signal is accessed at end processed；By the wordline address of the wordline of abnormal storage unit connection, shifted by decoding
The redundant word line connected to target redundancy storage unit, and the signal for controlling transistor that target redundancy storage unit is connected
Control terminal accesses the first signal.
Optionally, the control circuit is also used to:
When there is no abnormal storage unit, the redundant word line access wordline that the redundant storage unit connects is enabled
Signal；
When there is abnormal storage unit, the redundant word line of at least one described redundant storage unit connection is accessed into word
Line enable signal, and the wordline of abnormal storage unit connection is set to second signal, the first signal and second signal are logic
Opposite signal.
Optionally, the control circuit includes: the decoding circuit for generating word line decoding signal, generates wordline enable signal
Wordline enable signal generation circuit, generates the sense amplifier enable signal generation circuit of sense amplifier enable signal, and door,
First multiplexer and the second multiplexer；
The redundant storage unit includes: replaceable redundant storage unit and can not replacement redundancy storage unit；Target is superfluous
Balance storage unit is determined from the replaceable redundant storage unit；
The decoding circuit and the wordline enable signal generation circuit are by with door, the wordline phase connecting with storage unit
Connection；
The decoding circuit and the wordline enable signal generation circuit are by the first multiplexer, with replaceable redundancy
The redundant word line of storage unit connection is connected；
The decoding circuit and the sense amplifier enable signal generation circuit and can be replaced by the second multiplexer
The signal control terminal for changing the control transistor of redundant storage unit connection is connected；
It is described can not replacement redundancy storage unit connection redundant word line, directly with the wordline enable signal generation circuit
Connection；It is described can not replacement redundancy storage unit connection control transistor signal control terminal, directly make with sense amplifier
Energy signal generating circuit is connected.
Optionally, described and door is two inputs and door；Two input and the first input end of door and the wordline are enabled
Signal generating circuit connection, the second input terminal are connected with the decoding circuit, the wordline phase that output end is connect with storage unit
Connection；
First multiplexer is the one or two road transmitter；The first input end of one or the two road transmitter and institute
The connection of wordline enable signal generation circuit is stated, the second input terminal is connected with the decoding circuit, output end and replaceable redundancy
The redundant word line of storage unit connection is connected；
Second multiplexer is the two or two road transmitter, the first input end of the two or the two road transmitter and spirit
Quick amplifier enable signal generation circuit connection, the second input terminal is connected with the decoding circuit, defeated to receive the first signal
The signal control terminal for the control transistor that outlet is connect with replaceable redundant storage unit is connected.
Optionally, the one or the two road transmitter, for selecting first input end when not there is no abnormal storage unit
The wordline enable signal of input；When there is abnormal storage unit, the second input terminal is selected, to import wordline to redundant word line
Decoded signal；
Two or the two road transmitter, for when not there is no abnormal storage unit, selecting first input end input
SAEN signal；When there is abnormal storage unit, the second input terminal is selected, with the letter of the control transistor connected to output end
Number control terminal imports the first signal；
The decoding circuit is used for, when there is abnormal storage unit, by the wordline of abnormal storage unit connection
Wordline address, by decoding the redundant word line for being displaced to target redundancy storage unit and being connected.
Optionally, the control transistor is NMOS tube；The grid of the control transistor is control signal end, and drain electrode connects
Connect the redundant storage unit, source electrode ground connection.
Optionally, the redundant storage unit includes:
First PMOS tube P1, the first NMOS tube N1, the second PMOS tube P2, the second NMOS tube N2, third NMOS tube N3 and
Four NMOS tube N4；
The grid of first PMOS tube P1, the grid of the first NMOS tube N1, the drain electrode of the second PMOS tube P2, the second NMOS tube N2
Drain electrode connected with the source electrode of third NMOS tube N3, formed back end Q；The grid of second PMOS tube P2, the second NMOS tube N2
Grid, the drain electrode of the first PMOS tube P1, the drain electrode of the first NMOS tube N1, the 4th NMOS tube N4 source electrode connection, formed data
Node QB；
The grid of third NMOS tube N3 and the 4th NMOS tube N4 are connect with wordline WL, the drain electrode of third NMOS tube N3 and bit line
BL connection, the drain electrode of the 4th NMOS tube N4 are connect with bit line BLB；The source electrode of the source electrode of first PMOS tube P1 and the second PMOS tube P2
It is connect with supply voltage VDD；The leakage of the source electrode of the source electrode of first NMOS tube N1 and the second NMOS tube N2 and the control transistor
Pole connection.
Optionally, the memory further include:
The multipair bit line pair being connected in parallel with the wordline and redundant word line.
The embodiment of the present invention also provides a kind of chip, comprising: memory described above.
The embodiment of the present invention also provides a kind of circuit control method, based on memory described above, which comprises
When there is no when the storage unit of exception, use redundant storage unit realization sense amplifier in memory；
When there is abnormal storage unit in memory, retaining at least one redundant storage unit and realizing sensitive amplification
Device, and abnormal storage unit is replaced using remaining target redundancy storage unit.
Optionally, described to realize that sense amplifier includes: using redundant storage unit
By the signal control terminal of the control transistor of redundant storage unit connection, sense amplifier enable signal is accessed；
It is described to replace abnormal storage unit using remaining target redundancy storage unit and include:
By the wordline address of the wordline of abnormal storage unit connection, target redundancy storage unit institute is displaced to by decoding
The redundant word line of connection, and the signal control terminal for the control transistor that target redundancy storage unit connects is accessed into the first signal.
It is optionally, described to realize sense amplifier using redundant storage unit further include:
The redundant word line of redundant storage unit connection is accessed into wordline enable signal；
The method also includes:
When there is abnormal storage unit in memory, the wordline of abnormal storage unit connection is set to the second letter
Number, the first signal and second signal are the opposite signal of logic.
Optionally, the redundant storage unit includes: replaceable redundant storage unit and can not replacement redundancy storage unit；
Target redundancy storage unit is determined from the replaceable redundant storage unit；
It is described to include: by the redundant word line access wordline enable signal of redundant storage unit connection
The wordline enable signal for selecting the first input end of the one or two road transmitter to access, the one or the two road transmitter
First input end accesses wordline enable signal, and the second input terminal accesses word line decoding signal, and output end connects replaceable redundancy and deposits
The redundant word line of storage unit；
The signal control terminal of the control transistor by redundant storage unit connection, accesses sense amplifier enable signal
Include:
The sense amplifier enable signal for selecting the first input end of the two or two road transmitter to access, the two or two tunnel pass
The first input end of defeated device accesses sense amplifier enable signal, and the second input terminal accesses the first signal, and output end connection can be replaced
Change the signal control terminal of the control transistor of redundant storage unit.
Memory provided in an embodiment of the present invention can use redundant storage list when there is no abnormal storage unit
Member realizes sense amplifier, and when avoiding storage unit not abnormal, the useless situation of redundant storage unit realizes redundant storage unit
It is efficient using and memory sense amplifier function realization；Meanwhile when there is abnormal storage unit, can retain to
A few redundant storage unit realizes sense amplifier, and remaining target redundancy storage unit can be used for replacing abnormal storage
Unit reduces memory performance loss when storage unit exception；Since the area of storage unit is compared to the sensitive amplification of tradition
Device is smaller, and the embodiment of the present invention can improve in memory shared by storage unit on the basis of efficiently using redundant storage unit
Area ratio, reduce the area consumption of memory.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of application for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is the structural schematic diagram of the memory of traditional design；
Fig. 2 is the structural schematic diagram of memory provided in an embodiment of the present invention；
Fig. 3 is the structural schematic diagram of storage unit；
Fig. 4 is the structural schematic diagram of traditional sense amplifier；
Fig. 5 is another structural schematic diagram of memory provided in an embodiment of the present invention；
Fig. 6 is redundant storage unit and the attachment structure schematic diagram for controlling transistor；
Fig. 7 is the connection schematic diagram that sense amplifier is realized using redundant storage unit；
Fig. 8 is waveform diagram；
Fig. 9 is the connection schematic diagram that abnormal storage unit is replaced using redundant storage unit；
Figure 10 is another structural schematic diagram of memory provided in an embodiment of the present invention；
Figure 11 is a flow chart of circuit control method provided in an embodiment of the present invention；
Figure 12 is another flow chart of circuit control method provided in an embodiment of the present invention；
Figure 13 is the another structural schematic diagram of memory provided in an embodiment of the present invention；
Figure 14 is the method flow diagram that sense amplifier is realized using redundant storage unit；
Figure 15 is the structural schematic diagram of the memory moved towards with signal；
Figure 16 is the method flow diagram that abnormal storage unit is replaced using replaceable redundant storage unit；
Figure 17 is another structural schematic diagram of the memory moved towards with signal；
Figure 18 is another waveform diagram；
Figure 19 is the structural schematic diagram of redundant storage unit.
Specific embodiment
Optionally, Fig. 1 shows the structural schematic diagram of the memory of traditional design, and memory is generally arranged as by storing
The matrix structure of the rows and columns of unit composition, therefore memory can have multiple memory cell arrays, each storage unit battle array
Column can have multiple storage units；
Referring to Fig.1, reservoir designs have bit line to (BL and BLB), wordline (Word Line, WL), redundant word line (with
Red-WL is indicated), storage unit (is indicated) with Cell, and (Red-Cell, Red-Cell can be redundant storage unit
Redundancy Cell's writes a Chinese character in simplified form) and sense amplifier (being indicated with SA)；SA connection data-out port (Data Output,
DO)；
Wherein, the English spelling of BL is Bit Line, indicates bit line；Bit line is to can be the opposite bit line BL of logic and anti-
Bit line BLB is constituted；The quantity of bit line pair can be multipair, the quantity of wordline can be it is a plurality of, the quantity of redundant word line can also be with
To be a plurality of, bit line is to can and be connected in wordline and redundant word line；
Exemplary, Fig. 1 is illustrated with a pair of bit lines pair, n+1 root wordline and 2 redundant word lines, i.e., a pair of bit lines is to simultaneously
It is connected in n+1 root wordline and 2 redundant word lines, n+1 root wordline is WL [0] to WL [n] respectively, and 2 redundant word lines are respectively
The quantity of Red-WL [0] and Red-WL [1], n can be set according to the actual design situation of memory, not office of the embodiment of the present invention
Limit；Fig. 1 illustrates only a pair of bit lines pair for the purpose convenient for signal, may exist multipair bit line pair in actual design；
The quantity of storage unit can be multiple, the quantity of redundant storage unit may be it is multiple, Fig. 1 shows 2
The case where redundant storage unit is only a kind of signal.
Memory based on traditional design can replace exception by redundant storage unit when storage unit occurs abnormal
Storage unit reduces the performance loss of memory in storage unit exception.
As can be seen that memory has storage unit for storing data except design, also in the memory of traditional design
Design has the redundant storage unit that abnormal storage unit is replaced in storage unit exception, meanwhile, memory is also devised with spirit
Quick amplifier；However, redundant storage unit can only be used effectively in storage unit exception, when storage unit do not occur it is different
Chang Shi, redundant storage unit will become useless, this simultaneously cannot achieve the effective use of redundant storage unit；Meanwhile memory
Sense amplifier consumes the area of memory very much；Therefore, the effective use of redundant storage unit in memory how is realized, and
The area consumption for reducing memory realizes that the area efficient of memory utilizes, it is in need of consideration to become those skilled in the art
Problem.
Based on this, the embodiment of the present invention, to realize effective use redundant storage unit, improves storage by improving memory
Area ratio shared by storage unit in device, reduces the area consumption of memory, realizes that the area efficient of memory utilizes；Below will
In conjunction with the attached drawing in the embodiment of the present invention, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that
Described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Based on the implementation in the present invention
Example, every other embodiment obtained by those of ordinary skill in the art without making creative efforts belong to
The scope of protection of the invention.
As a kind of optional realization of disclosure of the embodiment of the present invention, deposited Fig. 2 shows provided in an embodiment of the present invention
The structural schematic diagram of reservoir, referring to Fig. 2, memory provided in an embodiment of the present invention may include:
Wordline (is indicated) with WL；The quantity of wordline can be more, exemplary, and with n+1 root wordline, (WL [0] arrives WL to Fig. 2
[n]) to be illustrated, the quantity of n can be determined according to actual design situation；
Redundant word line (is indicated) with Pro-WL；The quantity of redundant word line can be more, and exemplary, Fig. 2 is superfluous to be arranged 4
Remaining wordline (Pro-WL [0] to Pro-WL [3]) is illustrated, and certainly, the quantity of redundant word line shown in Fig. 2 is only exemplary
, the embodiment of the present invention does not limit to the quantity of redundant word line, and the quantity of redundant word line can be determined according to actual design situation；
The bit line being connected in parallel with wordline and redundant word line is to (BL and BLB)；The quantity of bit line pair can be multipair, be just
In signal, Fig. 2 illustrates only a pair of bit lines pair；
Storage unit (is indicated) with Cell；The quantity of storage unit can be to be multiple, and storage unit can connect wordline；Example
, it is to connect a wordline with a storage unit to be illustrated shown in Fig. 2, as storage unit is divided into Cell [0] to Cell
[n], Cell [0] connection WL [0], Cell [1] connection WL [1], and so on；Obviously, storage unit and wordline shown in Fig. 2
Connection signal is only a kind of optional example, and the embodiment of the present invention can also support other of storage unit and wordline connection type, only
Each storage unit is made to be matched with the wordline of connection；
Redundant storage unit (is indicated) with Pro-Cell；The quantity of redundant storage unit can be multiple, redundant storage list
Member can connect redundant word line；It is exemplary, it is to connect a redundant word line with a redundant storage unit to be illustrated shown in Fig. 2,
If redundant storage unit can be divided into Pro-Cell [0] to Pro-Cell [3],
Pro-Cell [0] connection Pro-WL [0], Pro-Cell [1] connection Pro-WL [1], and so on；Obviously, Fig. 2 institute
The connection signal of the redundant storage unit and redundant word line that show is only a kind of optional example, and the embodiment of the present invention can also support redundancy
Other of storage unit and redundant word line connection type, as long as each redundant storage unit is made to match the redundancy connected
Wordline.
Memory provided in an embodiment of the present invention does not design traditional sense amplifier, in embodiments of the present invention, spirit
Quick amplifier can be realized by redundant storage unit；Specifically, (as there is no damage when there is no abnormal storage unit
Storage unit), redundant storage unit can be used to realize sense amplifier for the embodiment of the present invention, and exemplary, Fig. 2 is illustrated with Pro-
Cell [0] realizes the example of sense amplifier to Pro-Cell [3]；
And when there is abnormal storage unit, the embodiment of the present invention can retain at least one redundant storage unit and realize spirit
(there are sense amplifiers to make in memory, and so as to realize data amplification output, the embodiment of the present invention is needed for quick amplifier
Retain minimum of one redundant storage unit to realize sense amplifier), and remaining redundant storage unit can be used for replacing exception
Storage unit；For purposes of illustration only, the embodiment of the present invention will can be used to replace remaining redundant storage list of abnormal storage unit
Member is known as, target redundancy storage unit.
It is understood that the area of traditional sense amplifier is larger, if designed in memory traditional sensitive
Amplifier will extremely consume the area of memory, and the structure of redundant storage unit can be consistent with storage unit, is deposited using redundancy
Storage unit is realized and on the one hand can effectively improve storage unit by sense amplifier shared area ratio is (i.e. identical in memory
The memory of area can be laid out more storage units, that is to say, that under the quantity of same memory cell, the face of memory
Product can be smaller), the area consumption of memory is reduced, on the other hand, in embodiments of the present invention, redundant storage unit can be with
For replacing abnormal storage unit, when there is abnormal storage unit, the performance loss of memory is reduced；
Memory provided in an embodiment of the present invention can use redundant storage list when there is no abnormal storage unit
Member realizes sense amplifier, and when avoiding storage unit not abnormal, the useless situation of redundant storage unit realizes redundant storage unit
It is efficient using and memory sense amplifier function realization；Meanwhile when there is abnormal storage unit, can retain to
A few redundant storage unit realizes sense amplifier, and remaining target redundancy storage unit can be used for replacing abnormal storage
Unit reduces memory performance loss when storage unit exception；Since the area of storage unit is compared to the sensitive amplification of tradition
Device is smaller, and the embodiment of the present invention can improve in memory shared by storage unit on the basis of efficiently using redundant storage unit
Area ratio, reduce the area consumption of memory.
For ease of understanding, the structure of a kind of optional traditional sense amplifier and storage unit is carried out below illustrative
Explanation；Optionally, Fig. 3 shows a kind of alternative construction of storage unit, and structure shown in Fig. 3 can be adapted for storage shown in Fig. 2
Unit Cell is equally applicable to redundant storage unit Pro-Cell；It is exemplary, (especially SRAM memory in memory
In), redundant storage unit and storage unit can be selected 6T structure and realize (constituting storage unit by the structure of 6 metal-oxide-semiconductors)；It is superfluous
Balance storage unit uses 6T structure, can reduce the area of redundant storage unit, and makes redundant storage unit and storage single
Member can be with seamless connection；
As shown in figure 3, the storage unit of 6T structure may include:
First PMOS tube P1, the first NMOS tube N1, the second PMOS tube P2, the second NMOS tube N2, third NMOS tube N3 and
Four NMOS tube N4；
First PMOS tube P1 and the first NMOS tube N1 constitutes a phase inverter, and the second PMOS tube P2 and the second NMOS tube N2 are constituted
Another phase inverter, third NMOS tube N3 are the access pipe of back end Q, and the 4th NMOS tube N4 is the access pipe of back end QB,
To which two phase inverters constitute the data latches of stable state；
In specific connection, the leakage of the grid of the first PMOS tube P1, the grid of the first NMOS tube N1, the second PMOS tube P2
The drain electrode of pole, the second NMOS tube N2 is connected with the source electrode of third NMOS tube N3, forms back end Q；The grid of second PMOS tube P2
Pole, the grid of the second NMOS tube N2, the drain electrode of the first PMOS tube P1, the drain electrode of the first NMOS tube N1, the 4th NMOS tube N4 source
Pole connection, forms back end QB；
The grid of third NMOS tube N3 and the 4th NMOS tube N4 are connect (if redundant storage unit, shown in Fig. 3 with wordline WL
Wordline WL can be replaced redundant word line Pro-WL), the drain electrode of third NMOS tube N3 is connect with bit line BL, the 4th NMOS tube N4's
Drain electrode is connect with antiposition line BLB；The source electrode of the source electrode of first PMOS tube P1 and the second PMOS tube P2 are connect with supply voltage VDD；
The source electrode of the source electrode of first NMOS tube N1 and the second NMOS tube N2 are connect with ground wire VSS.
Optionally, Fig. 4 shows a kind of alternative construction of traditional sense amplifier, as shown in figure 4, traditional sense amplifier
Before a read operation, back end Q and QB can be charged to supply voltage VDD by charging circuit 101；When reading and writing beginning, charging
Circuit 101 is hung up, and the voltage of bit line BL is pulled down by storage unit part, and is transmitted to back end Q by PMOS tube 104；When
After sense amplifier enable signal (SAEN) starting, NMOS tube 103 is opened, and PMOS tube 104 and 105 turns off；When SAEN is
When logic 1, the voltage of signal P-VSS pulled down to 0, and latch 102 continues the voltage of back end Q to be pulled down to 0 (example at this time
If supply voltage VDD is 1V, the voltage of back end Q has pulled down to 0.8V, then latch 102 can continue to pull down back end
The voltage of Q is to 0), to reach voltage amplification effect, and by output circuits (output circuit) by data export to
Data output end DO.
In conjunction with Fig. 3 and Fig. 4, it can be seen that traditional sense amplifier is the circuit for consuming very much memory area, especially
, when the quantity of multiplexer (MUX) is smaller, traditional sense amplifier more consumes memory area；Therefore, this hair
The sense amplifier of bright embodiment abandoning tradition in memory, and sense amplifier is realized by redundant storage unit, so as to
The area of memory consumption can be greatly reduced.
As a kind of optional realization, the embodiment of the present invention can control transistor in the external connection of redundant storage unit, lead to
The access signal for crossing the signal control terminal of control transistor, the wordline for managing redundant storage unit is wordline as storage unit
Using or the wordline of sense amplifier use, to realize redundant storage unit in the abnormal storage unit of replacement and realize sensitive
Switch between the effect of amplifier, saves memory area to reach and the function of replacement abnormal memory cell is provided；
Optionally, if the enabled letter of signal control terminal access sense amplifier of the control transistor of redundant storage unit connection
Number, the redundant storage unit is for realizing sense amplifier；If the signal control of the control transistor of redundant storage unit connection
It terminates into the first signal (optional, the first signal such as logic 1), the redundant storage unit is for replacing abnormal storage unit.
Optionally, Fig. 5 shows another structural schematic diagram of memory provided in an embodiment of the present invention, in conjunction with Fig. 2 and Fig. 5
It is shown:
In Fig. 5, redundant storage unit can also connect control transistor M, such as Pro-Cell in addition to connecting redundant word line
[0] M [0] is connected, Pro-Cell [1] connection M [1], and so on；It should be noted that control transistor it is optional be not provided in
In memory cell array, but it is set to the outside of storage unit, by the external control transistor of redundant storage unit, this is because
Memory cell array may be not extra space for arranging control transistor M, meanwhile, redundant storage unit external control crystalline substance
Body pipe can reduce the change to memory cell array；
It is exemplary, transistor is controlled in Fig. 5 and is illustrated by taking NMOS tube as an example, controls the grid of transistor as signal control
End, for incoming control signal, (Program-Sig can indicate control signal, such as M [0] access Program-Sig [0], M
[1] Program-Sig [1] is accessed, and so on), drain electrode connection redundant storage unit, source electrode ground connection.
It is exemplary, to control transistor as NMOS tube, for redundant storage unit uses 6T structure, optional show as a kind of
Example, Fig. 6 shows redundant storage unit and controls a kind of optional connection structure of transistor, in conjunction with shown in Fig. 3 and Fig. 6, redundancy
The source electrode of first NMOS tube N1 of storage unit and the source electrode of the second NMOS tube N2 are no longer grounded VSS, but it is brilliant to access control
The drain electrode of body pipe M forms data point P-VSS as shown in Figure 6, and the source electrode of control transistor M is grounded VSS, and grid is signal control
Termination control signal Program-Sig processed.
Illustrate for 4 redundant storage units shown in Fig. 5, Pro-WL [0] to Pro-WL [3] is to be connected to redundant storage
The redundant word line of unit may make redundant word line access wordline to make when redundant storage unit is used to realize sense amplifier
Energy signal, so that redundant word line and wordline WL same-phase, that is, open any wordline, then redundant word line can be opened, at this point,
Bit line will imported into redundant storage unit to the voltage difference of BL and BLB；Also, the control transistor of redundant storage unit connection
Signal control terminal can access sense amplifier enable signal (SAEN), i.e. Program-Sig is SAEN, thus redundant storage unit
Connection redundant word line can be used as sense amplifier wordline use.
For 4 redundant storage units shown in Fig. 5, when the partial redundance storage unit in redundant storage unit is for replacing
When the normal storage unit of transversion, the embodiment of the present invention can retain at least one redundant storage unit for realizing sense amplifier,
The redundant word line of at least one redundant storage unit can access wordline enable signal, with wordline WL same-phase, and connect
The signal control terminal for controlling transistor can access SAEN；
Decoding displacement is carried out by the wordline address of the wordline to abnormal storage unit connection, for replacing abnormal deposit
The redundant word line that the target redundancy storage unit of storage unit is connected, alternatively at the wordline of abnormal storage unit；Such as Pro-
WL [0] alternatively arrives a certain in WL [n] to a certain, certain two or certain three in Pro-WL [3] at wordline WL [0],
Certain two or certain three (wordline that the wordline of replacement can be abnormal storage unit connection), and target redundancy storage unit connects
The control signal of the control transistor connect can be set to logic 1, so that data point P-VSS can be protected always in target redundancy storage unit
Holding is 0, so that the wordline that the redundant word line of the connection of target redundancy storage unit can be used as storage unit uses；
It is exemplary, it, can be at most using 3 redundant storage units for replacing in the case where 4 redundant storage units
Abnormal storage unit, i.e., must retain at least one redundant storage unit for realizing sense amplifier.
Optionally, Fig. 7 illustrates the connection schematic diagram that sense amplifier is realized using redundant storage unit, exemplary, if
4 redundant storage unit Pro-WL [0] to Pro-WL [3] are used to realize sense amplifier, then each redundant storage unit connects
The redundant word line Pro-WL connect is opened, and the redundant word line of such as each redundant storage unit connection accesses wordline enable signal
(WLEN), and the signal control terminal of the control transistor of redundant storage unit connection accesses sense amplifier enable signal
(SAEN)；
Optionally, Fig. 8 shows the corresponding waveform diagram of Fig. 7；In conjunction with shown in Fig. 5, Fig. 6, Fig. 7 and Fig. 8, redundancy is used
Storage unit realizes sense amplifier, and detailed process can be such that
Redundant storage unit connection redundant word line open, at this time wordline WL [n] choose (i.e. end storage unit connection
Wordline is chosen), storage unit starts to pull down the voltage (to illustrate for the end the BL voltage for pulling down bit line pair) of BL, then BL and BLB
Voltage difference will import redundant storage unit；
Before WLEN and WL [n] shutdown, SAEN is opened, and with the opening of SAEN, the control of redundant storage unit connection is brilliant
The signal control terminal of body pipe can access SAEN, then the data point P-VSS in redundant storage unit pulled down to 0, at this point, one superfluous
Balance storage unit constitutes a latch, that is to say, that a redundant storage unit can be considered a sense amplifier；Pass through BL
With the voltage difference of BLB and the unstable state of redundant storage unit, the voltage of BL can be pulled down to 0 rapidly by redundant storage unit；
Later, stable BL and BLB can have enough voltage differences (i.e. logical zero and logic 1), with other electricity being supplied in chip
Road uses；Here, more for realizing the redundant storage unit of sense amplifier, then the voltage of BL pull down to 0 speed it is faster,
The performance of sense amplifier is higher.
Optionally, Fig. 9 illustrates the optional connection schematic diagram that abnormal storage unit is replaced using redundant storage unit, figure
The storage unit of 9 cross is because abnormal (as damaged), needs to be replaced；At this point, the wordline WL of abnormal storage unit connection can
It is set to logical zero, Tie0 is such as set, in this way, abnormal storage unit can not be opened；As shown in figure 9, storage unit Cell [n-1]
It is damaged with Cell [n], the wordline of storage unit Cell [n-1] and Cell [n] connection is set to Tie0；
And the wordline address of the wordline of abnormal storage unit connection can be decoded and be displaced to, the redundant word line of respective numbers
On, so that the storage unit that the target redundancy storage unit of redundant word line connection is alternatively damaged；Such as wordline WL [n-1] and WL
The wordline address of [n] can be displaced to by decoding, the redundancy of redundant storage unit Pro-Cell [0] and Pro-Cell [1] connection
Wordline；
Remaining redundant storage unit can be used for realizing sense amplifier；Such as Pro-Cell [2] and Pro-Cell [3] can
For realizing sense amplifier, realization process and the signal of corresponding waveform can refer to and be described above, and details are not described herein again.
It is understood that the embodiment of the present invention must retain at least one redundant storage unit for realizing sensitive amplification
Device, therefore the embodiment of the present invention can further divide redundant storage unit, and redundant storage unit is divided into alternatively
Redundant storage unit and can not replacement redundancy storage unit；Wherein, replaceable redundant storage unit can be used for replacing abnormal deposit
Storage unit can only be used to realize sense amplifier without replaceable redundant storage unit；
Optionally, the quantity of replaceable redundant storage unit can be multiple, can not replacement redundancy storage unit quantity
It can be at least one；When the quantity of abnormal storage unit is greater than or equal to the quantity of replaceable redundant storage unit, this
Replaceable redundant storage unit is used only in inventive embodiments, replaces the abnormal storage unit of respective numbers, retains not replaceable
Redundant storage unit realizes sense amplifier；
It is exemplary, such as 4 redundant storage units are being set, wherein 2 are replaceable redundant storage unit, in addition 2 are
Can not be in the case where replacement redundancy storage unit, if abnormal storage unit is greater than or equal to 2, the embodiment of the present invention only makes
The storage unit that 2 exceptions are replaced with 2 replaceable redundant storage units, can not replacement redundancy storage list without employing 2
Member replaces abnormal storage unit, i.e., it is minimum retain 2 can not replacement redundancy storage unit realize sense amplifier；To,
The embodiment of the present invention can be in the case where retaining the sense amplifier function of memory, and the efficient of maximum possible utilizes redundant storage
Unit, and the brought memory performance loss of exception for reducing storage unit；
When the quantity of abnormal storage unit is less than the quantity of replaceable redundant storage unit, the embodiment of the present invention can make
With replaceable redundant storage unit corresponding with the abnormal quantity of storage unit, replace abnormal storage unit, it is remaining can
Replacement redundancy storage unit is combinable can not replacement redundancy storage unit realization sense amplifier；
It is exemplary, such as 4 redundant storage units are being set, wherein 2 are replaceable redundant storage unit, in addition 2 are
Can not in the case where replacement redundancy storage unit, if abnormal storage unit is 1, the embodiment of the present invention can be used 1 can
The abnormal storage unit of replacement redundancy storage unit replacement, and can not using remaining 1 replaceable redundant storage unit and 2
Replacement redundancy storage unit realizes sense amplifier, to realize the efficient utilization of redundant storage unit.
As a kind of optional realization of disclosure of the embodiment of the present invention, the embodiment of the present invention can pass through setting control electricity
Road, the abnormal storage unit of control redundant storage unit replacement, and control redundant storage unit and realize sense amplifier；It is optional
, Figure 10 shows another structural schematic diagram of memory provided in an embodiment of the present invention, in conjunction with shown in Fig. 5 and Figure 10, this hair
The memory that bright embodiment provides can also include: control circuit 20；
Control circuit 20 can be with the wordline WL of storage unit Cell, the redundant word line Pro- of redundant storage unit Pro-Cell
WL controls the signal control terminal connection of transistor；Replacement exception is realized to control redundant storage unit by control circuit 20
Storage unit, and control redundant storage unit realize sense amplifier.
Optionally, in the case where realizing sense amplifier using redundant storage unit, Figure 11 shows implementation of the present invention
One optional process of the circuit control method that example provides, which can be realized by control circuit, in conjunction with Figure 10 and figure
Shown in 11, this method may include:
Step S100, when there is no abnormal storage unit, the redundant word line of redundant storage unit connection is accessed into word
Line enable signal.
Optionally, the redundant word line that control circuit can be connected to redundant storage unit inputs wordline enable signal WLEN, from
And the wordline same-phase that redundant word line is opened, and is connect with storage unit Cell.
Step S110, the signal control terminal of the control transistor of redundant storage unit connection is accessed, sense amplifier makes
It can signal.
Optionally, control circuit can input SAEN signal to control transistor.
Optionally, step S100 and step S110 can not also distinguish sequencing or sequencing is reverse.
Optionally, in the case where replacing abnormal storage unit using redundant storage unit, Figure 12 shows the present invention
The another optional process for the circuit control method that embodiment provides, which can be realized by control circuit, in conjunction with figure
Shown in 10 and Figure 12, this method may include:
Step S200, when there is abnormal storage unit, the wordline of abnormal storage unit connection is set to logical zero.
After the wordline of abnormal storage unit connection is set to logical zero, abnormal storage unit will be unable to open；Optionally,
Logical zero may be considered a kind of optional form of second signal, and second signal can be the signal opposite with the first signal logic,
First signal can be logic 1, and second signal can be logical zero, and the signal of the logic 1 below related to may be considered the first letter
Number a kind of optional form, the signal of the logical zero below related to may be considered a kind of optional form of second signal；Certainly,
The form of the first signal and the second signal is not limited thereto in the embodiment of the present invention, as long as the first signal and the second signal logic
It is opposite.
Step S210, by the wordline address of the wordline of abnormal storage unit connection, target redundancy is displaced to by decoding
The redundant word line of storage unit connection, and the signal control terminal for the control transistor that target redundancy storage unit connects is set to and is patrolled
Collect 1.
Optionally, step S200 and step S210 can not also distinguish sequencing or sequencing is reverse.
Optionally, target redundancy storage unit can be determined from replaceable redundant storage unit, specifically how selection target
Redundant storage unit can refer to previously for replaceable redundant storage unit and can not replacement redundancy storage unit part description,
Details are not described herein again；
It is shifted and is decoded by wordline, the wordline address for the wordline that the embodiment of the present invention can connect abnormal storage unit,
It is displaced to the redundant word line of target redundancy storage unit connection, to replace abnormal storage list using target redundancy storage unit
Member；Also, the signal control terminal of the control transistor of target redundancy storage unit connection is set to Tie1, no longer access SAEN letter
Number.
It is understood that in redundant storage unit can not replacement redundancy storage unit, can also according to shown in Figure 11 side
Method realizes sense amplifier；And when the quantity of replaceable redundant storage unit is greater than abnormal storage unit, it is not used for replacing
The replaceable redundant storage unit of abnormal storage unit, can be according to method shown in Figure 11, and can not replacement redundancy storage unit
Sense amplifier is realized together.
In a kind of optional example, control circuit may include: the decoding circuit for generating word line decoding signal, generate wordline
The wordline enable signal generation circuit of enable signal, the sense amplifier enable signal for generating sense amplifier enable signal generate
Circuit；And control circuit can by setting with door, multiplexer realize decoding circuit, wordline enable signal generation circuit,
The connection of sense amplifier enable signal generation circuit and wordline, the signal control terminal of redundant word line, control transistor；
Optionally, Figure 13 shows the another structural schematic diagram of memory provided in an embodiment of the present invention, in conjunction with Figure 10 and
Shown in Figure 13, in memory provided in an embodiment of the present invention, redundant storage unit can be divided into replaceable redundant storage unit
(Figure 13 illustratively indicates replaceable redundant storage unit with redundant storage unit Pro-Cell [0] and Pro-Cell [1]), and
Can not replacement redundancy storage unit (Figure 13 is illustratively indicated not with redundant storage unit Pro-Cell [2] and Pro-Cell [3]
Replaceable redundant storage unit)；
Control circuit 20 may include:
Decoding circuit 21, decoding circuit 21 can realize the decoding (such as decoded signal WLE [0] arrive WLE [n]) and not of wordline WL
Decoding (such as decoded signal Pro-WLE [0] and Pro-WLE of the redundant word line Pro-WL of replaceable redundant storage unit connection
[1]), so that the wordline address of the wordline WL of abnormal storage unit can be decoded displacement when there is abnormal storage unit
To can not replacement redundancy storage unit connection redundant word line；Optionally, X-direction decoder, X-direction can be selected in decoding circuit 21
It may be considered the line direction of memory；
Wordline enable signal generation circuit 22, for generating wordline enable signal WLEN, such as wordline clock pulses (Word
Line Clock Pulse), wordline enable signal cooperates decoding circuit, may be implemented to select word in [n] from wordline WL [0] to WL
Line；
Sense amplifier enable signal generation circuit 23, for generating sense amplifier enable signal；
Two inputs and door 24；
One or two road transmitter 25；
Two or two road transmitter 26.
With continued reference to Figure 13, storage unit connection wordline can by two input with door 24 (two input with door be only and door
A kind of optional form, the embodiment of the present invention can also support other kinds of and door), with decoding circuit 21 and wordline enable signal
Generation circuit 22 connects；Specifically, two inputs connect the wordline of storage unit Cell, first input end connection with the output end of door
Wordline enable signal generation circuit 22, for receiving wordline enable signal (WLEN as shown in the figure), the connection decoding of the second input terminal
Circuit, for receiving word line decoding signal (WLE [0] as shown in the figure arrives WLE [n])；
The redundant word line of replaceable redundant storage unit connection, can (two road transmitters be only by the one or two road transmitter 25
It is a kind of optional form of multiplexer, the embodiment of the present invention can also support other kinds of multiplexer), with decoding electricity
Road 21 and wordline enable signal generation circuit 22 connect；Specifically, the output end of the one or two road transmitter connects, replaceable redundancy
The redundant word line of storage unit, first input end (such as logical zero input terminal) connects wordline enable signal generation circuit, for receiving
Wordline enable signal (WLEN as shown in the figure), the second input terminal (such as 1 input terminal of logic) connects decoding circuit, for receiving wordline
Decoded signal (Pro-WLE [0] as shown in the figure arrives Pro-WLE [1])；
The signal control terminal of the transistor of replaceable redundant storage unit connection, can by the two or two road transmitter 26, with
Decoding circuit 21 and sense amplifier enable signal generation circuit 23 connect；Specifically, the output end of the two or two road transmitter 26
Connection, the signal control terminal of the transistor of replaceable redundant storage unit connection, first input end (such as logical zero input terminal) connection
Sense amplifier enable signal generation circuit 23, for receiving SAEN signal, the second input terminal (such as 1 input terminal of logic) connection is translated
Code circuit 21, for receiving Tie1 signal；
Can not replacement redundancy storage unit redundant word line, wordline enable signal generation circuit 22 is directly connected to, for connecing
Receive wordline enable signal, can not replacement redundancy storage unit connection control transistor signal control terminal, be directly connected to sensitive
Amplifier enable signal generation circuit 23, for receiving SAEN signal；As it can be seen that can not replacement redundancy storage unit can keep receiving
SAEN signal and WLEN signal are needed without such as replaceable redundant storage unit through the one or two road transmitter and the two or two tunnel
Transmitter carry out signal behavior, therefore the embodiment of the present invention can keep can not replacement redundancy storage unit realize sense amplifier.
It is realized using redundant storage unit sensitive based on memory shown in Figure 13 when not there is no abnormal storage unit
The method flow of amplifier, can be as shown in figure 14, and corresponding signal trend can refer to shown in Figure 15, and Figure 15 dotted line shows signal
Trend；In conjunction with shown in Figure 13, Figure 14 and Figure 15, this method may include:
Step S300, the wordline enable signal of the one or two road transmitter selection first input end input.
Optionally, logical zero input terminal may be selected in each one or two road transmitter, then wordline enable signal imports not replaceable superfluous
The redundant word line of balance storage unit connection.
Step S310, the SAEN signal of the two or two road transmitter selection first input end input.
Optionally, logical zero input terminal may be selected in each two or two road transmitter, then can import can not replacement redundancy for SAEN signal
The signal control terminal of the control transistor of storage unit connection, to control the signal control terminal of transistor by SAEN signal pipe
Control.
In conjunction with Figure 15 as can be seen that redundant storage unit Pro-Cell [0] is arrived when not there is no abnormal storage unit
Pro-Cell [3] realizes sense amplifier, and the signal control of the control transistor M connected terminates to SAEN signal, and can replace
The redundant word line that redundant storage unit Pro-Cell [0] arrives Pro-Cell [1] connection is changed, WLEN is accessed；Working condition at this time
It is to choose storage unit Cell [n] (choosing end storage unit at this time), then pulls down the voltage of BL and BLB, Pro-
Cell [0] is used as SA to Pro-Cell [3], and signal is amplified and is exported.
It is replaced when there is abnormal storage unit using replaceable redundant storage unit based on memory shown in Figure 13
The method flow of abnormal storage unit can be as shown in figure 16, and corresponding signal trend can refer to shown in Figure 17, and Figure 17 dotted line shows
Signal trend is gone out；In conjunction with shown in Figure 13, Figure 16 and Figure 17, method may include:
Step S400, the wordline address for the wordline that decoding circuit connects the storage unit of damage, decoding are displaced to target
The redundant word line of redundant storage unit connection.
As shown in figure 17, storage unit Cell [n-1] and Cell [n] are abnormal, then the connection of storage unit Cell [n-1]
The wordline address of wordline WL [n-1] can be decoded and be displaced to redundant word line Pro-WL [0], such as scheme WLE [n-1] and arrive Pro-WLE
[0] line signal, the wordline address of the wordline WL [n] of storage unit Cell [n] can be decoded and be displaced to redundant word line Pro-
WL [1], the line for such as scheming WLE [n] to Pro-WLE [1] are illustrated.
Optionally, also the wordline that the storage unit of damage connects can be set to Tie0.
Step S410, the one or two road transmitter of target redundancy storage unit selects the second input terminal, deposits to target redundancy
The redundant word line of storage unit imports word line decoding signal.
As shown in figure 17,1 input terminal of logic may be selected in the one or two road transmitter of target redundancy storage unit.
Step S420, the two or two road transmitter of target redundancy storage unit selects the second input terminal, and target redundancy is deposited
The signal control terminal of the control transistor of storage unit connection is set to logic 1.
As shown in figure 17, the two or two road transmitter of target redundancy storage unit selects 1 input terminal of logic.
In conjunction with Figure 17 as can be seen that replaceable redundancy is deposited when two storage unit Cell [n-1] and Cell [n] are damaged
Storage unit Pro-Cell [0] and Pro-Cell [1] is used as target redundancy storage unit, for replacing storage unit Cell [n-1]
With Cell [n], then the signal control terminal of the control transistor M of Pro-Cell [0] and Pro-Cell [1] connection is set to Tie1
(meanwhile the wordline of Cell [n-1] and Cell [n] connection can also be set to Tie0), without replaceable redundant storage unit Pro-
Cell [2] and Pro-Cell [3] realizes sense amplifier.Working condition at this time is to choose redundant storage unit Pro-Cell
[1] it (chooses end storage unit at this time), then pulls down the voltage of BL and BLB, Pro-Cell [2] and Pro-Cell [3]
As SA, signal is amplified and is exported.
It should be noted that the placement location of control transistor, however it is not limited to it is above-mentioned diagrammatically shown, as long as setting is storing
Outside cell array, and it can be connect with redundant storage unit；Optionally, control transistor and the redundant storage unit that is connect
Position it is closer, then the control effect for controlling crystal is better.
Optionally, although above-mentioned example is with BL and BLB scene, and for carrying out signal amplification output, this both-end amplifies
Output scene is only a kind of optional example of the embodiment of the present invention, and the embodiment of the present invention can also be applicable in Single-end output circuit,
Single-end output circuit can carry out logic output by a BL or BLB.
Optionally, in order to improve the speed and efficiency of memory, the embodiment of the present invention can also will access redundant word line
The voltage of WLEN carries out boosting processing, optional waveform signal as shown in figure 18.
Optionally, in order to improve the speed and efficiency of memory, in redundant storage unit, the embodiment of the present invention can also will
Back end Q in the redundant storage unit of 6T structure is connected with bit line BL, and back end QB is connected with antiposition line BLB, optional
6T structural representation as shown in figure 19.
Memory construction provided in an embodiment of the present invention, it can be achieved that redundant storage unit realize sense amplifier, thus
The circuit structure that traditional sense amplifier is omitted in memory realizes sensitive amplification by the lesser redundant storage unit of area
Device, and the storage unit abnormal with the replacement of partial redundance storage unit, can on the basis of efficiently using redundant storage unit,
Area ratio shared by storage unit in memory is improved, the area consumption of memory is reduced, realizes the efficient benefit of memory area
With.
As a kind of optional realization, the embodiment of the present invention also provides a kind of chip, which may include described above
Memory provided in an embodiment of the present invention.
As a kind of optional realization, the embodiment of the present invention is directed to provided memory, corresponding circuit control can also be provided
Method processed, correlation method content, which can refer to, to be described above, and details are not described herein again.
Described above is multiple example schemes provided in an embodiment of the present invention, each optional side of each example scheme introduction
Formula can be combined with each other in the absence of conflict, cross reference, thus extend a variety of possible example schemes, these
It is considered disclosure of the embodiment of the present invention, disclosed embodiment scheme.
Although the embodiment of the present invention discloses as above, present invention is not limited to this.Anyone skilled in the art, not
It is detached from the spirit and scope of the present invention, can make various changes or modifications, therefore protection scope of the present invention should be with right
It is required that subject to limited range.
Claims (15)
1. a kind of memory characterized by comprising
Wordline；
Redundant word line；
Connect the storage unit of the wordline；
Connect the redundant storage unit of the redundant word line；
Wherein, when there is no abnormal storage unit, sense amplifier is realized using the redundant storage unit；When there are different
When normal storage unit, retains at least one redundant storage unit and realize sense amplifier, and deposited using remaining target redundancy
The abnormal storage unit of storage unit replacement.
2. memory according to claim 1, which is characterized in that further include: connect the control of the redundant storage unit
Transistor；
Wherein, if the signal control terminal of the control transistor of redundant storage unit connection accesses sense amplifier enable signal,
The redundant storage unit is for realizing sense amplifier；If the signal control terminal of the control transistor of redundant storage unit connection
The first signal is accessed, the redundant storage unit is for replacing abnormal storage unit.
3. memory according to claim 2, which is characterized in that further include: control circuit；The control circuit connects institute
State wordline, the signal control terminal of the redundant word line and the control transistor；
The control circuit, the control for when there is no abnormal storage unit, the redundant storage unit to be connected are brilliant
The signal control terminal of body pipe accesses sense amplifier enable signal；
When there is abnormal storage unit, the signal for the control transistor that at least one redundant storage unit connects is controlled
Sense amplifier enable signal is accessed at end；By the wordline address of the wordline of abnormal storage unit connection, it is displaced to by decoding
The redundant word line that target redundancy storage unit is connected, and the signal control for controlling transistor that target redundancy storage unit is connected
System is terminated into the first signal.
4. memory according to claim 3, which is characterized in that the control circuit is also used to:
When there is no abnormal storage unit, the redundant word line access wordline that the redundant storage unit is connected is enabled to be believed
Number；
When there is abnormal storage unit, the redundant word line access wordline of at least one described redundant storage unit connection is made
Energy signal, and the wordline of abnormal storage unit connection is set to second signal, the first signal is that logic is opposite with second signal
Signal.
5. memory according to claim 4, which is characterized in that the control circuit includes: to generate word line decoding signal
Decoding circuit, generate wordline enable signal wordline enable signal generation circuit, generate sense amplifier enable signal spirit
Quick amplifier enable signal generation circuit, with door, the first multiplexer and the second multiplexer；
The redundant storage unit includes: replaceable redundant storage unit and can not replacement redundancy storage unit；Target redundancy is deposited
Storage unit is determined from the replaceable redundant storage unit；
The decoding circuit and the wordline enable signal generation circuit are by the way that with door, the wordline connecting with storage unit is connected
It connects；
The decoding circuit and the wordline enable signal generation circuit are by the first multiplexer, with replaceable redundant storage
The redundant word line of unit connection is connected；
The decoding circuit and the sense amplifier enable signal generation circuit are and replaceable superfluous by the second multiplexer
The signal control terminal of the control transistor of balance storage unit connection is connected；
It is described can not replacement redundancy storage unit connection redundant word line, directly with the wordline enable signal generation circuit connect
It connects；It is described can not the connection of replacement redundancy storage unit control transistor signal control terminal, it is directly enabled with sense amplifier
Signal generating circuit is connected.
6. memory according to claim 5, which is characterized in that described and door is two inputs and door；It is described two input with
The first input end of door is connect with the wordline enable signal generation circuit, and the second input terminal is connected with the decoding circuit,
The wordline that output end is connect with storage unit is connected；
First multiplexer is the one or two road transmitter；The first input end and the word of one or the two road transmitter
The connection of line enable signal generation circuit, the second input terminal are connected with the decoding circuit, output end and replaceable redundant storage
The redundant word line of unit connection is connected；
Second multiplexer is the two or two road transmitter, and the first input end of the two or the two road transmitter is put with sensitive
Big device enable signal generation circuit connection, the second input terminal is connected with the decoding circuit, to receive the first signal, output end
The signal control terminal for the control transistor connecting with replaceable redundant storage unit is connected.
7. memory according to claim 5 or 6, which is characterized in that the one or the two road transmitter, for that ought not exist
When the storage unit of exception, the wordline enable signal of first input end input is selected；When there is abnormal storage unit, selection
Second input terminal, to import word line decoding signal to redundant word line；
Two or the two road transmitter, for selecting the SAEN of first input end input when not there is no abnormal storage unit
Signal；When there is abnormal storage unit, the second input terminal is selected, with the signal control of the control transistor connected to output end
End processed imports the first signal；
The decoding circuit is used for, when there is abnormal storage unit, by the wordline of the wordline of abnormal storage unit connection
Address, by decoding the redundant word line for being displaced to target redundancy storage unit and being connected.
8. memory according to claim 2, which is characterized in that the control transistor is NMOS tube；The control is brilliant
The grid of body pipe is control signal end, and drain electrode connects the redundant storage unit, source electrode ground connection.
9. memory according to claim 8, which is characterized in that the redundant storage unit includes:
First PMOS tube P1, the first NMOS tube N1, the second PMOS tube P2, the second NMOS tube N2, third NMOS tube N3 and the 4th
NMOS tube N4；
The grid of first PMOS tube P1, the grid of the first NMOS tube N1, the drain electrode of the second PMOS tube P2, the leakage of the second NMOS tube N2
Pole is connected with the source electrode of third NMOS tube N3, forms back end Q；The grid of the grid of second PMOS tube P2, the second NMOS tube N2
Pole, the drain electrode of the first PMOS tube P1, the drain electrode of the first NMOS tube N1, the source electrode connection of the 4th NMOS tube N4, form back end
QB；
The grid of third NMOS tube N3 and the 4th NMOS tube N4 are connect with wordline WL, and the drain electrode of third NMOS tube N3 and bit line BL connect
It connects, the drain electrode of the 4th NMOS tube N4 is connect with bit line BLB；The source electrode of the source electrode of first PMOS tube P1 and the second PMOS tube P2 and electricity
Source voltage VDD connection；The drain electrode of the source electrode of the source electrode of first NMOS tube N1 and the second NMOS tube N2 and the control transistor connects
It connects.
10. memory according to claim 1, which is characterized in that further include:
The multipair bit line pair being connected in parallel with the wordline and redundant word line.
11. a kind of chip characterized by comprising the described in any item memories of claim 1-10.
12. a kind of circuit control method, which is characterized in that be based on the described in any item memories of claim 1-10, the side
Method includes:
When there is no when the storage unit of exception, use redundant storage unit realization sense amplifier in memory；
When there is abnormal storage unit in memory, retaining at least one redundant storage unit and realizing sense amplifier, and
Abnormal storage unit is replaced using remaining target redundancy storage unit.
13. circuit control method according to claim 12, which is characterized in that described to realize spirit using redundant storage unit
Quick amplifier includes:
By the signal control terminal of the control transistor of redundant storage unit connection, sense amplifier enable signal is accessed；
It is described to replace abnormal storage unit using remaining target redundancy storage unit and include:
By the wordline address of the wordline of abnormal storage unit connection, target redundancy storage unit is displaced to by decoding and is connected
Redundant word line, and by target redundancy storage unit connect control transistor signal control terminal access the first signal.
14. circuit control method according to claim 13, which is characterized in that described to realize spirit using redundant storage unit
Quick amplifier further include:
The redundant word line of redundant storage unit connection is accessed into wordline enable signal；
The method also includes:
When there is abnormal storage unit in memory, the wordline of abnormal storage unit connection is set to second signal, the
One signal and second signal are the opposite signal of logic.
15. circuit control method according to claim 13, which is characterized in that the redundant storage unit includes: that can replace
Change redundant storage unit and can not replacement redundancy storage unit；Target redundancy storage unit is from the replaceable redundant storage unit
Middle determination；
It is described to include: by the redundant word line access wordline enable signal of redundant storage unit connection
The wordline enable signal for selecting the first input end of the one or two road transmitter to access, the first of the one or the two road transmitter
Input terminal accesses wordline enable signal, and the second input terminal accesses word line decoding signal, and output end connects replaceable redundant storage list
The redundant word line of member；
The signal control terminal of the control transistor by redundant storage unit connection, accesses sense amplifier enable signal packet
It includes:
The sense amplifier enable signal for selecting the first input end of the two or two road transmitter to access, the two or the two road transmitter
First input end access sense amplifier enable signal, the second input terminal accesses the first signal, and output end connection is replaceable superfluous
The signal control terminal of the control transistor of balance storage unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910314248.8A CN110070904B (en) | 2019-04-18 | 2019-04-18 | Memory, chip and circuit control method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910314248.8A CN110070904B (en) | 2019-04-18 | 2019-04-18 | Memory, chip and circuit control method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110070904A true CN110070904A (en) | 2019-07-30 |
| CN110070904B CN110070904B (en) | 2021-01-29 |
Family
ID=67368159
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910314248.8A Active CN110070904B (en) | 2019-04-18 | 2019-04-18 | Memory, chip and circuit control method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110070904B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023071144A1 (en) * | 2021-10-29 | 2023-05-04 | 长鑫存储技术有限公司 | Memory structure and memory |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6191983B1 (en) * | 1997-06-19 | 2001-02-20 | Hitachi, Ltd. | Semiconductor memory |
| CN1366308A (en) * | 2001-01-17 | 2002-08-28 | 株式会社东芝 | Semiconductor storage formed for optimizing testing technique and rebundance technique |
| WO2010084539A1 (en) * | 2009-01-20 | 2010-07-29 | パナソニック株式会社 | Semiconductor memory |
| CN103632729A (en) * | 2012-08-27 | 2014-03-12 | 三星电子株式会社 | Semiconductor memory device and system having redundancy cells |
| CN103956179A (en) * | 2014-05-12 | 2014-07-30 | 北京兆易创新科技股份有限公司 | Sense amplifier and memory system using same |
| CN106205693A (en) * | 2014-12-19 | 2016-12-07 | 爱思开海力士有限公司 | Semiconductor storage unit |
| CN108564978A (en) * | 2018-04-20 | 2018-09-21 | 电子科技大学 | A kind of reading circuit with redundancy structure |
| CN109036490A (en) * | 2017-06-12 | 2018-12-18 | 三星电子株式会社 | Memory devices and its programmed method including OTP memory cell |
-
2019
- 2019-04-18 CN CN201910314248.8A patent/CN110070904B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6191983B1 (en) * | 1997-06-19 | 2001-02-20 | Hitachi, Ltd. | Semiconductor memory |
| CN1366308A (en) * | 2001-01-17 | 2002-08-28 | 株式会社东芝 | Semiconductor storage formed for optimizing testing technique and rebundance technique |
| WO2010084539A1 (en) * | 2009-01-20 | 2010-07-29 | パナソニック株式会社 | Semiconductor memory |
| CN103632729A (en) * | 2012-08-27 | 2014-03-12 | 三星电子株式会社 | Semiconductor memory device and system having redundancy cells |
| CN103956179A (en) * | 2014-05-12 | 2014-07-30 | 北京兆易创新科技股份有限公司 | Sense amplifier and memory system using same |
| CN106205693A (en) * | 2014-12-19 | 2016-12-07 | 爱思开海力士有限公司 | Semiconductor storage unit |
| CN109036490A (en) * | 2017-06-12 | 2018-12-18 | 三星电子株式会社 | Memory devices and its programmed method including OTP memory cell |
| CN108564978A (en) * | 2018-04-20 | 2018-09-21 | 电子科技大学 | A kind of reading circuit with redundancy structure |
Non-Patent Citations (1)
| Title |
|---|
| NICOLA LUPO: "A Cross-Coupled Redundant Sense Amplifier for Radiation Hardened SRAMs", 《 2017 NEW GENERATION OF CAS (NGCAS)》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023071144A1 (en) * | 2021-10-29 | 2023-05-04 | 长鑫存储技术有限公司 | Memory structure and memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110070904B (en) | 2021-01-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7440313B2 (en) | Two-port SRAM having improved write operation | |
| CN101506894B (en) | Figure memories with selective precharge and operation method thereof | |
| CN1126104C (en) | Low power memory including selective precharge circuit | |
| CN105845168A (en) | Methods and apparatus for reducing power consumption in memory circuitry by controlling precharge duration | |
| US7193924B2 (en) | Dual-port static random access memory having improved cell stability and write margin | |
| US7336546B2 (en) | Global bit select circuit with dual read and write bit line pairs | |
| CN101202104B (en) | Dynamic random access memory circuit , integrated circuit and method for reading and writing memory unit | |
| CN101009135A (en) | Semiconductor memory device having reduced voltage coupling between bit lines | |
| EP0594347A2 (en) | Synchronous static random access memory | |
| US20080158938A1 (en) | Memory cells with lower power consumption during a write operation | |
| CN101303888A (en) | Sram with switchable power supply sets of voltages | |
| US20140036610A1 (en) | Devices and methods for controlling memory cell pre-charge operations | |
| IL129310A (en) | Random access memory and process for writing to and reading from the same | |
| CN101727973B (en) | Semiconductor memory apparatus | |
| CN115810374A (en) | Memory circuit and memory computing circuit with BCAM addressing and logic operation functions | |
| US6396764B1 (en) | Segmented memory architecture and systems and methods using the same | |
| CN114038492A (en) | Multi-phase sampling memory computing circuit | |
| CN110070904A (en) | A kind of memory, chip and circuit control method | |
| US20220068371A1 (en) | Pseudo-triple-port sram | |
| CN101542629A (en) | Memories with front end precharge | |
| CN118215964A (en) | Memory with single ended sensing using reset-set latches | |
| US11302388B2 (en) | Decoding for pseudo-triple-port SRAM | |
| US11615837B2 (en) | Pseudo-triple-port SRAM datapaths | |
| CN101727961B (en) | Imbedded reconfigurable memorizer in programmable gate array | |
| US6434069B1 (en) | Two-phase charge-sharing data latch for memory circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 300384 Tianjin Binhai New Area Tianjin Huayuan Industrial Zone No. 18 Haitai West Road North 2-204 Industrial Incubation-3-8 Applicant after: Haiguang Information Technology Co.,Ltd. Address before: 300384 Tianjin Binhai New Area Tianjin Huayuan Industrial Zone No. 18 Haitai West Road North 2-204 Industrial Incubation-3-8 Applicant before: HAIGUANG INFORMATION TECHNOLOGY Co.,Ltd. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CB03 | Change of inventor or designer information | ||
| CB03 | Change of inventor or designer information |
Inventor after: Huang Ruifeng Inventor after: Yang Changkai Inventor after: Wang Jianlong Inventor before: Huang Ruifeng Inventor before: Yang Changkai Inventor before: Wang Jianlong |